From: Daniel Henrique Barboza Date: Tue, 16 Jun 2026 23:59:36 +0000 (-0300) Subject: hw/riscv/sifive_u.c: use intc_phandle in plic creation X-Git-Tag: v11.1.0-rc0~34^2~25 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=64d98e0797c821da99894517215539dea2ade7cd;p=thirdparty%2Fqemu.git hw/riscv/sifive_u.c: use intc_phandle in plic creation The info about intc_phandles for each CPU is already stored in the intc_phandles array. We don't need to fetch them again using qemu_fdt_get_phandle(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260616235939.1358663-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index fda9a09f06..b3468254f5 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -199,20 +199,16 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, plic_phandle = phandle++; cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); for (cpu = 0; cpu < ms->smp.cpus; cpu++) { - nodename = - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); /* cpu 0 is the management hart that does not have S-mode */ if (cpu == 0) { - cells[0] = cpu_to_be32(intc_phandle); + cells[0] = cpu_to_be32(intc_phandles[cpu]); cells[1] = cpu_to_be32(IRQ_M_EXT); } else { - cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); + cells[cpu * 4 - 2] = cpu_to_be32(intc_phandles[cpu]); cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); - cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); } - g_free(nodename); } nodename = g_strdup_printf("/soc/interrupt-controller@%lx", (long)memmap[SIFIVE_U_DEV_PLIC].base);