From: Abel Vesa Date: Fri, 20 Mar 2026 11:16:43 +0000 (+0200) Subject: arm64: dts: qcom: glymur: Describe display-related nodes X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=652b7210b8b92eaf121d4ed12f99e81cedbacb0a;p=thirdparty%2Fkernel%2Fstable.git arm64: dts: qcom: glymur: Describe display-related nodes The MDSS (Mobile Display SubSystem) on Glymur provides four DisplayPort controllers. Describe them together with the display controller and eDP PHY. Also add the combo PHY link and vco_div clocks to the display clock controller, and connect the PHYs and DP endpoints in the graph. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260320-dts-qcom-glymur-crd-add-edp-v7-1-ca415560447e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 7807f9155156..2c9d10f2e987 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2367,6 +2367,28 @@ status = "disabled"; }; + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0x0 0x00faac00 0x0 0x1d0>, + <0x0 0x00faa400 0x0 0x128>, + <0x0 0x00faa800 0x0 0x128>, + <0x0 0x00faa000 0x0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + usb_0_hsphy: phy@fd3000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -2434,6 +2456,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2507,6 +2530,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; }; }; }; @@ -3770,6 +3794,7 @@ reg = <2>; usb_2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -4134,20 +4159,445 @@ status = "disabled"; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1de0 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0x0 0x0ae01000 0x0 0x93000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-205000000 { + opp-hz = /bits/ 64 <205000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-660000000 { + opp-hz = /bits/ 64 <660000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-717000000 { + opp-hz = /bits/ 64 <717000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf54000 0x0 0x200>, + <0x0 0xaf54200 0x0 0x200>, + <0x0 0xaf55000 0x0 0xc00>, + <0x0 0xaf56000 0x0 0x400>, + <0x0 0xaf57000 0x0 0x400>, + <0x0 0xaf58000 0x0 0x400>, + <0x0 0xaf59000 0x0 0x400>, + <0x0 0xaf5a000 0x0 0x600>, + <0x0 0xaf5b000 0x0 0x600>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf5c000 0x0 0x200>, + <0x0 0xaf5c200 0x0 0x200>, + <0x0 0xaf5d000 0x0 0xc00>, + <0x0 0xaf5e000 0x0 0x400>, + <0x0 0xaf5f000 0x0 0x400>, + <0x0 0xaf60000 0x0 0x400>, + <0x0 0xaf61000 0x0 0x400>, + <0x0 0xaf62000 0x0 0x600>, + <0x0 0xaf63000 0x0 0x600>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp2: displayport-controller@af64000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af64000 0x0 0x200>, + <0x0 0x0af64200 0x0 0x200>, + <0x0 0x0af65000 0x0 0xc00>, + <0x0 0x0af66000 0x0 0x400>, + <0x0 0x0af67000 0x0 0x400>, + <0x0 0x0af68000 0x0 0x400>, + <0x0 0x0af69000 0x0 0x400>, + <0x0 0x0af6a000 0x0 0x600>, + <0x0 0x0af6b000 0x0 0x600>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_2_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp3: displayport-controller@af6c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af6c000 0x0 0x200>, + <0x0 0x0af6c200 0x0 0x200>, + <0x0 0x0af6d000 0x0 0xc00>, + <0x0 0x0af6e000 0x0 0x400>, + <0x0 0x0af6f000 0x0 0x400>, + <0x0 0x0af70000 0x0 0x400>, + <0x0 0x0af71000 0x0 0x400>, + <0x0 0x0af72000 0x0 0x600>, + <0x0 0x0af73000 0x0 0x600>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + }; + }; + }; + }; + }; dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>, + <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>, <0>, /* dsi0 */ <0>, <0>, /* dsi1 */