From: Lijo Lazar Date: Thu, 26 Mar 2026 05:41:39 +0000 (+0530) Subject: drm/amdgpu: Move validation of reserve region info X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6845355a08c2dc7e5af3c37b7d8f61afbfec1939;p=thirdparty%2Flinux.git drm/amdgpu: Move validation of reserve region info Keep validation of reserved regions also as part of filling details. If the information is invalid, size is kept as 0 so that it's not considered for reservation. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8d072eb4af78..212b489845a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1748,6 +1748,8 @@ static void amdgpu_ttm_init_mem_train_resv_region(struct amdgpu_device *adev) static void amdgpu_ttm_init_vram_resv_regions(struct amdgpu_device *adev) { + uint64_t vram_size = adev->gmc.visible_vram_size; + /* Initialize memory reservations as required for VGA. * This is used for VGA emulation and pre-OS scanout buffers to * avoid display artifacts while transitioning between pre-OS @@ -1756,6 +1758,12 @@ static void amdgpu_ttm_init_vram_resv_regions(struct amdgpu_device *adev) amdgpu_gmc_init_vga_resv_regions(adev); amdgpu_ttm_init_fw_resv_region(adev); amdgpu_ttm_init_mem_train_resv_region(adev); + + if (adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size > vram_size) + adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size = 0; + + if (adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size > vram_size) + adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size = 0; } int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev, @@ -2122,27 +2130,17 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) *The reserved vram for firmware must be pinned to the specified *place on the VRAM, so reserve it early. */ - if (adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size > - adev->gmc.visible_vram_size) { - adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size = 0; - } else { - r = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_VRAM_USAGE); - if (r) - return r; - } + r = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_VRAM_USAGE); + if (r) + return r; /* * The reserved VRAM for the driver must be pinned to a specific * location in VRAM, so reserve it early. */ - if (adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size > - adev->gmc.visible_vram_size) { - adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size = 0; - } else { - r = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE); - if (r) - return r; - } + r = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE); + if (r) + return r; /* * only NAVI10 and later ASICs support IP discovery.