From: Pan Li <pan2.li@intel.com>
Date: Wed, 22 Jul 2026 01:32:21 +0000 (+0800)
Subject: RISC-V: Add test cases for vfwcvt.rtz.x.f.v reg overlap
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=685386593ce1baba1c7585e9fb5ecfa4ccbc9846;p=thirdparty%2Fgcc.git

RISC-V: Add test cases for vfwcvt.rtz.x.f.v reg overlap

Add test cases for register group overlap, please
note it is not overlap as much as possible.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-mf2.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m1.c
new file mode 100644
index 00000000000..e121b893789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m1,
+  vfloat16m1_t,
+  vint32m2_t,
+  __riscv_vle16_v_f16m1,
+  __riscv_vfwcvt_rtz_x_f_v_i32m2,
+  __riscv_vse32_v_i32m2,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v0,v1([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v2,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m2.c
new file mode 100644
index 00000000000..70eb8751fe2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m2,
+  vfloat16m2_t,
+  vint32m4_t,
+  __riscv_vle16_v_f16m2,
+  __riscv_vfwcvt_rtz_x_f_v_i32m4,
+  __riscv_vse32_v_i32m4,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v0,v2([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v4,v6} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m4.c
new file mode 100644
index 00000000000..acbb0953f69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m4,
+  vfloat16m4_t,
+  vint32m8_t,
+  __riscv_vle16_v_f16m4,
+  __riscv_vfwcvt_rtz_x_f_v_i32m8,
+  __riscv_vse32_v_i32m8,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v8,v12} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf2.c
new file mode 100644
index 00000000000..c7ef4ccd89e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m1,
+  vfloat16mf2_t,
+  vint32m1_t,
+  __riscv_vle16_v_f16mf2,
+  __riscv_vfwcvt_rtz_x_f_v_i32m1,
+  __riscv_vse32_v_i32m1,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v30,v31} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf4.c
new file mode 100644
index 00000000000..135b4e38e5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf4.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m1,
+  vfloat16mf4_t,
+  vint32mf2_t,
+  __riscv_vle16_v_f16mf4,
+  __riscv_vfwcvt_rtz_x_f_v_i32mf2,
+  __riscv_vse32_v_i32mf2,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v30,v31} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m1.c
new file mode 100644
index 00000000000..2a2086938db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e32m1,
+  vfloat32m1_t,
+  vint64m2_t,
+  __riscv_vle32_v_f32m1,
+  __riscv_vfwcvt_rtz_x_f_v_i64m2,
+  __riscv_vse64_v_i64m2,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v0,v1([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v2,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m2.c
new file mode 100644
index 00000000000..43d2bec6ece
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e32m2,
+  vfloat32m2_t,
+  vint64m4_t,
+  __riscv_vle32_v_f32m2,
+  __riscv_vfwcvt_rtz_x_f_v_i64m4,
+  __riscv_vse64_v_i64m4,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v0,v2([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v4,v6} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m4.c
new file mode 100644
index 00000000000..a8519e7fc08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e32m4,
+  vfloat32m4_t,
+  vint64m8_t,
+  __riscv_vle32_v_f32m4,
+  __riscv_vfwcvt_rtz_x_f_v_i64m8,
+  __riscv_vse64_v_i64m8,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.x\.f\.v\s+v8,v12} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-mf2.c
new file mode 100644
index 00000000000..8d0e009a94c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e32m1,
+  vfloat32mf2_t,
+  vint64m1_t,
+  __riscv_vle32_v_f32mf2,
+  __riscv_vfwcvt_rtz_x_f_v_i64m1,
+  __riscv_vse64_v_i64m1,
+  vfwcvt_rtz_x,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.rtz\.x\.f\.v\s+v30,v31} } } */