From: Marc Zyngier Date: Sat, 23 May 2026 14:02:29 +0000 (+0100) Subject: dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6951e870868d0b4bc385cbc851b871effa595330;p=thirdparty%2Flinux.git dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description The arm,arch_timer DT binding is extremely imprecise in describing the requirements for interrupts. Follow the architecture by making it explicit that: - the EL1 secure timer irq is required if EL3 is implemented - the EL1 physical timer irq is always required - the EL1 virtual timer irq is always required - the EL2 physical timer irq is required if EL2 is implemented - the EL2 virtual timer irq is required if FEAT_VHE is implemented The consequence of the above is that the minimum number of interrupts to be described is 2, and not 1. Finally, clean up the description which made the assumption that the timers are plugged into a GIC (unfortunately, that's not always true), drop the MMIO nonsense that has long be moved to a separate binding, and use the architectural terminology to describe the various interrupts. Signed-off-by: Marc Zyngier Signed-off-by: Daniel Lezcano Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260523140242.586031-5-maz@kernel.org --- diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index c5fc3b6c8bd0b..c65e48a155ab6 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -10,13 +10,8 @@ maintainers: - Marc Zyngier - Mark Rutland description: |+ - ARM cores may have a per-core architected timer, which provides per-cpu timers, - or a memory mapped architected timer, which provides up to 8 frames with a - physical and optional virtual timer per frame. - - The per-core architected timer is attached to a GIC to deliver its - per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC - to deliver its interrupts via SPIs. + The per-core architected timer is expected to deliver per-CPU interrupts + (commonly to a GIC to deliver its per-processor interrupts as PPIs). properties: compatible: @@ -33,13 +28,13 @@ properties: - const: arm,armv7-timer interrupts: - minItems: 1 + minItems: 2 items: - - description: secure timer irq - - description: non-secure timer irq - - description: virtual timer irq - - description: hypervisor timer irq - - description: hypervisor virtual timer irq + - description: EL1 secure physical timer irq, if EL3 is implemented + - description: EL1 non-secure physical timer irq + - description: EL1 virtual timer irq + - description: EL2 physical timer irq, if EL2 is implemented + - description: EL2 virtual timer irq, if FEAT_VHE is implemented interrupt-names: oneOf: