From: Ville Syrjälä Date: Mon, 10 Nov 2025 17:27:49 +0000 (+0200) Subject: drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6be05d5b286a4dc8710148cd4152e5e04cafddb2;p=thirdparty%2Fkernel%2Flinux.git drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() Use intel_de_wait_for_{set,clear}_ms() instead of intel_de_wait_ms() where appropriate. Done with cocci (with manual formatting fixes): @@ identifier func !~ "intel_de_wait_for"; expression display, reg, mask, timeout_ms; @@ func(...) { <... ( - intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL) + intel_de_wait_for_set_ms(display, reg, mask, timeout_ms) | - intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL) + intel_de_wait_for_clear_ms(display, reg, mask, timeout_ms) ) ...> } Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20251110172756.2132-11-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal Acked-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 68e9009d25565..d98b4cf6b60e0 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2826,9 +2826,9 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, intel_cx0_get_powerdown_update(lane_mask)); /* Update Timeout Value */ - if (intel_de_wait_ms(display, buf_ctl2_reg, - intel_cx0_get_powerdown_update(lane_mask), 0, - XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL)) + if (intel_de_wait_for_clear_ms(display, buf_ctl2_reg, + intel_cx0_get_powerdown_update(lane_mask), + XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS)) drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n", phy_name(phy)); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index ac6ff183bc979..bebd7488aab9c 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1201,9 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, XELPDP_LANE_PCLK_PLL_REQUEST(0), XELPDP_LANE_PCLK_PLL_REQUEST(0)); - if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port), - XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0), - XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL)) + if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port), + XELPDP_LANE_PCLK_PLL_ACK(0), + XE3PLPD_MACCLK_TURNON_LATENCY_MS)) drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n", phy_name(phy)); @@ -1214,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset | lane_phy_pulse_status, 0); - if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port), - lane_phy_current_status, 0, - XE3PLPD_RESET_END_LATENCY_MS, NULL)) + if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port), + lane_phy_current_status, + XE3PLPD_RESET_END_LATENCY_MS)) drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n", phy_name(phy)); - if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port), - lane_phy_pulse_status, lane_phy_pulse_status, - XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL)) + if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port), + lane_phy_pulse_status, + XE3PLPD_RATE_CALIB_DONE_LATENCY_MS)) drm_warn(display->drm, "PHY %c PLL rate not changed\n", phy_name(phy)); @@ -2001,9 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, XELPDP_LANE_PCLK_PLL_REQUEST(0)); /* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */ - if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port), - XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0), - XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL)) + if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port), + XELPDP_LANE_PCLK_PLL_ACK(0), + XE3PLPD_MACCLK_TURNON_LATENCY_MS)) drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n", phy_name(phy)); @@ -2029,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, rate_update, MB_WRITE_COMMITTED); /* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */ - if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port), - lane_phy_pulse_status, lane_phy_pulse_status, - XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL)) + if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port), + lane_phy_pulse_status, + XE3PLPD_RATE_CALIB_DONE_LATENCY_MS)) drm_warn(display->drm, "PHY %c PLL rate not changed\n", phy_name(phy));