From: Rajkumar Manoharan Date: Thu, 25 Oct 2012 11:41:31 +0000 (+0530) Subject: ath9k_hw: Enable hw PLL power save for AR9462 X-Git-Tag: v3.4.87~90 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6c2e0026cb5ab9d87c6b8a57fcf3d15ada8ed043;p=thirdparty%2Fkernel%2Fstable.git ath9k_hw: Enable hw PLL power save for AR9462 commit 1680260226a8fd2aab590319da83ad8e610da9bd upstream. This reduced the power consumption to half in full and network sleep. Cc: Paul Stewart Signed-off-by: Rajkumar Manoharan Signed-off-by: John W. Linville [bwh: Backported to 3.2: - INIT_INI_ARRAY macro requires an explicit size argument - Remove the now-redundant macro PCIE_PLL_ON_CREQ_DIS_L1_2P0] Signed-off-by: Ben Hutchings Cc: Jianguo Wu Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 0b2f48e4ab41e..42ad784b26884 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -33,9 +33,6 @@ */ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) { -#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \ - ar9462_pciephy_pll_on_clkreq_disable_L1_2p0 - #define AR9462_BB_CTX_COEFJ(x) \ ar9462_##x##_baseband_core_txfir_coeff_japan_2484 @@ -312,13 +309,13 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) /* Awake -> Sleep Setting */ INIT_INI_ARRAY(&ah->iniPcieSerdes, - PCIE_PLL_ON_CREQ_DIS_L1_2P0, - ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), + ar9462_pciephy_clkreq_disable_L1_2p0, + ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0), 2); /* Sleep -> Awake Setting */ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, - PCIE_PLL_ON_CREQ_DIS_L1_2P0, - ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), + ar9462_pciephy_clkreq_disable_L1_2p0, + ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0), 2); /* Fast clock modal settings */