From: Cerion Armour-Brown <cerion@valgrind.org>
Date: Mon, 2 Jan 2006 15:15:45 +0000 (+0000)
Subject: ppc64 altivec:
X-Git-Tag: svn/VALGRIND_3_2_3^2~131
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6d634f7e59336fac578b4a6ed4fee0cb2963e35a;p=thirdparty%2Fvalgrind.git

ppc64 altivec:
 - frontend: fix stvehx, stvewx
 - backend:  fix Iop_32HLto64 (mask off hi32 bits of src regs)



git-svn-id: svn://svn.valgrind.org/vex/trunk@1528
---

diff --git a/VEX/priv/guest-ppc/toIR.c b/VEX/priv/guest-ppc/toIR.c
index 97ca61f389..5850888a86 100644
--- a/VEX/priv/guest-ppc/toIR.c
+++ b/VEX/priv/guest-ppc/toIR.c
@@ -6475,7 +6475,7 @@ static Bool dis_av_store ( UInt theInstr )
 
    IRType ty           = mode64 ? Ity_I64 : Ity_I32;
    IRTemp EA           = newTemp(ty);
-   IRTemp addr_aligned = newTemp(Ity_I32);
+   IRTemp addr_aligned = newTemp(ty);
    IRTemp vS           = newTemp(Ity_V128);
    IRTemp eb           = newTemp(Ity_I8);
    IRTemp idx          = newTemp(Ity_I8);
@@ -6504,10 +6504,9 @@ static Bool dis_av_store ( UInt theInstr )
    }
    case 0x0A7: { // stvehx (Store Vector Half Word Indexed, AV p132)
       DIP("stvehx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
-      assign( addr_aligned,
-              mkSzNarrow32(ty, addr_align(mkexpr(EA), 2)) );
+      assign( addr_aligned, addr_align(mkexpr(EA), 2) );
       assign( eb, binop(Iop_And8, mkU8(0xF),
-                        unop(Iop_32to8, mkexpr(addr_aligned) )) );
+                        mkSzNarrow8(ty, mkexpr(addr_aligned) )) );
       assign( idx, binop(Iop_Shl8,
                          binop(Iop_Sub8, mkU8(14), mkexpr(eb)),
                          mkU8(3)) );
@@ -6518,10 +6517,9 @@ static Bool dis_av_store ( UInt theInstr )
    }
    case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133)
       DIP("stvewx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
-      assign( addr_aligned,
-              mkSzNarrow32(ty, addr_align(mkexpr(EA), 4)) );
+      assign( addr_aligned, addr_align(mkexpr(EA), 4) );
       assign( eb, binop(Iop_And8, mkU8(0xF),
-                        unop(Iop_32to8, mkexpr(addr_aligned) )) );
+                        mkSzNarrow8(ty, mkexpr(addr_aligned) )) );
       assign( idx, binop(Iop_Shl8,
                          binop(Iop_Sub8, mkU8(12), mkexpr(eb)),
                          mkU8(3)) );
diff --git a/VEX/priv/host-ppc/isel.c b/VEX/priv/host-ppc/isel.c
index 7772dac5c1..6862f1df44 100644
--- a/VEX/priv/host-ppc/isel.c
+++ b/VEX/priv/host-ppc/isel.c
@@ -1252,13 +1252,17 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
 //zz       }
 
       if (e->Iex.Binop.op == Iop_32HLto64) {
-         HReg   r_dst = newVRegI(env);
          HReg   r_Hi  = iselIntExpr_R(env, e->Iex.Binop.arg1);
          HReg   r_Lo  = iselIntExpr_R(env, e->Iex.Binop.arg2);
+         HReg   r_dst = newVRegI(env);
+         HReg   msk   = newVRegI(env);
          vassert(mode64);
          /* r_dst = OR( r_Hi<<32, r_Lo ) */
          addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
                                      r_dst, r_Hi, PPCRH_Imm(False,32)));
+         addInstr(env, PPCInstr_LI(msk, 0xFFFFFFFF, mode64));
+         addInstr(env, PPCInstr_Alu( Palu_AND, r_Lo, r_Lo,
+                                     PPCRH_Reg(msk) ));
          addInstr(env, PPCInstr_Alu( Palu_OR, r_dst, r_dst,
                                      PPCRH_Reg(r_Lo) ));
          return r_dst;