From: Georg-Johann Lay Date: Fri, 16 Sep 2011 18:28:32 +0000 (+0000) Subject: avr.md: (umulqihi3, mulqihi3): Write as one pattern. X-Git-Tag: releases/gcc-4.7.0~3736 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6deb519753e07d167eda75bced5a7987a57f0a03;p=thirdparty%2Fgcc.git avr.md: (umulqihi3, mulqihi3): Write as one pattern. * config/avr/avr.md: (umulqihi3, mulqihi3): Write as one pattern. (umulqi3_highpart, smulqi3_highpart): Ditto. (*maddqihi4.const, *umaddqihi4.uconst): Ditto. (*msubqihi4.const, *umsubqihi4.uconst): Ditto. (*muluqihi3.uconst, *mulsqihi3.sconst): Ditto. From-SVN: r178913 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 25cd75374495..ce61c21aa682 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2011-09-16 Georg-Johann Lay + + * config/avr/avr.md: (umulqihi3, mulqihi3): Write as one pattern. + (umulqi3_highpart, smulqi3_highpart): Ditto. + (*maddqihi4.const, *umaddqihi4.uconst): Ditto. + (*msubqihi4.const, *umsubqihi4.uconst): Ditto. + (*muluqihi3.uconst, *mulsqihi3.sconst): Ditto. + 2011-09-16 Georg-Johann Lay PR target/50358 diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index c16150497eb3..80bb8f5300d2 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -1027,31 +1027,21 @@ [(set_attr "type" "xcall") (set_attr "cc" "clobber")]) -(define_insn "smulqi3_highpart" - [(set (match_operand:QI 0 "register_operand" "=r") - (truncate:QI - (lshiftrt:HI (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d")) - (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))) +;; "umulqi3_highpart" +;; "smulqi3_highpart" +(define_insn "mulqi3_highpart" + [(set (match_operand:QI 0 "register_operand" "=r") + (truncate:QI + (lshiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "")) + (any_extend:HI (match_operand:QI 2 "register_operand" ""))) (const_int 8))))] "AVR_HAVE_MUL" - "muls %1,%2 + "mul %1,%2 mov %0,r1 clr __zero_reg__" [(set_attr "length" "3") (set_attr "cc" "clobber")]) -(define_insn "umulqi3_highpart" - [(set (match_operand:QI 0 "register_operand" "=r") - (truncate:QI - (lshiftrt:HI (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) - (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))) - (const_int 8))))] - "AVR_HAVE_MUL" - "mul %1,%2 - mov %0,r1 - clr __zero_reg__" - [(set_attr "length" "3") - (set_attr "cc" "clobber")]) ;; Used when expanding div or mod inline for some special values (define_insn "*subqi3.ashiftrt7" @@ -1064,25 +1054,16 @@ [(set_attr "length" "2") (set_attr "cc" "clobber")]) -(define_insn "mulqihi3" - [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d")) - (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))] - "AVR_HAVE_MUL" - "muls %1,%2 - movw %0,r0 - clr r1" - [(set_attr "length" "3") - (set_attr "cc" "clobber")]) - -(define_insn "umulqihi3" - [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) - (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))] +;; "umulqihi3" +;; "mulqihi3" +(define_insn "mulqihi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "")) + (any_extend:HI (match_operand:QI 2 "register_operand" ""))))] "AVR_HAVE_MUL" - "mul %1,%2 + "mul %1,%2 movw %0,r0 - clr r1" + clr __zero_reg__" [(set_attr "length" "3") (set_attr "cc" "clobber")]) @@ -1293,42 +1274,46 @@ ;; Handle small constants -(define_insn_and_split "*umaddqihi4.uconst" - [(set (match_operand:HI 0 "register_operand" "=r") - (plus:HI (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) - (match_operand:HI 2 "u8_operand" "M")) - (match_operand:HI 3 "register_operand" "0"))) +;; "umaddqihi4.uconst" +;; "maddqihi4.sconst" +(define_insn_and_split "*maddqihi4.const" + [(set (match_operand:HI 0 "register_operand" "=r") + (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "")) + (match_operand:HI 2 "8_operand" "n")) + (match_operand:HI 3 "register_operand" "0"))) (clobber (match_scratch:QI 4 "=&d"))] "AVR_HAVE_MUL" "#" "&& reload_completed" [(set (match_dup 4) (match_dup 2)) - ; *umaddqihi4 + ; *umaddqihi4 resp. *maddqihi4 (set (match_dup 0) - (plus:HI (mult:HI (zero_extend:HI (match_dup 1)) - (zero_extend:HI (match_dup 4))) + (plus:HI (mult:HI (any_extend:HI (match_dup 1)) + (any_extend:HI (match_dup 4))) (match_dup 3)))] { operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) -(define_insn_and_split "*umsubqihi4.uconst" - [(set (match_operand:HI 0 "register_operand" "=r") - (minus:HI (match_operand:HI 3 "register_operand" "0") - (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) - (match_operand:HI 2 "u8_operand" "M")))) +;; "*umsubqihi4.uconst" +;; "*msubqihi4.sconst" +(define_insn_and_split "*msubqihi4.const" + [(set (match_operand:HI 0 "register_operand" "=r") + (minus:HI (match_operand:HI 3 "register_operand" "0") + (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "")) + (match_operand:HI 2 "8_operand" "n")))) (clobber (match_scratch:QI 4 "=&d"))] "AVR_HAVE_MUL" "#" "&& reload_completed" [(set (match_dup 4) (match_dup 2)) - ; *umsubqihi4 + ; *umsubqihi4 resp. *msubqihi4 (set (match_dup 0) (minus:HI (match_dup 3) - (mult:HI (zero_extend:HI (match_dup 1)) - (zero_extend:HI (match_dup 4)))))] + (mult:HI (any_extend:HI (match_dup 1)) + (any_extend:HI (match_dup 4)))))] { operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) @@ -1356,46 +1341,6 @@ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), QImode); }) -(define_insn_and_split "*maddqihi4.sconst" - [(set (match_operand:HI 0 "register_operand" "=r") - (plus:HI (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d")) - (match_operand:HI 2 "s8_operand" "n")) - (match_operand:HI 3 "register_operand" "0"))) - (clobber (match_scratch:QI 4 "=&d"))] - "AVR_HAVE_MUL" - "#" - "&& reload_completed" - [(set (match_dup 4) - (match_dup 2)) - ; *maddqihi4 - (set (match_dup 0) - (plus:HI (mult:HI (sign_extend:HI (match_dup 1)) - (sign_extend:HI (match_dup 4))) - (match_dup 3)))] - { - operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); - }) - -(define_insn_and_split "*msubqihi4.sconst" - [(set (match_operand:HI 0 "register_operand" "=r") - (minus:HI (match_operand:HI 3 "register_operand" "0") - (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d")) - (match_operand:HI 2 "s8_operand" "M")))) - (clobber (match_scratch:QI 4 "=&d"))] - "AVR_HAVE_MUL" - "#" - "&& reload_completed" - [(set (match_dup 4) - (match_dup 2)) - ; *smsubqihi4 - (set (match_dup 0) - (minus:HI (match_dup 3) - (mult:HI (sign_extend:HI (match_dup 1)) - (sign_extend:HI (match_dup 4)))))] - { - operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); - }) - ;; Same as the insn above, but combiner tries versions canonicalized to ASHIFT ;; for MULT with power of 2 and skips trying MULT insn above. We omit 128 ;; because this would require an extra pattern for just one value. @@ -1469,20 +1414,22 @@ ; mul HI: $1 = sign/zero-extend, $2 = small constant ;****************************************************************************** -(define_insn_and_split "*muluqihi3.uconst" +;; "*muluqihi3.uconst" +;; "*mulsqihi3.sconst" +(define_insn_and_split "*mulqihi3.const" [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) - (match_operand:HI 2 "u8_operand" "M"))) + (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "")) + (match_operand:HI 2 "8_operand" "n"))) (clobber (match_scratch:QI 3 "=&d"))] "AVR_HAVE_MUL" "#" "&& reload_completed" [(set (match_dup 3) (match_dup 2)) - ; umulqihi3 + ; umulqihi3 resp. mulqihi3 (set (match_dup 0) - (mult:HI (zero_extend:HI (match_dup 1)) - (zero_extend:HI (match_dup 3))))] + (mult:HI (any_extend:HI (match_dup 1)) + (any_extend:HI (match_dup 3))))] { operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) @@ -1505,24 +1452,6 @@ operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) -(define_insn_and_split "*mulsqihi3.sconst" - [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d")) - (match_operand:HI 2 "s8_operand" "n"))) - (clobber (match_scratch:QI 3 "=&d"))] - "AVR_HAVE_MUL" - "#" - "&& reload_completed" - [(set (match_dup 3) - (match_dup 2)) - ; mulqihi3 - (set (match_dup 0) - (mult:HI (sign_extend:HI (match_dup 1)) - (sign_extend:HI (match_dup 3))))] - { - operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); - }) - (define_insn_and_split "*mulsqihi3.uconst" [(set (match_operand:HI 0 "register_operand" "=r") (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))