From: Greg Kroah-Hartman Date: Mon, 14 Mar 2022 09:50:51 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v4.9.307~9 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6e24f25bdb76549ea36f6e0fb5a2bf8d9595bef8;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: ext4-add-check-to-prevent-attempting-to-resize-an-fs-with-sparse_super2.patch kvm-svm-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domains.patch x86-cpu-add-hardware-enforced-cache-coherency-as-a-cpuid-feature.patch x86-cpufeatures-mark-two-free-bits-in-word-3.patch x86-mm-pat-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domnains.patch --- diff --git a/queue-5.4/ext4-add-check-to-prevent-attempting-to-resize-an-fs-with-sparse_super2.patch b/queue-5.4/ext4-add-check-to-prevent-attempting-to-resize-an-fs-with-sparse_super2.patch new file mode 100644 index 00000000000..ffb4952b1c9 --- /dev/null +++ b/queue-5.4/ext4-add-check-to-prevent-attempting-to-resize-an-fs-with-sparse_super2.patch @@ -0,0 +1,55 @@ +From b1489186cc8391e0c1e342f9fbc3eedf6b944c61 Mon Sep 17 00:00:00 2001 +From: Josh Triplett +Date: Mon, 7 Jun 2021 12:15:24 -0700 +Subject: ext4: add check to prevent attempting to resize an fs with sparse_super2 + +From: Josh Triplett + +commit b1489186cc8391e0c1e342f9fbc3eedf6b944c61 upstream. + +The in-kernel ext4 resize code doesn't support filesystem with the +sparse_super2 feature. It fails with errors like this and doesn't finish +the resize: +EXT4-fs (loop0): resizing filesystem from 16640 to 7864320 blocks +EXT4-fs warning (device loop0): verify_reserved_gdb:760: reserved GDT 2 missing grp 1 (32770) +EXT4-fs warning (device loop0): ext4_resize_fs:2111: error (-22) occurred during file system resize +EXT4-fs (loop0): resized filesystem to 2097152 + +To reproduce: +mkfs.ext4 -b 4096 -I 256 -J size=32 -E resize=$((256*1024*1024)) -O sparse_super2 ext4.img 65M +truncate -s 30G ext4.img +mount ext4.img /mnt +python3 -c 'import fcntl, os, struct ; fd = os.open("/mnt", os.O_RDONLY | os.O_DIRECTORY) ; fcntl.ioctl(fd, 0x40086610, struct.pack("Q", 30 * 1024 * 1024 * 1024 // 4096), False) ; os.close(fd)' +dmesg | tail +e2fsck ext4.img + +The userspace resize2fs tool has a check for this case: it checks if the +filesystem has sparse_super2 set and if the kernel provides +/sys/fs/ext4/features/sparse_super2. However, the former check requires +manually reading and parsing the filesystem superblock. + +Detect this case in ext4_resize_begin and error out early with a clear +error message. + +Signed-off-by: Josh Triplett +Link: https://lore.kernel.org/r/74b8ae78405270211943cd7393e65586c5faeed1.1623093259.git.josh@joshtriplett.org +Signed-off-by: Theodore Ts'o +Signed-off-by: Greg Kroah-Hartman +--- + fs/ext4/resize.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/fs/ext4/resize.c ++++ b/fs/ext4/resize.c +@@ -74,6 +74,11 @@ int ext4_resize_begin(struct super_block + return -EPERM; + } + ++ if (ext4_has_feature_sparse_super2(sb)) { ++ ext4_msg(sb, KERN_ERR, "Online resizing not supported with sparse_super2"); ++ return -EOPNOTSUPP; ++ } ++ + if (test_and_set_bit_lock(EXT4_FLAGS_RESIZING, + &EXT4_SB(sb)->s_ext4_flags)) + ret = -EBUSY; diff --git a/queue-5.4/kvm-svm-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domains.patch b/queue-5.4/kvm-svm-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domains.patch new file mode 100644 index 00000000000..35fb6bf68fb --- /dev/null +++ b/queue-5.4/kvm-svm-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domains.patch @@ -0,0 +1,42 @@ +From e1ebb2b49048c4767cfa0d8466f9c701e549fa5e Mon Sep 17 00:00:00 2001 +From: Krish Sadhukhan +Date: Thu, 17 Sep 2020 21:20:38 +0000 +Subject: KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains + +From: Krish Sadhukhan + +commit e1ebb2b49048c4767cfa0d8466f9c701e549fa5e upstream. + +In some hardware implementations, coherency between the encrypted and +unencrypted mappings of the same physical page in a VM is enforced. In +such a system, it is not required for software to flush the VM's page +from all CPU caches in the system prior to changing the value of the +C-bit for the page. + +So check that bit before flushing the cache. + +Signed-off-by: Krish Sadhukhan +Signed-off-by: Borislav Petkov +Acked-by: Paolo Bonzini +Link: https://lkml.kernel.org/r/20200917212038.5090-4-krish.sadhukhan@oracle.com +[ The linux-5.4.y stable branch does not have the Linux 5.7 refactoring commit + eaf78265a4ab ("KVM: SVM: Move SEV code to separate file") so the + change was manually applied to sev_clflush_pages() in arch/x86/kvm/svm.c. ] +Signed-off-by: Liam Merwick +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kvm/svm.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/x86/kvm/svm.c ++++ b/arch/x86/kvm/svm.c +@@ -1904,7 +1904,8 @@ static void sev_clflush_pages(struct pag + uint8_t *page_virtual; + unsigned long i; + +- if (npages == 0 || pages == NULL) ++ if (this_cpu_has(X86_FEATURE_SME_COHERENT) || npages == 0 || ++ pages == NULL) + return; + + for (i = 0; i < npages; i++) { diff --git a/queue-5.4/series b/queue-5.4/series index 2f65db35f75..379d2af5e48 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -36,3 +36,8 @@ arm64-dts-marvell-armada-37xx-remap-io-space-to-bus-address-0x0.patch virtio-unexport-virtio_finalize_features.patch virtio-acknowledge-all-features-before-access.patch arm-fix-thumb2-regression-with-spectre-bhb.patch +ext4-add-check-to-prevent-attempting-to-resize-an-fs-with-sparse_super2.patch +x86-cpufeatures-mark-two-free-bits-in-word-3.patch +x86-cpu-add-hardware-enforced-cache-coherency-as-a-cpuid-feature.patch +x86-mm-pat-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domnains.patch +kvm-svm-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domains.patch diff --git a/queue-5.4/x86-cpu-add-hardware-enforced-cache-coherency-as-a-cpuid-feature.patch b/queue-5.4/x86-cpu-add-hardware-enforced-cache-coherency-as-a-cpuid-feature.patch new file mode 100644 index 00000000000..ee435d1486b --- /dev/null +++ b/queue-5.4/x86-cpu-add-hardware-enforced-cache-coherency-as-a-cpuid-feature.patch @@ -0,0 +1,49 @@ +From 5866e9205b47a983a77ebc8654949f696342f2ab Mon Sep 17 00:00:00 2001 +From: Krish Sadhukhan +Date: Thu, 17 Sep 2020 21:20:36 +0000 +Subject: x86/cpu: Add hardware-enforced cache coherency as a CPUID feature + +From: Krish Sadhukhan + +commit 5866e9205b47a983a77ebc8654949f696342f2ab upstream. + +In some hardware implementations, coherency between the encrypted and +unencrypted mappings of the same physical page is enforced. In such a system, +it is not required for software to flush the page from all CPU caches in the +system prior to changing the value of the C-bit for a page. This hardware- +enforced cache coherency is indicated by EAX[10] in CPUID leaf 0x8000001f. + + [ bp: Use one of the free slots in word 3. ] + +Suggested-by: Tom Lendacky +Signed-off-by: Krish Sadhukhan +Signed-off-by: Borislav Petkov +Link: https://lkml.kernel.org/r/20200917212038.5090-2-krish.sadhukhan@oracle.com +Signed-off-by: Liam Merwick +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/include/asm/cpufeatures.h | 2 +- + arch/x86/kernel/cpu/scattered.c | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -96,7 +96,7 @@ + #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ + #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ + #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ +-/* free ( 3*32+17) */ ++#define X86_FEATURE_SME_COHERENT ( 3*32+17) /* "" AMD hardware-enforced cache coherency */ + #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ + #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ + #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ +--- a/arch/x86/kernel/cpu/scattered.c ++++ b/arch/x86/kernel/cpu/scattered.c +@@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits + { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, + { X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 }, ++ { X86_FEATURE_SME_COHERENT, CPUID_EAX, 10, 0x8000001f, 0 }, + { 0, 0, 0, 0, 0 } + }; + diff --git a/queue-5.4/x86-cpufeatures-mark-two-free-bits-in-word-3.patch b/queue-5.4/x86-cpufeatures-mark-two-free-bits-in-word-3.patch new file mode 100644 index 00000000000..68cc2717765 --- /dev/null +++ b/queue-5.4/x86-cpufeatures-mark-two-free-bits-in-word-3.patch @@ -0,0 +1,39 @@ +From fbd5969d1ff2598143d6a6fbc9491a9e40ab9b82 Mon Sep 17 00:00:00 2001 +From: Borislav Petkov +Date: Thu, 4 Jun 2020 12:38:39 +0200 +Subject: x86/cpufeatures: Mark two free bits in word 3 + +From: Borislav Petkov + +commit fbd5969d1ff2598143d6a6fbc9491a9e40ab9b82 upstream. + +... so that they get reused when needed. + +No functional changes. + +Signed-off-by: Borislav Petkov +Link: https://lkml.kernel.org/r/20200604104150.2056-1-bp@alien8.de +Signed-off-by: Liam Merwick +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/include/asm/cpufeatures.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -96,6 +96,7 @@ + #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ + #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ + #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ ++/* free ( 3*32+17) */ + #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ + #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ + #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ +@@ -107,6 +108,7 @@ + #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ + #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ + #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ ++/* free ( 3*32+29) */ + #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ + #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ + diff --git a/queue-5.4/x86-mm-pat-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domnains.patch b/queue-5.4/x86-mm-pat-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domnains.patch new file mode 100644 index 00000000000..d82e2f8f110 --- /dev/null +++ b/queue-5.4/x86-mm-pat-don-t-flush-cache-if-hardware-enforces-cache-coherency-across-encryption-domnains.patch @@ -0,0 +1,38 @@ +From 75d1cc0e05af579301ce4e49cf6399be4b4e6e76 Mon Sep 17 00:00:00 2001 +From: Krish Sadhukhan +Date: Thu, 17 Sep 2020 21:20:37 +0000 +Subject: x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains + +From: Krish Sadhukhan + +commit 75d1cc0e05af579301ce4e49cf6399be4b4e6e76 upstream. + +In some hardware implementations, coherency between the encrypted and +unencrypted mappings of the same physical page is enforced. In such a +system, it is not required for software to flush the page from all CPU +caches in the system prior to changing the value of the C-bit for the +page. So check that bit before flushing the cache. + + [ bp: Massage commit message. ] + +Suggested-by: Tom Lendacky +Signed-off-by: Krish Sadhukhan +Signed-off-by: Borislav Petkov +Link: https://lkml.kernel.org/r/20200917212038.5090-3-krish.sadhukhan@oracle.com +Signed-off-by: Liam Merwick +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/mm/pageattr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/x86/mm/pageattr.c ++++ b/arch/x86/mm/pageattr.c +@@ -1967,7 +1967,7 @@ static int __set_memory_enc_dec(unsigned + /* + * Before changing the encryption attribute, we need to flush caches. + */ +- cpa_flush(&cpa, 1); ++ cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT)); + + ret = __change_page_attr_set_clr(&cpa, 1); +