From: Qiang Yu <qiang.yu@oss.qualcomm.com>
Date: Tue, 22 Jul 2025 09:11:50 +0000 (+0800)
Subject: arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3
X-Git-Tag: v6.18-rc1~147^2~32^2~159
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=6facfaff0fe3b4d5903bed6164eb5e60ee6cdb8f;p=thirdparty%2Fkernel%2Flinux.git

arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3

Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot
voltage rails can be described under this node in the board's dts.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 5e9a8fa3cf964..c9fea040223ba 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3306,6 +3306,17 @@
 					opp-peak-kBps = <15753000 1>;
 				};
 			};
+
+			pcie3_port: pcie@0 {
+				device_type = "pci";
+				compatible = "pciclass,0604";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie3_phy: phy@1be0000 {