From: Michal Simek Date: Tue, 12 Jul 2016 09:57:46 +0000 (+0200) Subject: Merge tag 'v2016.07' into master X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=77ab23952b4f7b0114a42418b44adabe86bef76b;p=thirdparty%2Fu-boot.git Merge tag 'v2016.07' into master Prepare v2016.07 - arm64 Revert "armv8: Enable CPUECTLR.SMPEN for coherency" This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. because it is breaking starting bootflow with ATF - zynq_nand - Fix code based on mainline patches "mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data" (sha1: 17cb4b8f327eb983cef7c510fcf77f1635a00e48) "mtd: nand: Add page argument to write_page() etc." (sha1: 81c772521ff26054a3fe75efa87d8daeae83e9b4) Signed-off-by: Michal Simek --- 77ab23952b4f7b0114a42418b44adabe86bef76b diff --cc Makefile index 954a865381a,88128ec72a2..88128ec72a2 mode 100755,100644..100755 --- a/Makefile +++ b/Makefile diff --cc arch/arm/dts/Makefile index 0fa11c665a6,ef573ec6851..a2622253c3c --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@@ -95,11 -97,19 +104,21 @@@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm018-dc4.dtb \ - zynqmp-zc1751-xm019-dc5.dtb + zynqmp-zc1751-xm019-dc5.dtb \ + zynqmp-mini-qspi.dtb \ + zynqmp-mini-nand.dtb - dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb - dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb + dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ + am335x-draco.dtb \ + am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-bonegreen.dtb \ + am335x-icev2.dtb \ + am335x-pxm50.dtb \ + am335x-rut.dtb + dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ + am43x-epos-evm.dtb \ + am437x-idk-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ diff --cc board/xilinx/zynqmp/zynqmp.c index 157f1a5124f,f15dc5d7152..93230a3dd24 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@@ -15,7 -16,7 +16,8 @@@ #include #include #include +#include + #include DECLARE_GLOBAL_DATA_PTR; @@@ -295,22 -213,16 +313,30 @@@ void scsi_init(void int board_late_init(void) { -- u32 reg = 0; ++ u32 ver, reg = 0; u8 bootmode; - u32 ver = zynqmp_get_silicon_version(); + const char *mode; + char *new_targets; + + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } + ++ ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + setenv("setup", "setenv baudrate 4800 && setenv bootcmd run veloce"); + case ZYNQMP_CSU_VERSION_EP108: + case ZYNQMP_CSU_VERSION_SILICON: + setenv("setup", "setenv partid auto"); + break; + case ZYNQMP_CSU_VERSION_QEMU: + default: + setenv("setup", "setenv partid 0"); + } + reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; @@@ -318,33 -230,35 +344,42 @@@ switch (bootmode) { case JTAG_MODE: puts("JTAG_MODE\n"); + mode = "pxe dhcp"; + setenv("modeboot", "jtagboot"); break; case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: - setenv("modeboot", "qspiboot"); + mode = "qspi0"; puts("QSPI_MODE\n"); ++ setenv("modeboot", "qspiboot"); break; case EMMC_MODE: puts("EMMC_MODE\n"); + mode = "mmc0"; + setenv("modeboot", "sdboot"); break; case SD_MODE: puts("SD_MODE\n"); + mode = "mmc0"; + setenv("modeboot", "sdboot"); break; case SD_MODE1: puts("SD_MODE1\n"); #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + mode = "mmc1"; + setenv("sdbootdev", "1"); + #else + mode = "mmc0"; #endif + setenv("modeboot", "sdboot"); break; case NAND_MODE: puts("NAND_MODE\n"); + mode = "nand0"; + setenv("modeboot", "nandboot"); break; default: + mode = ""; printf("Invalid Boot Mode:0x%x\n", bootmode); break; } diff --cc cmd/Kconfig index 102e5d3cd2b,d69b817c827..64059fe836b --- a/cmd/Kconfig +++ b/cmd/Kconfig @@@ -593,18 -593,13 +593,25 @@@ config CMD_SOUN sound init - set up sound system sound play - play a sound +config CMD_ZYNQ_AES + bool "Zynq AES" + depends on CMD_ZYNQ_RSA + help + Decrypts the encrypted image present in source address + and places the decrypted image at destination address + +config CMD_ZYNQ_RSA + bool "Zynq RSA" + help + Verifies the authenticated and encrypted zynq images. + + config CMD_QFW + bool "qfw" + select QFW + help + This provides access to the QEMU firmware interface. The main + feature is to allow easy loading of files passed to qemu-system + via -kernel / -initrd endmenu config CMD_BOOTSTAGE diff --cc configs/xilinx_zynqmp_ep_defconfig index 285e30ed46d,7325f190f0b..fb9da5dcb24 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@@ -1,11 -1,9 +1,11 @@@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" CONFIG_ARCH_ZYNQMP=y - CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_SYS_MALLOC_F_LEN=0x8000 ++CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_GPIO=y - CONFIG_DM_SPI_FLASH=y +CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" @@@ -21,6 -21,7 +23,8 @@@ CONFIG_SYS_PROMPT="ZynqMP> # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y + CONFIG_CMD_NAND=y ++CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y @@@ -49,12 -51,16 +54,19 @@@ CONFIG_ZYNQ_SDHCI= CONFIG_NAND_ARASAN=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_ZYNQ=y + CONFIG_DEBUG_UART_BASE=0xff000000 + CONFIG_DEBUG_UART_CLOCK=25000000 + CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_GADGET=y diff --cc configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 14534bee939,91af8ce3267..d3d36cf3392 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@@ -1,10 -1,9 +1,11 @@@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1" CONFIG_ARCH_ZYNQMP=y + CONFIG_SYS_MALLOC_F_LEN=0x8000 ++CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_GPIO=y - CONFIG_DM_SPI_FLASH=y +CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" @@@ -15,6 -17,6 +19,7 @@@ CONFIG_SYS_PROMPT="ZynqMP> CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y ++CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y diff --cc configs/xilinx_zynqmp_zcu102_defconfig index c5cb276c7b2,d7eb8c27304..c22a520bef2 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@@ -1,9 -1,8 +1,10 @@@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" CONFIG_ARCH_ZYNQMP=y - CONFIG_DM_GPIO=y + CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_DM_SPI_FLASH=y + CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" @@@ -14,6 -16,6 +18,7 @@@ CONFIG_SYS_PROMPT="ZynqMP> CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y ++CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y diff --cc configs/xilinx_zynqmp_zcu102_revB_defconfig index 1e679343c2a,80a59ef07dd..38dd95c4e88 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@@ -1,9 -1,8 +1,10 @@@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" CONFIG_ARCH_ZYNQMP=y - CONFIG_DM_GPIO=y + CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_DM_SPI_FLASH=y + CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" @@@ -14,6 -16,6 +18,7 @@@ CONFIG_SYS_PROMPT="ZynqMP> CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y ++CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y diff --cc configs/zynq_afx_nand_RSA_defconfig index 9478b9730ba,00000000000..240778f698d mode 100644,000000..100644 --- a/configs/zynq_afx_nand_RSA_defconfig +++ b/configs/zynq_afx_nand_RSA_defconfig @@@ -1,13 -1,0 +1,12 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_AFX=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nand" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="AFX_NAND" +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_nand_defconfig index 878a6a78b9d,00000000000..adb2ae8cf74 mode 100644,000000..100644 --- a/configs/zynq_afx_nand_defconfig +++ b/configs/zynq_afx_nand_defconfig @@@ -1,8 -1,0 +1,7 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_AFX=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nand" +CONFIG_SYS_EXTRA_OPTIONS="AFX_NAND" +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_nor_RSA_defconfig index e5825efeec4,00000000000..1600f494f0a mode 100644,000000..100644 --- a/configs/zynq_afx_nor_RSA_defconfig +++ b/configs/zynq_afx_nor_RSA_defconfig @@@ -1,12 -1,0 +1,11 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_AFX=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nor" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="AFX_NOR" +CONFIG_SYS_PROMPT="Zynq> " +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_nor_defconfig index 2069f16b66c,00000000000..ca27758d212 mode 100644,000000..100644 --- a/configs/zynq_afx_nor_defconfig +++ b/configs/zynq_afx_nor_defconfig @@@ -1,7 -1,0 +1,6 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_AFX=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nor" +CONFIG_SYS_EXTRA_OPTIONS="AFX_NOR" +CONFIG_SYS_PROMPT="Zynq> " +CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_qspi_RSA_defconfig index bb5a515d6d8,00000000000..c916e85662e mode 100644,000000..100644 --- a/configs/zynq_afx_qspi_RSA_defconfig +++ b/configs/zynq_afx_qspi_RSA_defconfig @@@ -1,20 -1,0 +1,19 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_AFX=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-qspi" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_OF_EMBED=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_QSPI=y diff --cc configs/zynq_afx_qspi_defconfig index fcdece95495,00000000000..1f60c684c2a mode 100644,000000..100644 --- a/configs/zynq_afx_qspi_defconfig +++ b/configs/zynq_afx_qspi_defconfig @@@ -1,15 -1,0 +1,14 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_AFX=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-qspi" +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +CONFIG_OF_EMBED=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_QSPI=y diff --cc configs/zynq_cc108_defconfig index 2b1a763c7a8,00000000000..ebb5506caeb mode 100644,000000..100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@@ -1,26 -1,0 +1,25 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_CC108=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +CONFIG_OF_EMBED=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_QSPI=y diff --cc configs/zynq_cse_nand_defconfig index b36240f4a59,00000000000..d25cea4be71 mode 100644,000000..100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@@ -1,11 -1,0 +1,11 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_CSE=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" +CONFIG_SYS_EXTRA_OPTIONS="CSE_NAND" +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_GO is not set +CONFIG_OF_EMBED=y +# CONFIG_EFI_LOADER is not set diff --cc configs/zynq_cse_nor_defconfig index 657890ebdc3,00000000000..7cfff64ccae mode 100644,000000..100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@@ -1,11 -1,0 +1,11 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_CSE=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" +CONFIG_SYS_EXTRA_OPTIONS="CSE_NOR" +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_GO is not set +CONFIG_OF_EMBED=y +# CONFIG_EFI_LOADER is not set diff --cc configs/zynq_cse_qspi_defconfig index 3e3aeebd3cf,00000000000..30aeac5b0c0 mode 100644,000000..100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@@ -1,43 -1,0 +1,43 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_CSE=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi" +CONFIG_SYS_EXTRA_OPTIONS="CSE_QSPI" +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_DM is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_QSPI=y +# CONFIG_EFI_LOADER is not set diff --cc configs/zynq_picozed_defconfig index 537294e7447,aeb127020fd..eeb0fab94d3 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@@ -1,8 -1,9 +1,8 @@@ CONFIG_ARM=y + CONFIG_SYS_CONFIG_NAME="zynq_picozed" CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_PICOZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_SPL=y -CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --cc configs/zynq_zc702_RSA_defconfig index aff10de2654,00000000000..90dbe0c49ff mode 100644,000000..100644 --- a/configs/zynq_zc702_RSA_defconfig +++ b/configs/zynq_zc702_RSA_defconfig @@@ -1,56 -1,0 +1,57 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_zc70x" +CONFIG_ARCH_ZYNQ=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300 diff --cc configs/zynq_zc706_RSA_defconfig index 042821c22a1,00000000000..dfc21fea5d5 mode 100644,000000..100644 --- a/configs/zynq_zc706_RSA_defconfig +++ b/configs/zynq_zc706_RSA_defconfig @@@ -1,53 -1,0 +1,53 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_zc70x" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_ZC706=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300 diff --cc configs/zynq_zc770_xm010_RSA_defconfig index ac75f318169,00000000000..9e814a3974b mode 100644,000000..100644 --- a/configs/zynq_zc770_xm010_RSA_defconfig +++ b/configs/zynq_zc770_xm010_RSA_defconfig @@@ -1,26 -1,0 +1,44 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_zc770" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TFTPPUT=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_CMD_EXT2=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_EXT4_WRITE=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SPI=y +CONFIG_ZYNQ_QSPI=y diff --cc configs/zynq_zc770_xm011_RSA_defconfig index e1222fcad18,00000000000..4e2a8c7ec63 mode 100644,000000..100644 --- a/configs/zynq_zc770_xm011_RSA_defconfig +++ b/configs/zynq_zc770_xm011_RSA_defconfig @@@ -1,13 -1,0 +1,26 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_zc770" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" ++CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TFTPPUT=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_OF_EMBED=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_ZYNQ_GEM=y diff --cc configs/zynq_zc770_xm012_RSA_defconfig index 8d620d71a3e,00000000000..0c9db7b56c4 mode 100644,000000..100644 --- a/configs/zynq_zc770_xm012_RSA_defconfig +++ b/configs/zynq_zc770_xm012_RSA_defconfig @@@ -1,15 -1,0 +1,25 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_zc770" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set ++CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TFTPPUT=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_OF_EMBED=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_ZYNQ_GEM=y diff --cc configs/zynq_zc770_xm013_RSA_defconfig index 81e313e7157,00000000000..0bbcab05433 mode 100644,000000..100644 --- a/configs/zynq_zc770_xm013_RSA_defconfig +++ b/configs/zynq_zc770_xm013_RSA_defconfig @@@ -1,18 -1,0 +1,34 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_zc770" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y ++CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TFTPPUT=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_OF_EMBED=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_ISSI=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_QSPI=y diff --cc configs/zynq_zed_RSA_defconfig index e22fecedffb,00000000000..9e056d7d57b mode 100644,000000..100644 --- a/configs/zynq_zed_RSA_defconfig +++ b/configs/zynq_zed_RSA_defconfig @@@ -1,50 -1,0 +1,50 @@@ +CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="zynq_zed" +CONFIG_ARCH_ZYNQ=y - CONFIG_TARGET_ZYNQ_ZED=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_ZYNQ_AES=y +CONFIG_CMD_ZYNQ_RSA=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300 diff --cc drivers/mtd/nand/Makefile index 4d83d9654ad,837d397bdaf..ebf19b41843 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@@ -68,8 -66,6 +66,7 @@@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand. obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o - obj-$(CONFIG_NAND_DOCG4) += docg4.o +obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o else # minimal SPL drivers diff --cc drivers/mtd/nand/zynq_nand.c index e7eb076054f,00000000000..f1b15d2b8b3 mode 100644,000000..100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@@ -1,1266 -1,0 +1,1264 @@@ +/* + * Xilinx Zynq NAND Flash Controller Driver + * This driver is based on plat_nand.c and mxc_nand.c drivers + * + * Copyright (C) 2009 - 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The NAND flash driver defines */ +#define ZYNQ_NAND_CMD_PHASE 1 /* End command valid in command phase */ +#define ZYNQ_NAND_DATA_PHASE 2 /* End command valid in data phase */ +#define ZYNQ_NAND_ECC_SIZE 512 /* Size of data for ECC operation */ + +/* Flash memory controller operating parameters */ +#define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \ + (0x1 << 4) | /* Clear interrupt */ \ + (0x1 << 6)) /* Disable ECC interrupt */ + +/* Assuming 50MHz clock (20ns cycle time) and 3V operation */ +#define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \ + (0x2 << 17) | /* t_ar from nand_cycles */ \ + (0x1 << 14) | /* t_clr from nand_cycles */ \ + (0x3 << 11) | /* t_wp from nand_cycles */ \ + (0x2 << 8) | /* t_rea from nand_cycles */ \ + (0x5 << 4) | /* t_wc from nand_cycles */ \ + (0x5 << 0)) /* t_rc from nand_cycles */ + +#define ZYNQ_NAND_SET_OPMODE 0x0 + +#define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \ + (0x2 << 21)) /* UpdateRegs operation */ + +#define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \ + (0x1 << 4) | /* ECC read at end of page */ \ + (0x0 << 5)) /* No Jumping */ + +#define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \ + (0x00 << 8) | /* Read command */ \ + (0x30 << 16) | /* Read End command */ \ + (0x1 << 24)) /* Read End command calid */ + +#define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \ + (0x05 << 8) | /* Read col change cmd */ \ + (0xE0 << 16) | /* Read col change end cmd */ \ + (0x1 << 24)) /* Read col change + end cmd valid */ +/* AXI Address definitions */ +#define START_CMD_SHIFT 3 +#define END_CMD_SHIFT 11 +#define END_CMD_VALID_SHIFT 20 +#define ADDR_CYCLES_SHIFT 21 +#define CLEAR_CS_SHIFT 21 +#define ECC_LAST_SHIFT 10 +#define COMMAND_PHASE (0 << 19) +#define DATA_PHASE (1 << 19) + +#define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */ +#define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */ + +/* ECC block registers bit position and bit mask */ +#define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ +#define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ + +#define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F +#define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0 + +/* NAND MIO buswidth count*/ +#define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13 +#define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8 + +/* NAND buswidth */ +enum zynq_nand_bus_width { + NAND_BW_UNKNOWN = -1, + NAND_BW_8BIT, + NAND_BW_16BIT, +}; + +/* SMC register set */ +struct zynq_nand_smc_regs { + u32 csr; /* 0x00 */ + u32 reserved0[2]; + u32 cfr; /* 0x0C */ + u32 dcr; /* 0x10 */ + u32 scr; /* 0x14 */ + u32 sor; /* 0x18 */ + u32 reserved1[249]; + u32 esr; /* 0x400 */ + u32 emcr; /* 0x404 */ + u32 emcmd1r; /* 0x408 */ + u32 emcmd2r; /* 0x40C */ + u32 reserved2[2]; + u32 eval0r; /* 0x418 */ +}; + +#define zynq_nand_smc_base ((struct zynq_nand_smc_regs *)ZYNQ_SMC_BASEADDR) + +/* + * struct zynq_nand_command_format - Defines NAND flash command format + * @start_cmd: First cycle command (Start command) + * @end_cmd: Second cycle command (Last command) + * @addr_cycles: Number of address cycles required to send the address + * @end_cmd_valid: The second cycle command is valid for cmd or data phase + */ +struct zynq_nand_command_format { + int start_cmd; + int end_cmd; + u8 addr_cycles; + u8 end_cmd_valid; +}; + +/* + * struct zynq_nand_info - Defines the NAND flash driver instance + * @parts: Pointer to the mtd_partition structure + * @nand_base: Virtual address of the NAND flash device + * @end_cmd_pending: End command is pending + * @end_cmd: End command + */ +struct zynq_nand_info { +#ifdef CONFIG_MTD_PARTITIONS + struct mtd_partition *parts; +#endif + void __iomem *nand_base; + unsigned long end_cmd_pending; + unsigned long end_cmd; +}; + +#define ONDIE_ECC_FEATURE_ADDR 0x90 + +/* The NAND flash operations command format */ +static const struct zynq_nand_command_format zynq_nand_commands[] = { + {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_READID, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_STATUS, NAND_CMD_NONE, 0, NAND_CMD_NONE}, + {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE}, + {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, NAND_CMD_NONE}, + {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_RESET, NAND_CMD_NONE, 0, NAND_CMD_NONE}, + {NAND_CMD_PARAM, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0}, + /* Add all the flash commands supported by the flash device and Linux + * The cache program command is not supported by driver because driver + * cant differentiate between page program and cached page program from + * start command, these commands can be differentiated through end + * command, which doesn't fit in to the driver design. The cache program + * command is not supported by NAND subsystem also, look at 1612 line + * number (in nand_write_page function) of nand_base.c file. + * {NAND_CMD_SEQIN, NAND_CMD_CACHEDPROG, 5, ZYNQ_NAND_YES} + */ +}; + +/* Define default oob placement schemes for large and small page devices */ +static struct nand_ecclayout nand_oob_16 = { + .eccbytes = 3, + .eccpos = {13, 14, 15}, + .oobfree = { + { .offset = 0, .length = 12 } + } +}; + +static struct nand_ecclayout nand_oob_64 = { + .eccbytes = 12, + .eccpos = { + 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63}, + .oobfree = { + { .offset = 2, .length = 50 } + } +}; + +static struct nand_ecclayout ondie_nand_oob_64 = { + .eccbytes = 32, + + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 24, 25, 26, 27, 28, 29, 30, 31, + 40, 41, 42, 43, 44, 45, 46, 47, + 56, 57, 58, 59, 60, 61, 62, 63 + }, + + .oobfree = { + { .offset = 4, .length = 4 }, + { .offset = 20, .length = 4 }, + { .offset = 36, .length = 4 }, + { .offset = 52, .length = 4 } + } +}; + +/* Generic flash bbt decriptors */ +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 4, + .len = 4, + .veroffs = 20, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 4, + .len = 4, + .veroffs = 20, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/* + * zynq_nand_waitfor_ecc_completion - Wait for ECC completion + * + * returns: status for command completion, -1 for Timeout + */ +static int zynq_nand_waitfor_ecc_completion(void) +{ + unsigned long timeout; + u32 status; + + /* Wait max 10ms */ + timeout = 10; + status = readl(&zynq_nand_smc_base->esr); + while (status & ZYNQ_NAND_ECC_BUSY) { + status = readl(&zynq_nand_smc_base->esr); + if (timeout == 0) + return -1; + timeout--; + udelay(1); + } + + return status; +} + +/* + * zynq_nand_init_nand_flash - Initialize NAND controller + * @option: Device property flags + * + * This function initializes the NAND flash interface on the NAND controller. + * + * returns: 0 on success or error value on failure + */ +static int zynq_nand_init_nand_flash(int option) +{ + u32 status; + + /* disable interrupts */ + writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr); + /* Initialize the NAND interface by setting cycles and operation mode */ + writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr); + if (option & NAND_BUSWIDTH_16) + writel((ZYNQ_NAND_SET_OPMODE | 0x1), &zynq_nand_smc_base->sor); + else + writel(ZYNQ_NAND_SET_OPMODE, &zynq_nand_smc_base->sor); + + writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr); + + /* Wait till the ECC operation is complete */ + status = zynq_nand_waitfor_ecc_completion(); + if (status < 0) { + printf("%s: Timeout\n", __func__); + return status; + } + + /* Set the command1 and command2 register */ + writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r); + writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r); + + return 0; +} + +/* + * zynq_nand_calculate_hwecc - Calculate Hardware ECC + * @mtd: Pointer to the mtd_info structure + * @data: Pointer to the page data + * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored + * + * This function retrieves the Hardware ECC data from the controller and returns + * ECC data back to the MTD subsystem. + * + * returns: 0 on success or error value on failure + */ +static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, + u8 *ecc_code) +{ + u32 ecc_value = 0; + u8 ecc_reg, ecc_byte; + u32 ecc_status; + + /* Wait till the ECC operation is complete */ + ecc_status = zynq_nand_waitfor_ecc_completion(); + if (ecc_status < 0) { + printf("%s: Timeout\n", __func__); + return ecc_status; + } + + for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) { + /* Read ECC value for each block */ + ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg); + ecc_status = (ecc_value >> 24) & 0xFF; + /* ECC value valid */ + if (ecc_status & 0x40) { + for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) { + /* Copy ECC bytes to MTD buffer */ + *ecc_code = ecc_value & 0xFF; + ecc_value = ecc_value >> 8; + ecc_code++; + } + } else { + debug("%s: ecc status failed\n", __func__); + } + } + return 0; +} + +/* + * onehot - onehot function + * @value: value to check for onehot + * + * This function checks whether a value is onehot or not. + * onehot is if and only if onebit is set. + * + */ +static int onehot(unsigned short value) +{ + return ((value & (value-1)) == 0); +} + +/* + * zynq_nand_correct_data - ECC correction function + * @mtd: Pointer to the mtd_info structure + * @buf: Pointer to the page data + * @read_ecc: Pointer to the ECC value read from spare data area + * @calc_ecc: Pointer to the calculated ECC value + * + * This function corrects the ECC single bit errors & detects 2-bit errors. + * + * returns: 0 if no ECC errors found + * 1 if single bit error found and corrected. + * -1 if multiple ECC errors found. + */ +static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf, + unsigned char *read_ecc, unsigned char *calc_ecc) +{ + unsigned char bit_addr; + unsigned int byte_addr; + unsigned short ecc_odd, ecc_even; + unsigned short read_ecc_lower, read_ecc_upper; + unsigned short calc_ecc_lower, calc_ecc_upper; + + read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff; + read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff; + + calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff; + calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff; + + ecc_odd = read_ecc_lower ^ calc_ecc_lower; + ecc_even = read_ecc_upper ^ calc_ecc_upper; + + if ((ecc_odd == 0) && (ecc_even == 0)) + return 0; /* no error */ + else if (ecc_odd == (~ecc_even & 0xfff)) { + /* bits [11:3] of error code is byte offset */ + byte_addr = (ecc_odd >> 3) & 0x1ff; + /* bits [2:0] of error code is bit offset */ + bit_addr = ecc_odd & 0x7; + /* Toggling error bit */ + buf[byte_addr] ^= (1 << bit_addr); + return 1; + } else if (onehot(ecc_odd | ecc_even) == 1) { + return 1; /* one error in parity */ + } else { + return -1; /* Uncorrectable error */ + } +} + +/* + * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to read + * @sndcmd: flag whether to issue read command or not + */ +static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + + p = chip->oob_poi; + chip->read_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->read_buf(mtd, p, data_width); + + return 0; +} + +/* + * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to write + */ +static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + const u8 *buf = chip->oob_poi; + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + + chip->write_buf(mtd, buf, (mtd->oobsize - data_width)); + buf += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + chip->write_buf(mtd, buf, data_width); + + /* Send command to program the OOB data */ + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + return status & NAND_STATUS_FAIL ? -EIO : 0; +} + +/* + * zynq_nand_read_page_raw - [Intern] read raw page data without ecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to read + */ +static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->read_buf(mtd, buf, mtd->writesize); + + p = chip->oob_poi; + chip->read_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + chip->read_buf(mtd, p, data_width); + return 0; +} + +static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + chip->read_buf(mtd, buf, mtd->writesize); + return 0; +} + +static int zynq_nand_read_subpage_raw(struct mtd_info *mtd, + struct nand_chip *chip, uint32_t offs, + uint32_t len, uint8_t *buf, int page) +{ + if (offs != 0) { + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offs, -1); + buf += offs; + } + + chip->read_buf(mtd, buf, len); + return 0; +} + +/* + * zynq_nand_write_page_raw - [Intern] raw page write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + */ +static int zynq_nand_write_page_raw(struct mtd_info *mtd, - struct nand_chip *chip, const u8 *buf, int oob_required) ++ struct nand_chip *chip, const u8 *buf, int oob_required, int page) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->write_buf(mtd, buf, mtd->writesize); + + p = chip->oob_poi; + chip->write_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + + chip->write_buf(mtd, p, data_width); + + return 0; +} + +/* + * nand_write_page_hwecc - Hardware ECC based page write function + * @mtd: Pointer to the mtd info structure + * @chip: Pointer to the NAND chip info structure + * @buf: Pointer to the data buffer + * @oob_required: must write chip->oob_poi to OOB + * + * This functions writes data and hardware generated ECC values in to the page. + */ +static int zynq_nand_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, const u8 *buf, int oob_required) ++ struct nand_chip *chip, const u8 *buf, int oob_required, int page) +{ + int i, eccsize = chip->ecc.size; + int eccsteps = chip->ecc.steps; + u8 *ecc_calc = chip->buffers->ecccalc; + const u8 *p = buf; + u32 *eccpos = chip->ecc.layout->eccpos; + unsigned long data_phase_addr = 0; + unsigned long data_width = 4; + u8 *oob_ptr; + + for (; (eccsteps - 1); eccsteps--) { + chip->write_buf(mtd, p, eccsize); + p += eccsize; + } + chip->write_buf(mtd, p, (eccsize - data_width)); + p += (eccsize - data_width); + + /* Set ECC Last bit to 1 */ + data_phase_addr = (unsigned long) chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + chip->write_buf(mtd, p, data_width); + + /* Wait for ECC to be calculated and read the error values */ + p = buf; + chip->ecc.calculate(mtd, p, &ecc_calc[0]); + + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]); + + /* Clear ECC last bit */ + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + + /* Write the spare area with ECC bytes */ + oob_ptr = chip->oob_poi; + chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + oob_ptr += (mtd->oobsize - data_width); + chip->write_buf(mtd, oob_ptr, data_width); + + return 0; +} + +/* + * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page + * write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + */ +static int zynq_nand_write_page_swecc(struct mtd_info *mtd, - struct nand_chip *chip, const u8 *buf, int oob_required) ++ struct nand_chip *chip, const u8 *buf, int oob_required, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *ecc_calc = chip->buffers->ecccalc; + const u8 *p = buf; + u32 *eccpos = chip->ecc.layout->eccpos; + + /* Software ecc calculation */ + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ecc_calc[i]; + - return chip->ecc.write_page_raw(mtd, chip, buf, 1); ++ return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); +} + +/* + * nand_read_page_hwecc - Hardware ECC based page read function + * @mtd: Pointer to the mtd info structure + * @chip: Pointer to the NAND chip info structure + * @buf: Pointer to the buffer to store read data + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to read + * + * This functions reads data and checks the data integrity by comparing hardware + * generated ECC values and read ECC values from spare area. + * + * returns: 0 always and updates ECC operation status in to MTD structure + */ +static int zynq_nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int i, stat, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *p = buf; + u8 *ecc_calc = chip->buffers->ecccalc; + u8 *ecc_code = chip->buffers->ecccode; + u32 *eccpos = chip->ecc.layout->eccpos; + unsigned long data_phase_addr = 0; + unsigned long data_width = 4; + u8 *oob_ptr; + + for (; (eccsteps - 1); eccsteps--) { + chip->read_buf(mtd, p, eccsize); + p += eccsize; + } + chip->read_buf(mtd, p, (eccsize - data_width)); + p += (eccsize - data_width); + + /* Set ECC Last bit to 1 */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->read_buf(mtd, p, data_width); + + /* Read the calculated ECC value */ + p = buf; + chip->ecc.calculate(mtd, p, &ecc_calc[0]); + + /* Clear ECC last bit */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + /* Read the stored ECC value */ + oob_ptr = chip->oob_poi; + chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); + + /* de-assert chip select */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + oob_ptr += (mtd->oobsize - data_width); + chip->read_buf(mtd, oob_ptr, data_width); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = ~(chip->oob_poi[eccpos[i]]); + + eccsteps = chip->ecc.steps; + p = buf; + + /* Check ECC error for all blocks and correct if it is correctable */ + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/* + * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page + * read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + */ +static int zynq_nand_read_page_swecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *p = buf; + u8 *ecc_calc = chip->buffers->ecccalc; + u8 *ecc_code = chip->buffers->ecccode; + u32 *eccpos = chip->ecc.layout->eccpos; + + chip->ecc.read_page_raw(mtd, chip, buf, 1, page); + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + eccsteps = chip->ecc.steps; + p = buf; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/* + * zynq_nand_select_chip - Select the flash device + * @mtd: Pointer to the mtd_info structure + * @chip: Chip number to be selected + * + * This function is empty as the NAND controller handles chip select line + * internally based on the chip address passed in command and data phase. + */ +static void zynq_nand_select_chip(struct mtd_info *mtd, int chip) +{ + return; +} + +/* + * zynq_nand_cmd_function - Send command to NAND device + * @mtd: Pointer to the mtd_info structure + * @command: The command to be sent to the flash device + * @column: The column address for this command, -1 if none + * @page_addr: The page address for this command, -1 if none + */ +static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ - struct nand_chip *chip = mtd->priv; ++ struct nand_chip *chip = mtd_to_nand(mtd); + const struct zynq_nand_command_format *curr_cmd = NULL; + u8 addr_cycles = 0; + struct zynq_nand_info *xnand; + void *cmd_addr; + unsigned long cmd_data = 0; + unsigned long cmd_phase_addr = 0; + unsigned long data_phase_addr = 0; + unsigned long end_cmd = 0; + unsigned long end_cmd_valid = 0; + unsigned long i; + - xnand = (struct zynq_nand_info *)chip->priv; ++ xnand = nand_get_controller_data(chip); + if (xnand->end_cmd_pending) { + /* Check for end command if this command request is same as the + * pending command then return + */ + if (xnand->end_cmd == command) { + xnand->end_cmd = 0; + xnand->end_cmd_pending = 0; + return; + } + } + + /* Emulate NAND_CMD_READOOB for large page device */ + if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) && + (command == NAND_CMD_READOOB)) { + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Get the command format */ + for (i = 0; (zynq_nand_commands[i].start_cmd != NAND_CMD_NONE || + zynq_nand_commands[i].end_cmd != NAND_CMD_NONE); i++) { + if (command == zynq_nand_commands[i].start_cmd) + curr_cmd = &zynq_nand_commands[i]; + } + if (curr_cmd == NULL) + return; + + /* Clear interrupt */ + writel((1 << 4), &zynq_nand_smc_base->cfr); + + /* Get the command phase address */ + if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) + end_cmd_valid = 1; + + if (curr_cmd->end_cmd == NAND_CMD_NONE) + end_cmd = 0x0; + else + end_cmd = curr_cmd->end_cmd; + + if ((command == NAND_CMD_READ0) || + (command == NAND_CMD_SEQIN)) { + addr_cycles = chip->onfi_params.addr_cycles & + ZYNQ_NAND_ROW_ADDR_CYCL_MASK; + addr_cycles += ((chip->onfi_params.addr_cycles & + ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4); + } else { + addr_cycles = curr_cmd->addr_cycles; + } + + cmd_phase_addr = (unsigned long)xnand->nand_base | + (addr_cycles << ADDR_CYCLES_SHIFT) | + (end_cmd_valid << END_CMD_VALID_SHIFT) | + (COMMAND_PHASE) | + (end_cmd << END_CMD_SHIFT) | + (curr_cmd->start_cmd << START_CMD_SHIFT); + + cmd_addr = (void __iomem *)cmd_phase_addr; + + /* Get the data phase address */ + end_cmd_valid = 0; + + data_phase_addr = (unsigned long)xnand->nand_base | + (0x0 << CLEAR_CS_SHIFT) | + (end_cmd_valid << END_CMD_VALID_SHIFT) | + (DATA_PHASE) | + (end_cmd << END_CMD_SHIFT) | + (0x0 << ECC_LAST_SHIFT); + + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->IO_ADDR_W = chip->IO_ADDR_R; + + /* Command phase AXI Read & Write */ + if (column != -1 && page_addr != -1) { + /* Adjust columns for 16 bit bus width */ + if (chip->options & NAND_BUSWIDTH_16) + column >>= 1; + cmd_data = column; + if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) { + cmd_data |= page_addr << 16; + /* Another address cycle for devices > 128MiB */ + if (chip->chipsize > (128 << 20)) { + writel(cmd_data, cmd_addr); + cmd_data = (page_addr >> 16); + } + } else { + cmd_data |= page_addr << 8; + } + } + /* Erase */ + else if (page_addr != -1) + cmd_data = page_addr; + /* Change read/write column, read id etc */ + else if (column != -1) { + /* Adjust columns for 16 bit bus width */ + if ((chip->options & NAND_BUSWIDTH_16) && + ((command == NAND_CMD_READ0) || + (command == NAND_CMD_SEQIN) || + (command == NAND_CMD_RNDOUT) || + (command == NAND_CMD_RNDIN))) + column >>= 1; + cmd_data = column; + } else + ; + + writel(cmd_data, cmd_addr); + + if (curr_cmd->end_cmd_valid) { + xnand->end_cmd = curr_cmd->end_cmd; + xnand->end_cmd_pending = 1; + } + + ndelay(100); + + if ((command == NAND_CMD_READ0) || + (command == NAND_CMD_RESET) || + (command == NAND_CMD_PARAM) || + (command == NAND_CMD_GET_FEATURES)) { + while (!chip->dev_ready(mtd)) + ; + return; + } +} + +/* + * zynq_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ - struct nand_chip *chip = mtd->priv; ++ struct nand_chip *chip = mtd_to_nand(mtd); + const u32 *nand = chip->IO_ADDR_R; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + *buf = readb(nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + *(u32 *)buf = readl(nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + + if (len) + *buf = readb(nand); + } +} + +/* + * zynq_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ - struct nand_chip *chip = mtd->priv; ++ struct nand_chip *chip = mtd_to_nand(mtd); + const u32 *nand = chip->IO_ADDR_W; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + writeb(*buf, nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + writel(*(u32 *)buf, nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + + if (len) + writeb(*buf, nand); + } +} + +/* + * zynq_nand_device_ready - Check device ready/busy line + * @mtd: Pointer to the mtd_info structure + * + * returns: 0 on busy or 1 on ready state + */ +static int zynq_nand_device_ready(struct mtd_info *mtd) +{ + /* Check the raw_int_status1 bit */ + if ((readl(&zynq_nand_smc_base->csr)) & 0x40) { + /* Clear the interrupt condition */ + writel((1 << 4), &zynq_nand_smc_base->cfr); + return 1; + } + return 0; +} + +/* + * zynq_nand_check_is_16bit_bw_flash - checking for 16 or 8 bit buswidth nand + * + * This function will check nand buswidth whether it supports 16 or 8 bit + * based on the MIO configuration done by FSBL. + * + * User needs to correctly configure the MIO's based on the + * buswidth supported by the nand flash which is present on the board. + * + * function will return -1, if there is no MIO configuration for + * nand flash. + */ +static int zynq_nand_check_is_16bit_bw_flash(void) +{ + int is_16bit_bw = NAND_BW_UNKNOWN; + int mio_num_8bit = 0, mio_num_16bit = 0; + + mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8"); + if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) + is_16bit_bw = NAND_BW_8BIT; + + mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16"); + if ((mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) && + (mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)) + is_16bit_bw = NAND_BW_16BIT; + + return is_16bit_bw; +} + +static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +{ + struct zynq_nand_info *xnand; + struct mtd_info *mtd; + unsigned long ecc_page_size; + int err = -1; + u8 maf_id, dev_id, i; + u8 get_feature[4]; + u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00}; + unsigned long ecc_cfg; + int ondie_ecc_enabled = 0; + int is_16bit_bw; + + xnand = calloc(1, sizeof(struct zynq_nand_info)); + if (!xnand) { + printf("%s: failed to allocate\n", __func__); + goto free; + } + + xnand->nand_base = (void *)ZYNQ_NAND_BASEADDR; - mtd = &nand_info[0]; - - nand_chip->priv = xnand; - mtd->priv = nand_chip; ++ mtd = nand_to_mtd(nand_chip); ++ nand_set_controller_data(nand_chip, xnand); + + /* Set address of NAND IO lines */ + nand_chip->IO_ADDR_R = xnand->nand_base; + nand_chip->IO_ADDR_W = xnand->nand_base; + + /* Set the driver entry points for MTD */ + nand_chip->cmdfunc = zynq_nand_cmd_function; + nand_chip->dev_ready = zynq_nand_device_ready; + nand_chip->select_chip = zynq_nand_select_chip; + + /* If we don't set this delay driver sets 20us by default */ + nand_chip->chip_delay = 30; + + /* Buffer read/write routines */ + nand_chip->read_buf = zynq_nand_read_buf; + nand_chip->write_buf = zynq_nand_write_buf; + + /* Check the NAND buswidth */ + /* FIXME this will be changed by using NAND_BUSWIDTH_AUTO */ + is_16bit_bw = zynq_nand_check_is_16bit_bw_flash(); + if (is_16bit_bw == NAND_BW_UNKNOWN) { + printf("%s: Unable detect NAND based on MIO settings\n", + __func__); + goto free; + } else if (is_16bit_bw == NAND_BW_16BIT) { + nand_chip->options = NAND_BUSWIDTH_16; + } + nand_chip->bbt_options = NAND_BBT_USE_FLASH; + + /* Initialize the NAND flash interface on NAND controller */ + if (zynq_nand_init_nand_flash(nand_chip->options) < 0) { + printf("%s: nand flash init failed\n", __func__); + goto free; + } + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, 1, NULL)) { + printf("%s: nand_scan_ident failed\n", __func__); + goto fail; + } + + /* Send the command for reading device ID */ + nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + maf_id = nand_chip->read_byte(mtd); + dev_id = nand_chip->read_byte(mtd); + + if ((maf_id == 0x2c) && ((dev_id == 0xf1) || + (dev_id == 0xa1) || (dev_id == 0xb1) || + (dev_id == 0xaa) || (dev_id == 0xba) || + (dev_id == 0xda) || (dev_id == 0xca) || + (dev_id == 0xac) || (dev_id == 0xbc) || + (dev_id == 0xdc) || (dev_id == 0xcc) || + (dev_id == 0xa3) || (dev_id == 0xb3) || + (dev_id == 0xd3) || (dev_id == 0xc3))) { + nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + + for (i = 0; i < 4; i++) + writeb(set_feature[i], nand_chip->IO_ADDR_W); + + /* wait for 1us after writing data with SET_FEATURES command */ + ndelay(1000); + + nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + nand_chip->read_buf(mtd, get_feature, 4); + + if (get_feature[0] & 0x08) { + debug("%s: OnDie ECC flash\n", __func__); + ondie_ecc_enabled = 1; + } else { + printf("%s: Unable to detect OnDie ECC\n", __func__); + } + } + + if (ondie_ecc_enabled) { + /* bypass the controller ECC block */ + ecc_cfg = readl(&zynq_nand_smc_base->emcr); + ecc_cfg &= ~0xc; + writel(ecc_cfg, &zynq_nand_smc_base->emcr); + + /* The software ECC routines won't work + * with the SMC controller + */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.strength = 1; + nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob; + nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw; + nand_chip->ecc.write_page = zynq_nand_write_page_raw; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + nand_chip->ecc.size = mtd->writesize; + nand_chip->ecc.bytes = 0; + + /* NAND with on-die ECC supports subpage reads */ + nand_chip->options |= NAND_SUBPAGE_READ; + + /* On-Die ECC spare bytes offset 8 is used for ECC codes */ + if (ondie_ecc_enabled) { + nand_chip->ecc.layout = &ondie_nand_oob_64; + /* Use the BBT pattern descriptors */ + nand_chip->bbt_td = &bbt_main_descr; + nand_chip->bbt_md = &bbt_mirror_descr; + } + } else { + /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.strength = 1; + nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE; + nand_chip->ecc.bytes = 3; + nand_chip->ecc.calculate = zynq_nand_calculate_hwecc; + nand_chip->ecc.correct = zynq_nand_correct_data; + nand_chip->ecc.hwctl = NULL; + nand_chip->ecc.read_page = zynq_nand_read_page_hwecc; + nand_chip->ecc.write_page = zynq_nand_write_page_hwecc; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + + switch (mtd->writesize) { + case 512: + ecc_page_size = 0x1; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + case 1024: + ecc_page_size = 0x2; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + case 2048: + ecc_page_size = 0x3; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + default: + /* The software ECC routines won't work with + * the SMC controller + */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.calculate = nand_calculate_ecc; + nand_chip->ecc.correct = nand_correct_data; + nand_chip->ecc.read_page = zynq_nand_read_page_swecc; + /* nand_chip->ecc.read_subpage = nand_read_subpage; */ + nand_chip->ecc.write_page = zynq_nand_write_page_swecc; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = + zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + nand_chip->ecc.size = 256; + nand_chip->ecc.bytes = 3; + break; + } + + if (mtd->oobsize == 16) + nand_chip->ecc.layout = &nand_oob_16; + else if (mtd->oobsize == 64) + nand_chip->ecc.layout = &nand_oob_64; + else + ; + } + + /* second phase scan */ + if (nand_scan_tail(mtd)) { + printf("%s: nand_scan_tailfailed\n", __func__); + goto fail; + } + - if (nand_register(devnum)) ++ if (nand_register(devnum, mtd)) + goto fail; + + return 0; +fail: +free: + kfree(xnand); + return err; +} + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +void board_nand_init(void) +{ + struct nand_chip *nand = &nand_chip[0]; + + if (zynq_nand_init(nand, 0)) + puts("ZYNQ NAND init failed\n"); +} diff --cc include/configs/xilinx_zynqmp.h index 7b9f1e61a0a,e776e324120..7d8140514f3 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@@ -75,25 -76,19 +76,26 @@@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL - #define CONFIG_BOOTP_SERVERIP + #define CONFIG_BOOTP_DNS + #define CONFIG_BOOTP_PXE + #define CONFIG_BOOTP_SUBNETMASK + + /* Diff from config_distro_defaults.h */ + #define CONFIG_SUPPORT_RAW_INITRD + #define CONFIG_ENV_VARS_UBOOT_CONFIG + #define CONFIG_AUTO_COMPLETE + + /* PXE */ + #define CONFIG_CMD_PXE + #define CONFIG_MENU +#ifdef CONFIG_ZYNQMP_QSPI +# define CONFIG_SPI_GENERIC +# define CONFIG_SF_DEFAULT_SPEED 30000000 +# define CONFIG_SF_DUAL_FLASH +# define CONFIG_CMD_SF_TEST +#endif + - /* NAND */ - #ifdef CONFIG_NAND_ARASAN - # define CONFIG_CMD_NAND - # define CONFIG_CMD_NAND_LOCK_UNLOCK - # define CONFIG_SYS_MAX_NAND_DEVICE 1 - # define CONFIG_SYS_NAND_SELF_INIT - # define CONFIG_SYS_NAND_ONFI_DETECTION - # define CONFIG_MTD_DEVICE - #endif - #if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC # define CONFIG_GENERIC_MMC @@@ -152,67 -144,6 +151,68 @@@ # define DFU_ALT_INFO #endif +/* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x200000\0" \ + "initrd_addr=0xa00000\0" \ + "initrd_size=0x2000000\0" \ + "fdt_addr=4000000\0" \ + "fdt_high=0x10000000\0" \ - CONFIG_KERNEL_FDT_OFST_SIZE \ + "sdbootdev=0\0"\ - CONFIG_KERNEL_FDT_OFST_SIZE \ ++ "kernel_offset=0x180000\0" \ ++ "fdt_offset=0x100000\0" \ ++ "kernel_size=0x1e00000\0" \ ++ "fdt_size=0x80000\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from SD ...; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \ + "sata_root=if test $scsidevs -gt 0; then setenv bootargs $bootargs root=/dev/sda rw rootfstype=ext4; fi\0" \ + "sataboot=load scsi 0 80000 boot/Image && load scsi 0 $fdt_addr boot/system.dtb && booti 80000 - $fdt_addr\0" \ + "veloce=fdt addr f000000 && fdt resize" \ + "fdt set /amba/misc_clk clock-frequency <48000> && "\ + "fdt set /timer clock-frequency <240000> && " \ + "fdt set /amba/i2c_clk clock-frequency <240000> && " \ + "booti 80000 - f000000\0" \ + "netboot=tftpboot 10000000 image.ub && bootm\0" \ + "qspiboot=sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && " \ + "sf read $kernel_addr $kernel_offset $kernel_size && " \ + "booti $kernel_addr - $fdt_addr\0" \ + "uenvboot=" \ + "if run sd_uEnvtxt_existence_test; then " \ + "run loadbootenv; " \ + "echo Loaded environment from ${bootenv}; " \ + "run importbootenv; " \ + "fi\0" \ + "sdboot=mmc dev $sdbootdev && mmcinfo && run uenvboot; " \ + "load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ + "load mmc $sdbootdev:$partid $kernel_addr Image && " \ + "booti $kernel_addr - $fdt_addr\0" \ + "nandboot=nand info && nand read $fdt_addr $fdt_offset $fdt_size && " \ + "nand read $kernel_addr $kernel_offset $kernel_size && " \ + "booti $kernel_addr - $fdt_addr\0" \ + "xen=tftpb $fdt_addr system.dtb && fdt addr $fdt_addr && fdt resize && " \ + "tftpb 0x80000 Image && " \ + "fdt set /chosen/dom0 reg <0x80000 0x$filesize> && "\ + "tftpb 6000000 xen.ub && bootm 6000000 - $fdt_addr\0" \ + "jtagboot=tftpboot 80000 Image && tftpboot $fdt_addr system.dtb && " \ + "tftpboot 6000000 rootfs.cpio.ub && booti 80000 6000000 $fdt_addr\0" \ + "nosmp=setenv bootargs $bootargs maxcpus=1\0" \ + "nfsroot=setenv bootargs $bootargs root=/dev/nfs nfsroot=$serverip:/mnt/sata,tcp ip=$ipaddr:$serverip:$serverip:255.255.255.0:zynqmp:eth0:off rw\0" \ + "sdroot=setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait\0" \ + "sdroot1=setenv bootargs $bootargs root=/dev/mmcblk1p2 rw rootwait\0" \ + "android=setenv bootargs $bootargs init=/init androidboot.selinux=disabled androidboot.hardware=$board\0" \ + "android_debug=run android && setenv bootargs $bootargs video=DP-1:1024x768@60 drm.debug=0xf\0" \ + "usbhostboot=usb start && load usb 0 $fdt_addr system.dtb && " \ + "load usb 0 $kernel_addr Image && " \ + "booti $kernel_addr - $fdt_addr\0" \ + DFU_ALT_INFO +#endif + +#define CONFIG_PREBOOT "run setup" +#define CONFIG_BOOTCOMMAND "run $modeboot" - #define CONFIG_BOOTDELAY 3 #define CONFIG_BOARD_LATE_INIT @@@ -268,15 -201,9 +270,15 @@@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) - #define CONFIG_CMD_SCSI + #define CONFIG_SCSI #endif +#define CONFIG_ARM_SMC + +#define CONFIG_FPGA_ZYNQMPPL +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA + #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #define CONFIG_CMD_BOOTI diff --cc include/configs/xilinx_zynqmp_mini.h index 702c5926749,00000000000..bc21a15b04b mode 100644,000000..100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@@ -1,98 -1,0 +1,103 @@@ +/* + * Configuration for Xilinx ZynqMP Flash utility + * + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + * Siva Durga Prasad Paladugu + * + * Based on Configuration for Versatile Express + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_MINI_H +#define __CONFIG_ZYNQMP_MINI_H + +#define CONFIG_SYS_NO_FLASH +#define _CONFIG_CMD_DEFAULT_H +/* #define CONFIG_SYS_DCACHE_OFF */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_FIT_DISABLE_SHA256 + +#include + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOARD_LATE_INIT +#undef CONFIG_CMD_BOOTZ +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_SYS_HUSH_PARSER +#undef CONFIG_SYS_PROMPT_HUSH_PS2 +#undef CONFIG_BOOTDELAY +#undef CONFIG_PREBOOT +#undef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_ENV_SIZE +#undef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#undef CONFIG_ZLIB +#undef CONFIG_GZIP +#undef CONFIG_CMD_SPL +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_EXT4 +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_FS_GENERIC +#undef CONFIG_CMD_MEMORY +#undef CONFIG_DOS_PARTITION +#undef CONFIG_CMD_ELF +#undef CONFIG_MP +#undef CONFIG_SYS_MEMTEST_START +#undef CONFIG_SYS_MEMTEST_END +#undef CONFIG_SYS_CACHELINE_SIZE +#undef CONFIG_SYS_INIT_SP_ADDR +#undef CONFIG_SYS_LONGHELP +#undef CONFIG_CMD_CACHE +#undef CONFIG_FPGA_ZYNQMPPL +#undef CONFIG_FPGA_XILINX +#undef CONFIG_FPGA +#undef CONFIG_CMD_SF_TEST +#undef CONFIG_CMD_GPIO +#undef CONFIG_CMD_SPI +#undef CONFIG_FIT_VERBOSE +#undef CONFIG_ZYNQ_SERIAL +#undef CONFIG_CMD_MII + +/* BOOTP options */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME +#undef CONFIG_BOOTP_MAY_FAIL +#undef CONFIG_BOOTP_SERVERIP ++#undef CONFIG_BOOTP_PXE +#undef CONFIG_CMD_BOOTI +#undef CONFIG_CMD_UNZIP + ++/* PXE */ ++#undef CONFIG_CMD_PXE ++#undef CONFIG_MENU ++ +/* Define needed configs */ +#define CONFIG_CMD_MEMORY +#define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */ + +#undef CONFIG_NR_DRAM_BANKS +#define CONFIG_NR_DRAM_BANKS 1 + +#if defined(CONFIG_MINI_QSPI) +# define CONFIG_SYS_SDRAM_SIZE (256 * 1024) +# define CONFIG_SYS_SDRAM_BASE 0xFFFC0000 +# define CONFIG_ENV_SIZE 1400 +# define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x20000) +# define CONFIG_SYS_MALLOC_LEN 0x2000 + +#elif defined(CONFIG_MINI_NAND) +# define CONFIG_SYS_SDRAM_SIZE 0x1000000 +# define CONFIG_SYS_SDRAM_BASE 0 +# define CONFIG_ENV_SIZE 0x10000 +# define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) +# define CONFIG_SYS_MALLOC_LEN 0x800000 + +#endif + +#endif /* __CONFIG_ZYNQMP_MINI_H */ diff --cc include/configs/zynq-common.h index 70418940cb5,8dbac8728f0..3dfdd50db9f --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@@ -311,13 -235,7 +311,12 @@@ DFU_ALT_INFO #endif +/* default boot is according to the bootmode switch settings */ +#if defined(CONFIG_CMD_ZYNQ_RSA) +#define CONFIG_BOOTCOMMAND "run rsa_$modeboot" +#else #define CONFIG_BOOTCOMMAND "run $modeboot" +#endif - #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ /* Miscellaneous configurable options */ diff --cc include/netdev.h index 498eeca8832,7a211bc609d..ade2faba053 --- a/include/netdev.h +++ b/include/netdev.h @@@ -134,65 -134,6 +134,7 @@@ static inline int pci_eth_init(bd_t *bi return num; } - /* - * Boards with mv88e61xx switch can use this by defining - * CONFIG_MV88E61XX_SWITCH in respective board configheader file - * the stuct and enums here are used to specify switch configuration params - */ - #if defined(CONFIG_MV88E61XX_SWITCH) - - /* constants for any 88E61xx switch */ - #define MV88E61XX_MAX_PORTS_NUM 6 - - enum mv88e61xx_cfg_mdip { - MV88E61XX_MDIP_NOCHANGE, - MV88E61XX_MDIP_REVERSE - }; - - enum mv88e61xx_cfg_ledinit { - MV88E61XX_LED_INIT_DIS, - MV88E61XX_LED_INIT_EN - }; - - enum mv88e61xx_cfg_rgmiid { - MV88E61XX_RGMII_DELAY_DIS, - MV88E61XX_RGMII_DELAY_EN - }; - - enum mv88e61xx_cfg_prtstt { - MV88E61XX_PORTSTT_DISABLED, - MV88E61XX_PORTSTT_BLOCKING, - MV88E61XX_PORTSTT_LEARNING, - MV88E61XX_PORTSTT_FORWARDING - }; - - struct mv88e61xx_config { - char *name; - u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; - enum mv88e61xx_cfg_rgmiid rgmii_delay; - enum mv88e61xx_cfg_prtstt portstate; - enum mv88e61xx_cfg_ledinit led_init; - enum mv88e61xx_cfg_mdip mdip; - u32 ports_enabled; - u8 cpuport; - }; - - /* - * Common mappings for Internal VLANs - * These mappings consider that all ports are useable; the driver - * will mask inexistent/unused ports. - */ - - /* Switch mode : routes any port to any port */ - #define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } - - /* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ - #define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } - - int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); - #endif /* CONFIG_MV88E61XX_SWITCH */ - +#ifdef CONFIG_FEC_MXC struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device;