From: Jernej Skrabec Date: Tue, 4 Nov 2025 18:09:36 +0000 (+0100) Subject: drm/sun4i: mixer: Convert heuristics to quirk X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=7907cf11406bd1e1a311765a09634f73454bbe3f;p=thirdparty%2Fkernel%2Flinux.git drm/sun4i: mixer: Convert heuristics to quirk Determination if FCC unit can be used for VI layer alpha depends on number of VI channels. This info won't be available anymore in future to VI layer driver because of DE33 way of allocating planes from same pool to different mixers. While order is slightly changed, it doesn't affect anything due to double buffering of registers. New order keeps related registers together and quirk separate. Reviewed-by: Chen-Yu Tsai Tested-by: Ryan Walklin Signed-off-by: Jernej Skrabec Link: https://patch.msgid.link/20251104180942.61538-25-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai --- diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index ceb9bd9201513..86361564189ce 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -708,6 +708,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { .de_type = SUN8I_MIXER_DE2, .scaler_mask = 0xf, .scanline_yuv = 2048, + .de2_fcc_alpha = 1, .ui_num = 3, .vi_num = 1, }; @@ -717,6 +718,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { .de_type = SUN8I_MIXER_DE2, .scaler_mask = 0x3, .scanline_yuv = 2048, + .de2_fcc_alpha = 1, .ui_num = 1, .vi_num = 1, }; @@ -727,6 +729,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { .mod_rate = 432000000, .scaler_mask = 0xf, .scanline_yuv = 2048, + .de2_fcc_alpha = 1, .ui_num = 3, .vi_num = 1, }; @@ -737,6 +740,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { .mod_rate = 297000000, .scaler_mask = 0xf, .scanline_yuv = 2048, + .de2_fcc_alpha = 1, .ui_num = 3, .vi_num = 1, }; @@ -747,6 +751,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, + .de2_fcc_alpha = 1, .ui_num = 1, .vi_num = 1, }; @@ -767,6 +772,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, + .de2_fcc_alpha = 1, .ui_num = 1, .vi_num = 1, }; @@ -777,6 +783,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { .mod_rate = 297000000, .scaler_mask = 0x1, .scanline_yuv = 1024, + .de2_fcc_alpha = 1, .ui_num = 0, .vi_num = 1, }; @@ -787,6 +794,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { .mod_rate = 297000000, .scaler_mask = 0xf, .scanline_yuv = 4096, + .de2_fcc_alpha = 1, .ui_num = 3, .vi_num = 1, }; @@ -797,6 +805,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, + .de2_fcc_alpha = 1, .ui_num = 1, .vi_num = 1, }; diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index d14188cdfab31..def07afd37e1f 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -176,6 +176,8 @@ enum sun8i_mixer_type { * a functional block. * @de_type: sun8i_mixer_type enum representing the display engine generation. * @scaline_yuv: size of a scanline for VI scaler for YUV formats. + * @de2_fcc_alpha: use FCC for missing DE2 VI alpha capability + * Most DE2 cores has FCC. If number of VI planes is one, enable this. * @map: channel map for DE variants processing YUV separately (DE33) */ struct sun8i_mixer_cfg { @@ -186,6 +188,7 @@ struct sun8i_mixer_cfg { unsigned long mod_rate; unsigned int de_type; unsigned int scanline_yuv; + unsigned int de2_fcc_alpha : 1; unsigned int map[6]; }; diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index ce4b270e503be..8e01174406645 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -49,14 +49,16 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer, val |= (state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL : SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED; - } else if (mixer->cfg->vi_num == 1) { - regmap_write(layer->regs, - SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG, - SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8)); } regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val); + + if (mixer->cfg->de2_fcc_alpha) { + regmap_write(layer->regs, + SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG, + SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8)); + } } static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer, @@ -450,7 +452,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, return ERR_PTR(ret); } - if (mixer->cfg->vi_num == 1 || mixer->cfg->de_type >= SUN8I_MIXER_DE3) { + if (mixer->cfg->de2_fcc_alpha || mixer->cfg->de_type >= SUN8I_MIXER_DE3) { ret = drm_plane_create_alpha_property(&layer->plane); if (ret) { dev_err(drm->dev, "Couldn't add alpha property\n");