From: stove <stove@rivosinc.com>
Date: Wed, 27 Aug 2025 20:36:17 +0000 (-0700)
Subject: target/riscv: use riscv_csrr in riscv_csr_read
X-Git-Tag: v10.0.5~12
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=79509912ddf1e2e637865427eadaeaaf57a1edfa;p=thirdparty%2Fqemu.git

target/riscv: use riscv_csrr in riscv_csr_read

Commit 38c83e8d3a33 ("target/riscv: raise an exception when CSRRS/CSRRC
writes a read-only CSR") changed the behavior of riscv_csrrw, which
would formerly be treated as read-only if the write mask were set to 0.

Fixes an exception being raised when accessing read-only vector CSRs
like vtype.

Fixes: 38c83e8d3a33 ("target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR")

Signed-off-by: stove <stove@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250827203617.79947-1-stove@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit cebaf7434b4af059caca053ee1ec7ed8df91c2a7)
(Mjt: context fix for v10.0.0-1030-gf1304836ea "target/riscv: Pass ra to riscv_csrrw")
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7a56666f9a2..71141f4ea61 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -839,7 +839,7 @@ static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 {
     target_ulong val = 0;
-    riscv_csrrw(env, csrno, &val, 0, 0);
+    riscv_csrr(env, csrno, &val);
     return val;
 }