From: Biju Das Date: Thu, 26 Mar 2026 11:06:35 +0000 (+0000) Subject: clk: renesas: rzg2l: Drop always-false check in rzg3s_cpg_pll_clk_recalc_rate() X-Git-Tag: v7.2-rc1~26^2~2^2~1^2~21 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=79b5d6970b4e5b7b7ee4d7fdb18e950086b72bde;p=thirdparty%2Flinux.git clk: renesas: rzg2l: Drop always-false check in rzg3s_cpg_pll_clk_recalc_rate() Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the function is SoC-specific. Reviewed-by: Claudiu Beznea Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326110648.29389-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index abfd8634d2bef..910c16a369a53 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1107,9 +1107,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, u32 nir, nfr, mr, pr, val, setting; u64 rate; - if (pll_clk->type != CLK_TYPE_G3S_PLL) - return parent_rate; - setting = GET_REG_SAMPLL_SETTING(pll_clk->conf); if (setting) { val = readl(priv->base + setting);