From: Greg Kroah-Hartman Date: Fri, 26 May 2023 18:45:43 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: review~76 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=7bcab33fe4c654a33add6b3791ec42889ffaf78a;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch --- diff --git a/queue-5.4/series b/queue-5.4/series index 6dcd1fe08ec..87085511a7f 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -121,3 +121,5 @@ vc_screen-reload-load-of-struct-vc_data-pointer-in-v.patch s390-qdio-get-rid-of-register-asm.patch s390-qdio-fix-do_sqbs-inline-assembly-constraint.patch watchdog-sp5100_tco-immediately-trigger-upon-starting.patch +spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch +spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch diff --git a/queue-5.4/spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch b/queue-5.4/spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch new file mode 100644 index 00000000000..618ad772a86 --- /dev/null +++ b/queue-5.4/spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch @@ -0,0 +1,97 @@ +From christophe.leroy@csgroup.eu Mon May 15 15:07:59 2023 +From: Christophe Leroy +Date: Mon, 15 May 2023 16:07:17 +0200 +Subject: spi: fsl-cpm: Use 16 bit mode for large transfers with even size +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Mark Brown +Message-ID: <3a1b8774ad7004acb594fbf220f98488dbaa2896.1684156552.git.christophe.leroy@csgroup.eu> + +From: Christophe Leroy + +(cherry picked from upstream fc96ec826bced75cc6b9c07a4ac44bbf651337ab) + +On CPM, the RISC core is a lot more efficiant when doing transfers +in 16-bits chunks than in 8-bits chunks, but unfortunately the +words need to be byte swapped as seen in a previous commit. + +So, for large tranfers with an even size, allocate a temporary tx +buffer and byte-swap data before and after transfer. + +This change allows setting higher speed for transfer. For instance +on an MPC 8xx (CPM1 comms RISC processor), the documentation tells +that transfer in byte mode at 1 kbit/s uses 0.200% of CPM load +at 25 MHz while a word transfer at the same speed uses 0.032% +of CPM load. This means the speed can be 6 times higher in +word mode for the same CPM load. + +For the time being, only do it on CPM1 as there must be a +trade-off between the CPM load reduction and the CPU load required +to byte swap the data. + +Signed-off-by: Christophe Leroy +Link: https://lore.kernel.org/r/f2e981f20f92dd28983c3949702a09248c23845c.1680371809.git.christophe.leroy@csgroup.eu +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + drivers/spi/spi-fsl-cpm.c | 23 +++++++++++++++++++++++ + drivers/spi/spi-fsl-spi.c | 3 +++ + 2 files changed, 26 insertions(+) + +--- a/drivers/spi/spi-fsl-cpm.c ++++ b/drivers/spi/spi-fsl-cpm.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + #include "spi-fsl-cpm.h" + #include "spi-fsl-lib.h" +@@ -120,6 +121,21 @@ int fsl_spi_cpm_bufs(struct mpc8xxx_spi + mspi->rx_dma = mspi->dma_dummy_rx; + mspi->map_rx_dma = 0; + } ++ if (t->bits_per_word == 16 && t->tx_buf) { ++ const u16 *src = t->tx_buf; ++ u16 *dst; ++ int i; ++ ++ dst = kmalloc(t->len, GFP_KERNEL); ++ if (!dst) ++ return -ENOMEM; ++ ++ for (i = 0; i < t->len >> 1; i++) ++ dst[i] = cpu_to_le16p(src + i); ++ ++ mspi->tx = dst; ++ mspi->map_tx_dma = 1; ++ } + + if (mspi->map_tx_dma) { + void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */ +@@ -173,6 +189,13 @@ void fsl_spi_cpm_bufs_complete(struct mp + if (mspi->map_rx_dma) + dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); + mspi->xfer_in_progress = NULL; ++ ++ if (t->bits_per_word == 16 && t->rx_buf) { ++ int i; ++ ++ for (i = 0; i < t->len; i += 2) ++ le16_to_cpus(t->rx_buf + i); ++ } + } + EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete); + +--- a/drivers/spi/spi-fsl-spi.c ++++ b/drivers/spi/spi-fsl-spi.c +@@ -369,6 +369,9 @@ static int fsl_spi_do_one_msg(struct spi + return -EINVAL; + if (t->bits_per_word == 16 || t->bits_per_word == 32) + t->bits_per_word = 8; /* pretend its 8 bits */ ++ if (t->bits_per_word == 8 && t->len >= 256 && ++ (mpc8xxx_spi->flags & SPI_CPM1)) ++ t->bits_per_word = 16; + } + } + diff --git a/queue-5.4/spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch b/queue-5.4/spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch new file mode 100644 index 00000000000..f0936963cf2 --- /dev/null +++ b/queue-5.4/spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch @@ -0,0 +1,118 @@ +From christophe.leroy@csgroup.eu Mon May 15 15:08:03 2023 +From: Christophe Leroy +Date: Mon, 15 May 2023 16:07:16 +0200 +Subject: spi: fsl-spi: Re-organise transfer bits_per_word adaptation +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Mark Brown +Message-ID: <1e4bfb4850ba849c316f48a0ab0d7123da0e2f54.1684156552.git.christophe.leroy@csgroup.eu> + +From: Christophe Leroy + +(backported from upstream 8a5299a1278eadf1e08a598a5345c376206f171e) + +For different reasons, fsl-spi driver performs bits_per_word +modifications for different reasons: +- On CPU mode, to minimise amount of interrupts +- On CPM/QE mode to work around controller byte order + +For CPU mode that's done in fsl_spi_prepare_message() while +for CPM mode that's done in fsl_spi_setup_transfer(). + +Reunify all of it in fsl_spi_prepare_message(), and catch +impossible cases early through master's bits_per_word_mask +instead of returning EINVAL later. + +Signed-off-by: Christophe Leroy +Link: https://lore.kernel.org/r/0ce96fe96e8b07cba0613e4097cfd94d09b8919a.1680371809.git.christophe.leroy@csgroup.eu +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + drivers/spi/spi-fsl-spi.c | 50 +++++++++++++++++++++------------------------- + 1 file changed, 23 insertions(+), 27 deletions(-) + +--- a/drivers/spi/spi-fsl-spi.c ++++ b/drivers/spi/spi-fsl-spi.c +@@ -204,26 +204,6 @@ static int mspi_apply_cpu_mode_quirks(st + return bits_per_word; + } + +-static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, +- struct spi_device *spi, +- int bits_per_word) +-{ +- /* CPM/QE uses Little Endian for words > 8 +- * so transform 16 and 32 bits words into 8 bits +- * Unfortnatly that doesn't work for LSB so +- * reject these for now */ +- /* Note: 32 bits word, LSB works iff +- * tfcr/rfcr is set to CPMFCR_GBL */ +- if (spi->mode & SPI_LSB_FIRST && +- bits_per_word > 8) +- return -EINVAL; +- if (bits_per_word <= 8) +- return bits_per_word; +- if (bits_per_word == 16 || bits_per_word == 32) +- return 8; /* pretend its 8 bits */ +- return -EINVAL; +-} +- + static int fsl_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) + { +@@ -251,9 +231,6 @@ static int fsl_spi_setup_transfer(struct + bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, + mpc8xxx_spi, + bits_per_word); +- else +- bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, +- bits_per_word); + + if (bits_per_word < 0) + return bits_per_word; +@@ -371,14 +348,27 @@ static int fsl_spi_do_one_msg(struct spi + * In CPU mode, optimize large byte transfers to use larger + * bits_per_word values to reduce number of interrupts taken. + */ +- if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { +- list_for_each_entry(t, &m->transfers, transfer_list) { ++ list_for_each_entry(t, &m->transfers, transfer_list) { ++ if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { + if (t->len < 256 || t->bits_per_word != 8) + continue; + if ((t->len & 3) == 0) + t->bits_per_word = 32; + else if ((t->len & 1) == 0) + t->bits_per_word = 16; ++ } else { ++ /* ++ * CPM/QE uses Little Endian for words > 8 ++ * so transform 16 and 32 bits words into 8 bits ++ * Unfortnatly that doesn't work for LSB so ++ * reject these for now ++ * Note: 32 bits word, LSB works iff ++ * tfcr/rfcr is set to CPMFCR_GBL ++ */ ++ if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8) ++ return -EINVAL; ++ if (t->bits_per_word == 16 || t->bits_per_word == 32) ++ t->bits_per_word = 8; /* pretend its 8 bits */ + } + } + +@@ -637,8 +627,14 @@ static struct spi_master * fsl_spi_probe + if (mpc8xxx_spi->type == TYPE_GRLIB) + fsl_spi_grlib_probe(dev); + +- master->bits_per_word_mask = +- (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & ++ if (mpc8xxx_spi->flags & SPI_CPM_MODE) ++ master->bits_per_word_mask = ++ (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32)); ++ else ++ master->bits_per_word_mask = ++ (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)); ++ ++ master->bits_per_word_mask &= + SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); + + if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)