From: John Linn Date: Wed, 30 Nov 2011 00:48:45 +0000 (-0800) Subject: Xilinx: ARM: Hack for doing MIO and IO PLL for GEM testing X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=7cb1b84deb9a4882a417e25c7f19628802db5cd8;p=thirdparty%2Fu-boot.git Xilinx: ARM: Hack for doing MIO and IO PLL for GEM testing This should not live on and is only temporary til FSBL is working. --- diff --git a/board/xilinx/dfe/board.c b/board/xilinx/dfe/board.c index b61745da576..18b8b25cbe9 100644 --- a/board/xilinx/dfe/board.c +++ b/board/xilinx/dfe/board.c @@ -4,6 +4,7 @@ #include #include +#include "ps7_init_hw.h" #define PARPORT_CRTL_BASEADDR XPSS_CRTL_PARPORT_BASEADDR #define NOR_FLASH_BASEADDR XPSS_PARPORT0_BASEADDR @@ -19,20 +20,21 @@ #define NAND_FLASH_MODE (0x00000004) /**< NAND */ #define SD_MODE (0x00000005) /**< Secure Digital card */ - - DECLARE_GLOBAL_DATA_PTR; -/* Where should these really go? */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") static void Out32(u32 OutAddress, u32 Value) { *(volatile u32 *) OutAddress = Value; + dmb(); } static u32 In32(u32 InAddress) { - return *(u32 *) InAddress; + volatile u32 temp = *(volatile u32 *)InAddress; + dmb(); + return temp; } static void Out8(u32 OutAddress, u8 Value) @@ -93,8 +95,484 @@ void init_nor_flash() Out8(NOR_FLASH_BASEADDR, 0xF0); } +#define Xil_Out32 Out32 +#define Xil_In32 In32 + +#if 1 +/* PLL divisor */ +#define ARM_PLL_FDIV 40 +#define DDR_PLL_FDIV 24 +#define IO_PLL_FDIV 30 + +#define ARM_PLL_RES 2 +#define ARM_PLL_CP 2 +#define ARM_PLL_LOCK_CNT 250 + +#define DDR_PLL_RES 2 +#define DDR_PLL_CP 2 +#define DDR_PLL_LOCK_CNT 300 + +#define IO_PLL_RES 2 +#define IO_PLL_CP 12 +#define IO_PLL_LOCK_CNT 325 + +/* CPU */ +#define CPU_SRCSEL CPU_ARM_PLL +#define CPU_DIVISOR 2 +/* DDR */ +#define DDR_3XCLK_DIVISOR 2 +#define DDR_2XCLK_DIVISOR 6 +/* DCI */ +#define DCI_DIVISOR0 2 +#define DCI_DIVISOR1 40 +/* USB0 */ +#define USB0_SRCSEL IO_PLL +#define USB0_DIVISOR0 15 +#define USB0_DIVISOR1 1 +/* GEM0 RX */ +#define GEM0_RX_SRCSEL GEM0_MIO_RX_CLK +/* GEM0 */ +#define GEM0_SRCSEL IO_PLL +#define GEM0_DIVISOR0 40 // was 8 JHL +#define GEM0_DIVISOR1 1 +/* SMC */ +#define SMC_SRCSEL IO_PLL +#define SMC_DIVISOR 40 +/* LQSPI */ +#define LQSPI_SRCSEL IO_PLL +#define LQSPI_DIVISOR 10 +/* SDIO */ +#define SDIO0_CD_SEL 0 +#define SDIO0_WP_SEL 15 +#define SDIO_SRCSEL IO_PLL +#define SDIO_DIVISOR 20 +/* UART */ +#define UART_SRCSEL IO_PLL +#define UART_DIVISOR 20 +/* SPI */ +#define SPI_SRCSEL IO_PLL +#define SPI_DIVISOR 20 +/* CAN */ +#define CAN_SRCSEL IO_PLL +#define CAN_DIVISOR0 42 +#define CAN_DIVISOR1 1 +/* FPGA0 */ +#define FPGA0_SRCSEL IO_PLL +#define FPGA0_DIVISOR0 15 +#define FPGA0_DIVISOR1 1 +/* FPGA1 */ +#define FPGA1_SRCSEL IO_PLL +#define FPGA1_DIVISOR0 15 +#define FPGA1_DIVISOR1 1 +/* FPGA2 */ +#define FPGA2_SRCSEL IO_PLL +#define FPGA2_DIVISOR0 15 +#define FPGA2_DIVISOR1 1 +/* FPGA3 */ +#define FPGA3_SRCSEL IO_PLL +#define FPGA3_DIVISOR0 15 +#define FPGA3_DIVISOR1 1 +/* PCAP */ +#define PCAP_SRCSEL IO_PLL +#define PCAP_DIVISOR 15 +#endif +void memtest_mio_init(void) +{ + unsigned int RegVal=0; + + /* SLCR unlock */ + Xil_Out32(SLCR_UNLOCK, 0xDF0D); + + /* LSPI */ + RegVal = (LVCMOS18 | FAST_CMOS | MIO_LQSPI | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO1, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_LQSPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO2, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_LQSPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO3, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_LQSPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO4, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_LQSPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO5, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_LQSPI | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO6, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_LQSPI | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO8, RegVal); + + /* GEM0 */ + RegVal = (DISABLE_RCVR | LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO16, RegVal); + + RegVal = (DISABLE_RCVR | LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO17, RegVal); + + RegVal = (DISABLE_RCVR | LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO18, RegVal); + + RegVal = (DISABLE_RCVR | LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO19, RegVal); + + RegVal = (DISABLE_RCVR | LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO20, RegVal); + + RegVal = (DISABLE_RCVR | LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO21, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO22, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO23, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO24, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO25, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO26, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_GEM | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO27, RegVal); + + /* MDIO0 */ + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_MDIO0 | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO52, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_MDIO0 | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO53, RegVal); + + /* USB0 */ + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_GPIO | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO7, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO28, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO29, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO30, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO31, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO32, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO33, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO34, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO35, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO36, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO37, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO38, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_USB | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO39, RegVal); + + /* SPI1 */ + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_SPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO10, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_SPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO11, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_SPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO12, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_SPI | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO13, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_SPI | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO14, RegVal); + + /* SDIO0 */ + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_GPIO | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO0, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_GPIO | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO15, RegVal); + + RegVal = ((SDIO0_CD_SEL << SDIO0_CD_SEL_SHIFT) | SDIO0_WP_SEL); + Xil_Out32(SLCR_SDIO0_WP_CD, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_SDIO | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO40, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_SDIO | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO41, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_SDIO | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO42, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_SDIO | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO43, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_SDIO | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO44, RegVal); + + RegVal = (LVCMOS18 | FAST_CMOS | MIO_SDIO | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO45, RegVal); + + /* CAN0 */ + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_GPIO | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO9, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_CAN | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO46, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_CAN | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO47, RegVal); + + /* UART1 */ + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_UART | TRI_ENABLE_OUT); + Xil_Out32(SLCR_MIO48, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_UART | TRI_ENABLE_IN); + Xil_Out32(SLCR_MIO49, RegVal); + + /* I2C0 */ + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_I2C | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO50, RegVal); + + RegVal = (LVCMOS18 | SLOW_CMOS | MIO_I2C | TRI_ENABLE_IN_OUT); + Xil_Out32(SLCR_MIO51, RegVal); + + Xil_Out32(SLCR_LOCK, 0x767B); + +} + +void memtest_pll_init(void) +{ + /* SLCR unlock */ + Xil_Out32(SLCR_UNLOCK, 0xDF0D); + + /* ARM PLL initialization */ +// memtest_arm_pll_init(); + + /* DDR PLL initialization */ +// memtest_ddr_pll_init(); + + /* IO PLL initialization */ + memtest_io_pll_init(); + + /* SLCR lock */ + Xil_Out32(SLCR_LOCK, 0x767B); + +} + +void memtest_arm_pll_init(void) +{ + unsigned int RegVal=0; + + /* Upadte arm pll configuration */ + Xil_Out32(SLCR_ARM_PLL_CFG, ((ARM_PLL_LOCK_CNT << PLL_LOCK_CNT_SHIFT) | (ARM_PLL_CP << PLL_CP_SHIFT) | ( ARM_PLL_RES << PLL_RES_SHIFT))); + + /* Update slcr_pll_fbdiv value */ + RegVal = Xil_In32(SLCR_ARM_PLL_CTRL); + RegVal &= ~(0x7F << PLL_FDIV_SHIFT); + RegVal |= (ARM_PLL_FDIV << PLL_FDIV_SHIFT); + Xil_Out32(SLCR_ARM_PLL_CTRL, RegVal); + + /* Put PLL in bypass mode */ + RegVal = Xil_In32(SLCR_ARM_PLL_CTRL); + RegVal |= PLL_BYPASS_FORCE; + Xil_Out32(SLCR_ARM_PLL_CTRL, RegVal); + + /* Assert reset to PLL */ + RegVal = Xil_In32(SLCR_ARM_PLL_CTRL); + RegVal |= PLL_RESET; + Xil_Out32(SLCR_ARM_PLL_CTRL, RegVal); + + /* Deassert reset to PLL */ + RegVal = Xil_In32(SLCR_ARM_PLL_CTRL); + RegVal &= ~PLL_RESET; + Xil_Out32(SLCR_ARM_PLL_CTRL, RegVal); + + /* Check PLL is locked */ + while(!(Xil_In32(SLCR_PLL_STATUS) & 0x1)); + + /* Remove PLL bypass mode */ + RegVal = Xil_In32(SLCR_ARM_PLL_CTRL); + RegVal &= ~PLL_BYPASS_FORCE; + Xil_Out32(SLCR_ARM_PLL_CTRL, RegVal); + +} + +void memtest_ddr_pll_init(void) +{ + unsigned int RegVal=0; + + /* Upadte ddr pll configuration */ + Xil_Out32(SLCR_DDR_PLL_CFG, ((DDR_PLL_LOCK_CNT << PLL_LOCK_CNT_SHIFT) | (DDR_PLL_CP << PLL_CP_SHIFT) | (DDR_PLL_RES << PLL_RES_SHIFT))); + + /* Update slcr_pll_fbdiv value */ + RegVal = Xil_In32(SLCR_DDR_PLL_CTRL); + RegVal &= ~(0x7F << PLL_FDIV_SHIFT); + RegVal |= (DDR_PLL_FDIV << PLL_FDIV_SHIFT); + Xil_Out32(SLCR_DDR_PLL_CTRL, RegVal); + + /* Put PLL in bypass mode */ + RegVal = Xil_In32(SLCR_DDR_PLL_CTRL); + RegVal |= PLL_BYPASS_FORCE; + Xil_Out32(SLCR_DDR_PLL_CTRL, RegVal); + + /* Assert reset to PLL */ + RegVal = Xil_In32(SLCR_DDR_PLL_CTRL); + RegVal |= PLL_RESET; + Xil_Out32(SLCR_DDR_PLL_CTRL, RegVal); + + /* Deassert reset to PLL */ + RegVal = Xil_In32(SLCR_DDR_PLL_CTRL); + RegVal &= ~PLL_RESET; + Xil_Out32(SLCR_DDR_PLL_CTRL, RegVal); + + /* Check PLL is locked */ + while(!(Xil_In32(SLCR_PLL_STATUS) & 0x2)); + + /* Remove PLL bypass mode */ + RegVal = Xil_In32(SLCR_DDR_PLL_CTRL); + RegVal &= ~PLL_BYPASS_FORCE; + Xil_Out32(SLCR_DDR_PLL_CTRL, RegVal); +} + + +void memtest_io_pll_init(void) +{ + unsigned int RegVal=0; + + /* Upadte io pll configuration */ + Xil_Out32(SLCR_IO_PLL_CFG, ((IO_PLL_LOCK_CNT << PLL_LOCK_CNT_SHIFT) | (IO_PLL_CP << PLL_CP_SHIFT) | (IO_PLL_RES << PLL_RES_SHIFT))); + + /* Update slcr_pll_fbdiv value */ + RegVal = Xil_In32(SLCR_IO_PLL_CTRL); + RegVal &= ~(0x7F << PLL_FDIV_SHIFT); + RegVal |= (IO_PLL_FDIV << PLL_FDIV_SHIFT); + Xil_Out32(SLCR_IO_PLL_CTRL, RegVal); + + /* Put PLL in bypass mode */ + RegVal = Xil_In32(SLCR_IO_PLL_CTRL); + RegVal |= PLL_BYPASS_FORCE; + Xil_Out32(SLCR_IO_PLL_CTRL, RegVal); + + /* Assert reset to PLL */ + RegVal = Xil_In32(SLCR_IO_PLL_CTRL); + RegVal |= PLL_RESET; + Xil_Out32(SLCR_IO_PLL_CTRL, RegVal); + + /* Deassert reset to PLL */ + RegVal = Xil_In32(SLCR_IO_PLL_CTRL); + RegVal &= ~PLL_RESET; + Xil_Out32(SLCR_IO_PLL_CTRL, RegVal); + + /* Check PLL is locked */ + while(!(Xil_In32(SLCR_PLL_STATUS) & 0x4)); + + /* Remove PLL bypass mode */ + RegVal = Xil_In32(SLCR_IO_PLL_CTRL); + RegVal &= ~PLL_BYPASS_FORCE; + Xil_Out32(SLCR_IO_PLL_CTRL, RegVal); +} + + +void memtest_clock_init(void) +{ + + /* SLCR unlock */ + Xil_Out32(SLCR_UNLOCK, 0xDF0D); + + /* ARM */ + Xil_Out32(SLCR_ARM_CLK_CTRL, (CPU_PERI_CLKACT_ENABLE | CPU_1XCLKACT_ENABLE | CPU_2XCLKACT_ENABLE | CPU_3OR2XCLKACT_ENABLE | + CPU_6OR4XCLKACT_ENABLE | (CPU_DIVISOR << CPU_DIVISOR_SHIFT) | (CPU_SRCSEL << CPU_SRCSEL_SHIFT))); + + /* DDR */ + Xil_Out32(SLCR_DDR_CLK_CTRL, ((DDR_2XCLK_DIVISOR << DDR_2XCLK_DIVISOR_SHIFT) | (DDR_3XCLK_DIVISOR << DDR_3XCLK_DIVISOR_SHIFT) | + DDR_2XCLKACT_ENABLE | DDR_3XCLKACT_ENABLE)); + + /* QSPI */ + Xil_Out32(SLCR_LQSPI_CLK_CTRL, ((LQSPI_DIVISOR << LQSPI_DIVISOR_SHIFT) | (LQSPI_SRCSEL << LQSPI_SRCSEL_SHIFT) | LQSPI_CLKACT_ENABLE)); + + /* GEM0 */ + Xil_Out32(SLCR_GEM0_RCLK_CTRL, ((GEM0_RX_SRCSEL << GEM0_RX_SRCSEL_SHIFT) | GEM0_RX_CLKACT_ENABLE)); + Xil_Out32(SLCR_GEM0_CLK_CTRL, ((GEM0_DIVISOR1 << GEM0_DIVISOR1_SHIFT) | (GEM0_DIVISOR0 << GEM0_DIVISOR0_SHIFT) | (GEM0_SRCSEL << GEM0_SRCSEL_SHIFT) | GEM0_CLKACT_ENABLE)); + + /* USB0 */ + /* USB Reference clock coming in externally hence no need to set */ + Xil_Out32(SLCR_USB0_CLK_CTRL, ((USB0_DIVISOR1 << USB0_DIVISOR1_SHIFT) | (USB0_DIVISOR0 << USB0_DIVISOR0_SHIFT) | (USB0_SRCSEL << USB0_SRCSEL_SHIFT) | USB0_CLKACT_ENABLE)); + + /* SPI1 */ + Xil_Out32(SLCR_SPI_CLK_CTRL, ((SPI_DIVISOR << SPI_DIVISOR_SHIFT) | (SPI_SRCSEL << SPI_SRCSEL_SHIFT) | SPI1_CLKACT_ENABLE)); + + /* SDIO0 */ + Xil_Out32(SLCR_SDIO_CLK_CTRL, ((SDIO_DIVISOR << SDIO_DIVISOR_SHIFT)| (SDIO_SRCSEL << SDIO_SRCSEL_SHIFT) | SDIO0_CLKACT_ENABLE)); + + /* CAN0 */ + Xil_Out32(SLCR_CAN_CLK_CTRL, ((CAN_DIVISOR1 << CAN_DIVISOR1_SHIFT) | (CAN_DIVISOR0 << CAN_DIVISOR0_SHIFT) | (CAN_SRCSEL << CAN_SRCSEL_SHIFT) | CAN0_CLKACT_ENABLE)); + + /* UART1 */ + Xil_Out32(SLCR_UART_CLK_CTRL, ((UART_DIVISOR << UART_DIVISOR_SHIFT) | (UART_SRCSEL << UART_SRCSEL_SHIFT) | UART1_CLKACT_ENABLE)); + + /* FPGA0 */ + Xil_Out32(SLCR_FPGA0_CLK_CTRL, ((FPGA0_DIVISOR1 << FPGA0_DIVISOR1_SHIFT) | (FPGA0_DIVISOR0 << FPGA0_DIVISOR0_SHIFT) | (FPGA0_SRCSEL << FPGA0_SRCSEL_SHIFT))); + + /* FPGA1 */ + Xil_Out32(SLCR_FPGA1_CLK_CTRL, ((FPGA1_DIVISOR1 << FPGA1_DIVISOR1_SHIFT) | (FPGA1_DIVISOR0 << FPGA1_DIVISOR0_SHIFT) | (FPGA1_SRCSEL << FPGA1_SRCSEL_SHIFT))); + + /* FPGA2 */ + Xil_Out32(SLCR_FPGA2_CLK_CTRL, ((FPGA2_DIVISOR1 << FPGA2_DIVISOR1_SHIFT) | (FPGA2_DIVISOR0 << FPGA2_DIVISOR0_SHIFT) | (FPGA2_SRCSEL << FPGA2_SRCSEL_SHIFT))); + + /* FPGA3 */ + Xil_Out32(SLCR_FPGA3_CLK_CTRL, ((FPGA3_DIVISOR1 << FPGA3_DIVISOR1_SHIFT) | (FPGA3_DIVISOR0 << FPGA3_DIVISOR0_SHIFT) | (FPGA3_SRCSEL << FPGA3_SRCSEL_SHIFT))); + + /* PCAP */ + Xil_Out32(SLCR_PCAP_CLK_CTRL, ((PCAP_DIVISOR << PCAP_DIVISOR_SHIFT) | (PCAP_SRCSEL << PCAP_SRCSEL_SHIFT) | PCAP_CLKACT_ENABLE)); + + /*IIC0*/ + /*MDIO0*/ + /*GPIO*/ + /* Enable interface clock */ + Xil_Out32(SLCR_APER_CLK_CTRL, (SLCR_DMA_CPU_2XCLKACT_ENABLE | SLCR_USB0_CPU_1XCLKACT_ENABLE | SLCR_GEM0_CPU_1XCLKACT_ENABLE | + SLCR_SDI0_CPU_1XCLKACT_ENABLE | SLCR_SPI1_CPU_1XCLKACT_ENABLE | SLCR_CAN0_CPU_1XCLKACT_ENABLE | + SLCR_I2C0_CPU_1XCLKACT_ENABLE | SLCR_UART1_CPU_1XCLKACT_ENABLE | SLCR_GPIO_CPU_1XCLKACT_ENABLE | + SLCR_LQSPI_CPU_1XCLKACT_ENABLE | SLCR_SMC_CPU_1XCLKACT_ENABLE)); + + /* DCI */ + Xil_Out32(SLCR_DCI_CLK_CTRL, ((DCI_DIVISOR1 << DCI_DIVISOR1_SHIFT) | (DCI_DIVISOR0 << DCI_DIVISOR0_SHIFT) | DCI_CLKACT_ENABLE)); + + /* SLCR lock */ + Xil_Out32(SLCR_LOCK, 0x767B); +} + +int from_burst_main() +{ + memtest_mio_init(); + memtest_pll_init(); + memtest_clock_init(); +} + int board_init(void) { + from_burst_main(); + icache_enable(); init_nor_flash();