From: Greg Kroah-Hartman Date: Wed, 11 Sep 2024 13:03:07 +0000 (+0200) Subject: drop clk patch from all branches X-Git-Tag: v4.19.322~5 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=801ae12521f066409bbf65943c103f33d66fc513;p=thirdparty%2Fkernel%2Fstable-queue.git drop clk patch from all branches --- diff --git a/queue-5.15/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch b/queue-5.15/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch deleted file mode 100644 index 93ee013c77f..00000000000 --- a/queue-5.15/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001 -From: Satya Priya Kakitapalli -Date: Wed, 31 Jul 2024 11:59:12 +0530 -Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL - -From: Satya Priya Kakitapalli - -commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream. - -The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha -value is greater than 0.5, the L value needs to be adjusted accordingly. -Thus update the logic to handle the signed alpha val. - -Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") -Cc: stable@vger.kernel.org -Signed-off-by: Satya Priya Kakitapalli -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com -Signed-off-by: Bjorn Andersson -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/clk/qcom/clk-alpha-pll.c -+++ b/drivers/clk/qcom/clk-alpha-pll.c -@@ -39,6 +39,7 @@ - #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) - # define PLL_POST_DIV_SHIFT 8 - # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) -+# define PLL_ALPHA_MSB BIT(15) - # define PLL_ALPHA_EN BIT(24) - # define PLL_ALPHA_MODE BIT(25) - # define PLL_VCO_SHIFT 20 -@@ -1913,6 +1914,18 @@ static void clk_zonda_pll_disable(struct - regmap_write(regmap, PLL_OPMODE(pll), 0x0); - } - -+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) -+{ -+ u64 remainder, quotient; -+ -+ quotient = rate; -+ remainder = do_div(quotient, prate); -+ *l = quotient; -+ -+ if ((remainder * 2) / prate) -+ *l = *l + 1; -+} -+ - static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) - { -@@ -1929,6 +1942,9 @@ static int clk_zonda_pll_set_rate(struct - if (ret < 0) - return ret; - -+ if (a & PLL_ALPHA_MSB) -+ zonda_pll_adjust_l_val(rate, prate, &l); -+ - regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); - regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); - diff --git a/queue-5.15/series b/queue-5.15/series index db3fabf2f43..5d23b35200e 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -80,7 +80,6 @@ fuse-use-unsigned-type-for-getxattr-listxattr-size-truncation.patch clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch -clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch tracing-avoid-possible-softlockup-in-tracing_iter_reset.patch ila-call-nf_unregister_net_hooks-sooner.patch diff --git a/queue-6.1/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch b/queue-6.1/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch deleted file mode 100644 index 3536757496e..00000000000 --- a/queue-6.1/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001 -From: Satya Priya Kakitapalli -Date: Wed, 31 Jul 2024 11:59:12 +0530 -Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL - -From: Satya Priya Kakitapalli - -commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream. - -The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha -value is greater than 0.5, the L value needs to be adjusted accordingly. -Thus update the logic to handle the signed alpha val. - -Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") -Cc: stable@vger.kernel.org -Signed-off-by: Satya Priya Kakitapalli -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com -Signed-off-by: Bjorn Andersson -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/clk/qcom/clk-alpha-pll.c -+++ b/drivers/clk/qcom/clk-alpha-pll.c -@@ -41,6 +41,7 @@ - #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) - # define PLL_POST_DIV_SHIFT 8 - # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) -+# define PLL_ALPHA_MSB BIT(15) - # define PLL_ALPHA_EN BIT(24) - # define PLL_ALPHA_MODE BIT(25) - # define PLL_VCO_SHIFT 20 -@@ -1986,6 +1987,18 @@ static void clk_zonda_pll_disable(struct - regmap_write(regmap, PLL_OPMODE(pll), 0x0); - } - -+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) -+{ -+ u64 remainder, quotient; -+ -+ quotient = rate; -+ remainder = do_div(quotient, prate); -+ *l = quotient; -+ -+ if ((remainder * 2) / prate) -+ *l = *l + 1; -+} -+ - static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) - { -@@ -2002,6 +2015,9 @@ static int clk_zonda_pll_set_rate(struct - if (ret < 0) - return ret; - -+ if (a & PLL_ALPHA_MSB) -+ zonda_pll_adjust_l_val(rate, prate, &l); -+ - regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); - regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); - diff --git a/queue-6.1/series b/queue-6.1/series index 88160150eda..a9f49c12cd0 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -26,7 +26,6 @@ fuse-use-unsigned-type-for-getxattr-listxattr-size-truncation.patch clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch -clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch spi-rockchip-resolve-unbalanced-runtime-pm-system-pm-handling.patch tracing-avoid-possible-softlockup-in-tracing_iter_reset.patch diff --git a/queue-6.10/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch b/queue-6.10/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch deleted file mode 100644 index 32d84e92da6..00000000000 --- a/queue-6.10/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001 -From: Satya Priya Kakitapalli -Date: Wed, 31 Jul 2024 11:59:12 +0530 -Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL - -From: Satya Priya Kakitapalli - -commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream. - -The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha -value is greater than 0.5, the L value needs to be adjusted accordingly. -Thus update the logic to handle the signed alpha val. - -Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") -Cc: stable@vger.kernel.org -Signed-off-by: Satya Priya Kakitapalli -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com -Signed-off-by: Bjorn Andersson -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/clk/qcom/clk-alpha-pll.c -+++ b/drivers/clk/qcom/clk-alpha-pll.c -@@ -41,6 +41,7 @@ - #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) - # define PLL_POST_DIV_SHIFT 8 - # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) -+# define PLL_ALPHA_MSB BIT(15) - # define PLL_ALPHA_EN BIT(24) - # define PLL_ALPHA_MODE BIT(25) - # define PLL_VCO_SHIFT 20 -@@ -2070,6 +2071,18 @@ static void clk_zonda_pll_disable(struct - regmap_write(regmap, PLL_OPMODE(pll), 0x0); - } - -+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) -+{ -+ u64 remainder, quotient; -+ -+ quotient = rate; -+ remainder = do_div(quotient, prate); -+ *l = quotient; -+ -+ if ((remainder * 2) / prate) -+ *l = *l + 1; -+} -+ - static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) - { -@@ -2086,6 +2099,9 @@ static int clk_zonda_pll_set_rate(struct - if (ret < 0) - return ret; - -+ if (a & PLL_ALPHA_MSB) -+ zonda_pll_adjust_l_val(rate, prate, &l); -+ - regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); - regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); - diff --git a/queue-6.10/series b/queue-6.10/series index 1fbaece41fa..1ce76fb06f5 100644 --- a/queue-6.10/series +++ b/queue-6.10/series @@ -47,7 +47,6 @@ clk-starfive-jh7110-sys-add-notifier-for-pll0-clock.patch clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch -clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch pinctrl-qcom-x1e80100-bypass-pdc-wakeup-parent-for-now.patch can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch mm-vmalloc-optimize-vmap_lazy_nr-arithmetic-when-purging-each-vmap_area.patch diff --git a/queue-6.6/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch b/queue-6.6/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch deleted file mode 100644 index cd372a59c10..00000000000 --- a/queue-6.6/clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001 -From: Satya Priya Kakitapalli -Date: Wed, 31 Jul 2024 11:59:12 +0530 -Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL - -From: Satya Priya Kakitapalli - -commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream. - -The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha -value is greater than 0.5, the L value needs to be adjusted accordingly. -Thus update the logic to handle the signed alpha val. - -Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") -Cc: stable@vger.kernel.org -Signed-off-by: Satya Priya Kakitapalli -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com -Signed-off-by: Bjorn Andersson -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/clk/qcom/clk-alpha-pll.c -+++ b/drivers/clk/qcom/clk-alpha-pll.c -@@ -41,6 +41,7 @@ - #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) - # define PLL_POST_DIV_SHIFT 8 - # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) -+# define PLL_ALPHA_MSB BIT(15) - # define PLL_ALPHA_EN BIT(24) - # define PLL_ALPHA_MODE BIT(25) - # define PLL_VCO_SHIFT 20 -@@ -2043,6 +2044,18 @@ static void clk_zonda_pll_disable(struct - regmap_write(regmap, PLL_OPMODE(pll), 0x0); - } - -+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) -+{ -+ u64 remainder, quotient; -+ -+ quotient = rate; -+ remainder = do_div(quotient, prate); -+ *l = quotient; -+ -+ if ((remainder * 2) / prate) -+ *l = *l + 1; -+} -+ - static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) - { -@@ -2059,6 +2072,9 @@ static int clk_zonda_pll_set_rate(struct - if (ret < 0) - return ret; - -+ if (a & PLL_ALPHA_MSB) -+ zonda_pll_adjust_l_val(rate, prate, &l); -+ - regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); - regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); - diff --git a/queue-6.6/series b/queue-6.6/series index 26eb255c9b4..a3fcbc2810a 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -33,7 +33,6 @@ clk-starfive-jh7110-sys-add-notifier-for-pll0-clock.patch clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch -clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch kexec_file-fix-elfcorehdr-digest-exclusion-when-config_crash_hotplug-y.patch mm-vmalloc-ensure-vmap_block-is-initialised-before-adding-to-queue.patch