From: Greg Kroah-Hartman Date: Fri, 21 Jul 2023 12:21:18 +0000 (+0200) Subject: drop some 6.4 and 6.1 drm patches X-Git-Tag: v5.15.121~32 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=816dc908fa67013db42d361273bcd240d8aac998;p=thirdparty%2Fkernel%2Fstable-queue.git drop some 6.4 and 6.1 drm patches --- diff --git a/queue-6.1/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch b/queue-6.1/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch deleted file mode 100644 index 1af1509abb1..00000000000 --- a/queue-6.1/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch +++ /dev/null @@ -1,140 +0,0 @@ -From e701156ccc6c7a5f104a968dda74cd6434178712 Mon Sep 17 00:00:00 2001 -From: Mario Limonciello -Date: Fri, 7 Jul 2023 21:26:09 -0500 -Subject: drm/amd: Align SMU11 SMU_MSG_OverridePcieParameters implementation with SMU13 - -From: Mario Limonciello - -commit e701156ccc6c7a5f104a968dda74cd6434178712 upstream. - -SMU13 overrides dynamic PCIe lane width and dynamic speed by when on -certain hosts. commit 38e4ced80479 ("drm/amd/pm: conditionally disable -pcie lane switching for some sienna_cichlid SKUs") worked around this -issue by setting up certain SKUs to set up certain limits, but the same -fundamental problem with those hosts affects all SMU11 implmentations -as well, so align the SMU11 and SMU13 driver handling. - -Signed-off-by: Mario Limonciello -Reviewed-by: Evan Quan -Signed-off-by: Alex Deucher -Cc: stable@vger.kernel.org # 6.1.x -Signed-off-by: Greg Kroah-Hartman ---- - .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 89 ++++--------------- - 1 file changed, 18 insertions(+), 71 deletions(-) - -diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c -index 8fe2e1716da4..f6599c00a6fd 100644 ---- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c -+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c -@@ -2077,89 +2077,36 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context - return ret; - } - --static void sienna_cichlid_get_override_pcie_settings(struct smu_context *smu, -- uint32_t *gen_speed_override, -- uint32_t *lane_width_override) --{ -- struct amdgpu_device *adev = smu->adev; -- -- *gen_speed_override = 0xff; -- *lane_width_override = 0xff; -- -- switch (adev->pdev->device) { -- case 0x73A0: -- case 0x73A1: -- case 0x73A2: -- case 0x73A3: -- case 0x73AB: -- case 0x73AE: -- /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */ -- *lane_width_override = 6; -- break; -- case 0x73E0: -- case 0x73E1: -- case 0x73E3: -- *lane_width_override = 4; -- break; -- case 0x7420: -- case 0x7421: -- case 0x7422: -- case 0x7423: -- case 0x7424: -- *lane_width_override = 3; -- break; -- default: -- break; -- } --} -- --#define MAX(a, b) ((a) > (b) ? (a) : (b)) -- - static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, - uint32_t pcie_gen_cap, - uint32_t pcie_width_cap) - { - struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; -- uint32_t gen_speed_override, lane_width_override; -- uint8_t *table_member1, *table_member2; -- uint32_t min_gen_speed, max_gen_speed; -- uint32_t min_lane_width, max_lane_width; -- uint32_t smu_pcie_arg; -+ u32 smu_pcie_arg; - int ret, i; - -- GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); -- GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); -- -- sienna_cichlid_get_override_pcie_settings(smu, -- &gen_speed_override, -- &lane_width_override); -+ /* PCIE gen speed and lane width override */ -+ if (!amdgpu_device_pcie_dynamic_switching_supported()) { -+ if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap) -+ pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1]; - -- /* PCIE gen speed override */ -- if (gen_speed_override != 0xff) { -- min_gen_speed = MIN(pcie_gen_cap, gen_speed_override); -- max_gen_speed = MIN(pcie_gen_cap, gen_speed_override); -- } else { -- min_gen_speed = MAX(0, table_member1[0]); -- max_gen_speed = MIN(pcie_gen_cap, table_member1[1]); -- min_gen_speed = min_gen_speed > max_gen_speed ? -- max_gen_speed : min_gen_speed; -- } -- pcie_table->pcie_gen[0] = min_gen_speed; -- pcie_table->pcie_gen[1] = max_gen_speed; -+ if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap) -+ pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1]; - -- /* PCIE lane width override */ -- if (lane_width_override != 0xff) { -- min_lane_width = MIN(pcie_width_cap, lane_width_override); -- max_lane_width = MIN(pcie_width_cap, lane_width_override); -+ /* Force all levels to use the same settings */ -+ for (i = 0; i < NUM_LINK_LEVELS; i++) { -+ pcie_table->pcie_gen[i] = pcie_gen_cap; -+ pcie_table->pcie_lane[i] = pcie_width_cap; -+ } - } else { -- min_lane_width = MAX(1, table_member2[0]); -- max_lane_width = MIN(pcie_width_cap, table_member2[1]); -- min_lane_width = min_lane_width > max_lane_width ? -- max_lane_width : min_lane_width; -+ for (i = 0; i < NUM_LINK_LEVELS; i++) { -+ if (pcie_table->pcie_gen[i] > pcie_gen_cap) -+ pcie_table->pcie_gen[i] = pcie_gen_cap; -+ if (pcie_table->pcie_lane[i] > pcie_width_cap) -+ pcie_table->pcie_lane[i] = pcie_width_cap; -+ } - } -- pcie_table->pcie_lane[0] = min_lane_width; -- pcie_table->pcie_lane[1] = max_lane_width; - - for (i = 0; i < NUM_LINK_LEVELS; i++) { - smu_pcie_arg = (i << 16 | --- -2.41.0 - diff --git a/queue-6.1/drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch b/queue-6.1/drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch deleted file mode 100644 index 22ab85683bc..00000000000 --- a/queue-6.1/drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 4481913607e58196c48a4fef5e6f45350684ec3c Mon Sep 17 00:00:00 2001 -From: Yunxiang Li -Date: Thu, 22 Jun 2023 10:18:03 -0400 -Subject: drm/ttm: fix bulk_move corruption when adding a entry -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Yunxiang Li - -commit 4481913607e58196c48a4fef5e6f45350684ec3c upstream. - -When the resource is the first in the bulk_move range, adding it again -(thus moving it to the tail) will corrupt the list since the first -pointer is not moved. This eventually lead to null pointer deref in -ttm_lru_bulk_move_del() - -Fixes: fee2ede15542 ("drm/ttm: rework bulk move handling v5") -Signed-off-by: Yunxiang Li -Reviewed-by: Christian König -CC: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20230622141902.28718-3-Yunxiang.Li@amd.com -Signed-off-by: Christian König -Signed-off-by: Greg Kroah-Hartman ---- - drivers/gpu/drm/ttm/ttm_resource.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/ttm/ttm_resource.c -+++ b/drivers/gpu/drm/ttm/ttm_resource.c -@@ -85,6 +85,8 @@ static void ttm_lru_bulk_move_pos_tail(s - struct ttm_resource *res) - { - if (pos->last != res) { -+ if (pos->first == res) -+ pos->first = list_next_entry(res, lru); - list_move(&res->lru, &pos->last->lru); - pos->last = res; - } -@@ -110,7 +112,8 @@ static void ttm_lru_bulk_move_del(struct - { - struct ttm_lru_bulk_move_pos *pos = ttm_lru_bulk_move_pos(bulk, res); - -- if (unlikely(pos->first == res && pos->last == res)) { -+ if (unlikely(WARN_ON(!pos->first || !pos->last) || -+ pos->first == res && pos->last == res)) { - pos->first = NULL; - pos->last = NULL; - } else if (pos->first == res) { diff --git a/queue-6.1/series b/queue-6.1/series index a12eb0439af..3fbaafe95af 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -148,12 +148,10 @@ drm-amd-display-remove-phantom-pipe-check-when-calculating-k1-and-k2.patch drm-amd-display-disable-seamless-boot-if-force_odm_combine-is-enabled.patch drm-amdgpu-fix-clearing-mappings-for-bos-that-are-always-valid-in-vm.patch drm-amd-disable-psr-su-on-parade-0803-tcon.patch -drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch drm-amd-display-add-a-null-pointer-check.patch drm-amd-display-correct-dmub_fw_version-macro.patch drm-amd-display-add-monitor-specific-edid-quirk.patch drm-amdgpu-avoid-restore-process-run-into-dead-loop.patch -drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch drm-ttm-don-t-leak-a-resource-on-swapout-move-error.patch drm-ttm-never-consider-pinned-bos-for-eviction-swap.patch serial-atmel-don-t-enable-irqs-prematurely.patch diff --git a/queue-6.4/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch b/queue-6.4/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch deleted file mode 100644 index 79e37721d85..00000000000 --- a/queue-6.4/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch +++ /dev/null @@ -1,137 +0,0 @@ -From e701156ccc6c7a5f104a968dda74cd6434178712 Mon Sep 17 00:00:00 2001 -From: Mario Limonciello -Date: Fri, 7 Jul 2023 21:26:09 -0500 -Subject: drm/amd: Align SMU11 SMU_MSG_OverridePcieParameters implementation with SMU13 - -From: Mario Limonciello - -commit e701156ccc6c7a5f104a968dda74cd6434178712 upstream. - -SMU13 overrides dynamic PCIe lane width and dynamic speed by when on -certain hosts. commit 38e4ced80479 ("drm/amd/pm: conditionally disable -pcie lane switching for some sienna_cichlid SKUs") worked around this -issue by setting up certain SKUs to set up certain limits, but the same -fundamental problem with those hosts affects all SMU11 implmentations -as well, so align the SMU11 and SMU13 driver handling. - -Signed-off-by: Mario Limonciello -Reviewed-by: Evan Quan -Signed-off-by: Alex Deucher -Cc: stable@vger.kernel.org # 6.1.x -Signed-off-by: Greg Kroah-Hartman ---- - drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 93 +++------------- - 1 file changed, 20 insertions(+), 73 deletions(-) - ---- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c -+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c -@@ -2077,89 +2077,36 @@ static int sienna_cichlid_display_disabl - return ret; - } - --static void sienna_cichlid_get_override_pcie_settings(struct smu_context *smu, -- uint32_t *gen_speed_override, -- uint32_t *lane_width_override) --{ -- struct amdgpu_device *adev = smu->adev; -- -- *gen_speed_override = 0xff; -- *lane_width_override = 0xff; -- -- switch (adev->pdev->device) { -- case 0x73A0: -- case 0x73A1: -- case 0x73A2: -- case 0x73A3: -- case 0x73AB: -- case 0x73AE: -- /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */ -- *lane_width_override = 6; -- break; -- case 0x73E0: -- case 0x73E1: -- case 0x73E3: -- *lane_width_override = 4; -- break; -- case 0x7420: -- case 0x7421: -- case 0x7422: -- case 0x7423: -- case 0x7424: -- *lane_width_override = 3; -- break; -- default: -- break; -- } --} -- --#define MAX(a, b) ((a) > (b) ? (a) : (b)) -- - static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, - uint32_t pcie_gen_cap, - uint32_t pcie_width_cap) - { - struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; -- uint32_t gen_speed_override, lane_width_override; -- uint8_t *table_member1, *table_member2; -- uint32_t min_gen_speed, max_gen_speed; -- uint32_t min_lane_width, max_lane_width; -- uint32_t smu_pcie_arg; -+ u32 smu_pcie_arg; - int ret, i; - -- GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); -- GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); -- -- sienna_cichlid_get_override_pcie_settings(smu, -- &gen_speed_override, -- &lane_width_override); -- -- /* PCIE gen speed override */ -- if (gen_speed_override != 0xff) { -- min_gen_speed = MIN(pcie_gen_cap, gen_speed_override); -- max_gen_speed = MIN(pcie_gen_cap, gen_speed_override); -- } else { -- min_gen_speed = MAX(0, table_member1[0]); -- max_gen_speed = MIN(pcie_gen_cap, table_member1[1]); -- min_gen_speed = min_gen_speed > max_gen_speed ? -- max_gen_speed : min_gen_speed; -- } -- pcie_table->pcie_gen[0] = min_gen_speed; -- pcie_table->pcie_gen[1] = max_gen_speed; -- -- /* PCIE lane width override */ -- if (lane_width_override != 0xff) { -- min_lane_width = MIN(pcie_width_cap, lane_width_override); -- max_lane_width = MIN(pcie_width_cap, lane_width_override); -+ /* PCIE gen speed and lane width override */ -+ if (!amdgpu_device_pcie_dynamic_switching_supported()) { -+ if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap) -+ pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1]; -+ -+ if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap) -+ pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1]; -+ -+ /* Force all levels to use the same settings */ -+ for (i = 0; i < NUM_LINK_LEVELS; i++) { -+ pcie_table->pcie_gen[i] = pcie_gen_cap; -+ pcie_table->pcie_lane[i] = pcie_width_cap; -+ } - } else { -- min_lane_width = MAX(1, table_member2[0]); -- max_lane_width = MIN(pcie_width_cap, table_member2[1]); -- min_lane_width = min_lane_width > max_lane_width ? -- max_lane_width : min_lane_width; -+ for (i = 0; i < NUM_LINK_LEVELS; i++) { -+ if (pcie_table->pcie_gen[i] > pcie_gen_cap) -+ pcie_table->pcie_gen[i] = pcie_gen_cap; -+ if (pcie_table->pcie_lane[i] > pcie_width_cap) -+ pcie_table->pcie_lane[i] = pcie_width_cap; -+ } - } -- pcie_table->pcie_lane[0] = min_lane_width; -- pcie_table->pcie_lane[1] = max_lane_width; - - for (i = 0; i < NUM_LINK_LEVELS; i++) { - smu_pcie_arg = (i << 16 | diff --git a/queue-6.4/drm-amd-pm-fix-smu-i2c-data-read-risk.patch b/queue-6.4/drm-amd-pm-fix-smu-i2c-data-read-risk.patch index eb62edc6731..f974ec36f5c 100644 --- a/queue-6.4/drm-amd-pm-fix-smu-i2c-data-read-risk.patch +++ b/queue-6.4/drm-amd-pm-fix-smu-i2c-data-read-risk.patch @@ -65,7 +65,7 @@ Signed-off-by: Greg Kroah-Hartman } --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c -@@ -3789,7 +3789,6 @@ static int sienna_cichlid_i2c_xfer(struc +@@ -3842,7 +3842,6 @@ static int sienna_cichlid_i2c_xfer(struc } mutex_lock(&adev->pm.mutex); r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); @@ -73,7 +73,7 @@ Signed-off-by: Greg Kroah-Hartman if (r) goto fail; -@@ -3806,6 +3805,7 @@ static int sienna_cichlid_i2c_xfer(struc +@@ -3859,6 +3858,7 @@ static int sienna_cichlid_i2c_xfer(struc } r = num_msgs; fail: diff --git a/queue-6.4/drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch b/queue-6.4/drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch deleted file mode 100644 index 766cff776e7..00000000000 --- a/queue-6.4/drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 4481913607e58196c48a4fef5e6f45350684ec3c Mon Sep 17 00:00:00 2001 -From: Yunxiang Li -Date: Thu, 22 Jun 2023 10:18:03 -0400 -Subject: drm/ttm: fix bulk_move corruption when adding a entry -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Yunxiang Li - -commit 4481913607e58196c48a4fef5e6f45350684ec3c upstream. - -When the resource is the first in the bulk_move range, adding it again -(thus moving it to the tail) will corrupt the list since the first -pointer is not moved. This eventually lead to null pointer deref in -ttm_lru_bulk_move_del() - -Fixes: fee2ede15542 ("drm/ttm: rework bulk move handling v5") -Signed-off-by: Yunxiang Li -Reviewed-by: Christian König -CC: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20230622141902.28718-3-Yunxiang.Li@amd.com -Signed-off-by: Christian König -Signed-off-by: Greg Kroah-Hartman ---- - drivers/gpu/drm/ttm/ttm_resource.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/ttm/ttm_resource.c -+++ b/drivers/gpu/drm/ttm/ttm_resource.c -@@ -86,6 +86,8 @@ static void ttm_lru_bulk_move_pos_tail(s - struct ttm_resource *res) - { - if (pos->last != res) { -+ if (pos->first == res) -+ pos->first = list_next_entry(res, lru); - list_move(&res->lru, &pos->last->lru); - pos->last = res; - } -@@ -111,7 +113,8 @@ static void ttm_lru_bulk_move_del(struct - { - struct ttm_lru_bulk_move_pos *pos = ttm_lru_bulk_move_pos(bulk, res); - -- if (unlikely(pos->first == res && pos->last == res)) { -+ if (unlikely(WARN_ON(!pos->first || !pos->last) || -+ pos->first == res && pos->last == res)) { - pos->first = NULL; - pos->last = NULL; - } else if (pos->first == res) { diff --git a/queue-6.4/series b/queue-6.4/series index 4af1fc51da5..58da1e1ff26 100644 --- a/queue-6.4/series +++ b/queue-6.4/series @@ -202,14 +202,12 @@ drm-amd-display-remove-phantom-pipe-check-when-calculating-k1-and-k2.patch drm-amd-display-disable-seamless-boot-if-force_odm_combine-is-enabled.patch drm-amdgpu-fix-clearing-mappings-for-bos-that-are-always-valid-in-vm.patch drm-amd-disable-psr-su-on-parade-0803-tcon.patch -drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch drm-amd-display-add-a-null-pointer-check.patch drm-amd-display-fix-128b132b-link-loss-handling.patch drm-amd-display-correct-dmub_fw_version-macro.patch drm-amd-display-add-monitor-specific-edid-quirk.patch drm-amdgpu-avoid-restore-process-run-into-dead-loop.patch drm-amd-pm-fix-smu-i2c-data-read-risk.patch -drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch drm-ttm-don-t-leak-a-resource-on-eviction-error.patch drm-ttm-don-t-leak-a-resource-on-swapout-move-error.patch drm-ttm-never-consider-pinned-bos-for-eviction-swap.patch