From: Sasha Levin Date: Mon, 12 Aug 2024 01:09:16 +0000 (-0400) Subject: Fixes for 5.10 X-Git-Tag: v6.1.105~98 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=827644c700484429b41dd33ca253599ec2531c36;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.10 Signed-off-by: Sasha Levin --- diff --git a/queue-5.10/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch b/queue-5.10/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch new file mode 100644 index 00000000000..42687b871ec --- /dev/null +++ b/queue-5.10/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch @@ -0,0 +1,44 @@ +From 2c692b85d27842a0c67689019a13342acdf30e5f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Aug 2024 10:18:01 +0200 +Subject: ALSA: usb-audio: Re-add ScratchAmp quirk entries + +From: Takashi Iwai + +[ Upstream commit 03898691d42e0170e7d00f07cbe21ce0e9f3a8fa ] + +At the code refactoring of USB-audio quirk handling, I assumed that +the quirk entries of Stanton ScratchAmp devices were only about the +device name, and moved them completely into the rename table. +But it seems that the device requires the quirk entry so that it's +probed by the driver itself. + +This re-adds back the quirk entries of ScratchAmp, but in a +minimalistic manner. + +Fixes: 5436f59bc5bc ("ALSA: usb-audio: Move device rename and profile quirks to an internal table") +Link: https://patch.msgid.link/20240808081803.22300-1-tiwai@suse.de +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/quirks-table.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h +index 97fe2fadcafb3..8f2fb2ac7af67 100644 +--- a/sound/usb/quirks-table.h ++++ b/sound/usb/quirks-table.h +@@ -2573,6 +2573,10 @@ YAMAHA_DEVICE(0x7010, "UB99"), + } + }, + ++/* Stanton ScratchAmp */ ++{ USB_DEVICE(0x103d, 0x0100) }, ++{ USB_DEVICE(0x103d, 0x0101) }, ++ + /* Novation EMS devices */ + { + USB_DEVICE_VENDOR_SPEC(0x1235, 0x0001), +-- +2.43.0 + diff --git a/queue-5.10/arm64-add-neoverse-v2-part.patch b/queue-5.10/arm64-add-neoverse-v2-part.patch new file mode 100644 index 00000000000..cba0d83a393 --- /dev/null +++ b/queue-5.10/arm64-add-neoverse-v2-part.patch @@ -0,0 +1,45 @@ +From 05ad5b494fe379743aa3983c37f74ac3fae4910a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:28 +0100 +Subject: arm64: Add Neoverse-V2 part + +From: Besar Wicaksono + +[ Upstream commit f4d9d9dcc70b96b5e5d7801bd5fbf8491b07b13d ] + +Add the part number and MIDR for Neoverse-V2 + +Signed-off-by: Besar Wicaksono +Reviewed-by: James Clark +Link: https://lore.kernel.org/r/20240109192310.16234-2-bwicaksono@nvidia.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index c2a1ccd5fd468..b772159a84b9c 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -84,6 +84,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_NEOVERSE_V2 0xD4F + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -136,6 +137,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.10/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch b/queue-5.10/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch new file mode 100644 index 00000000000..2259e845f71 --- /dev/null +++ b/queue-5.10/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch @@ -0,0 +1,99 @@ +From 77a6af20a48028a162516a5acf41c45a26d8050f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:27 +0100 +Subject: arm64: cpufeature: Force HWCAP to be based on the sysreg visible to + user-space + +From: James Morse + +[ Upstream commit 237405ebef580a7352a52129b2465c117145eafa ] + +arm64 advertises hardware features to user-space via HWCAPs, and by +emulating access to the CPUs id registers. The cpufeature code has a +sanitised system-wide view of an id register, and a sanitised user-space +view of an id register, where some features use their 'safe' value +instead of the hardware value. + +It is currently possible for a HWCAP to be advertised where the user-space +view of the id register does not show the feature as supported. +Erratum workaround need to remove both the HWCAP, and the feature from +the user-space view of the id register. This involves duplicating the +code, and spreading it over cpufeature.c and cpu_errata.c. + +Make the HWCAP code use the user-space view of id registers. This ensures +the values never diverge, and allows erratum workaround to remove HWCAP +by modifying the user-space view of the id register. + +Signed-off-by: James Morse +Reviewed-by: Suzuki K Poulose +Link: https://lore.kernel.org/r/20220909165938.3931307-2-james.morse@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fixup lack of 'width' parameter ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/cpufeature.c | 36 +++++++++++++++++++++++++++------- + 1 file changed, 29 insertions(+), 7 deletions(-) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 1f0a2deafd643..11a42fcf94bfc 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1196,17 +1196,39 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) + return val >= entry->min_field_value; + } + +-static bool +-has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++static u64 ++read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) + { +- u64 val; +- + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) +- val = read_sanitised_ftr_reg(entry->sys_reg); ++ return read_sanitised_ftr_reg(entry->sys_reg); + else +- val = __read_sysreg_by_encoding(entry->sys_reg); ++ return __read_sysreg_by_encoding(entry->sys_reg); ++} ++ ++static bool ++has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++{ ++ int mask; ++ struct arm64_ftr_reg *regp; ++ u64 val = read_scoped_sysreg(entry, scope); ++ ++ regp = get_arm64_ftr_reg(entry->sys_reg); ++ if (!regp) ++ return false; ++ ++ mask = cpuid_feature_extract_unsigned_field(regp->user_mask, ++ entry->field_pos); ++ if (!mask) ++ return false; ++ ++ return feature_matches(val, entry); ++} + ++static bool ++has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++{ ++ u64 val = read_scoped_sysreg(entry, scope); + return feature_matches(val, entry); + } + +@@ -2172,7 +2194,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { + }; + + #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ +- .matches = has_cpuid_feature, \ ++ .matches = has_user_cpuid_feature, \ + .sys_reg = reg, \ + .field_pos = field, \ + .sign = s, \ +-- +2.43.0 + diff --git a/queue-5.10/arm64-cputype-add-cortex-a720-definitions.patch b/queue-5.10/arm64-cputype-add-cortex-a720-definitions.patch new file mode 100644 index 00000000000..80583c4c638 --- /dev/null +++ b/queue-5.10/arm64-cputype-add-cortex-a720-definitions.patch @@ -0,0 +1,52 @@ +From b33837eef36793a3a5f8b43d711c1138dc900630 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:33 +0100 +Subject: arm64: cputype: Add Cortex-A720 definitions + +From: Mark Rutland + +[ Upstream commit add332c40328cf06fe35e4b3cde8ec315c4629e5 ] + +Add cputype definitions for Cortex-A720. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-186 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-A720 TRM, which can be found at: + + https://developer.arm.com/documentation/102530/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index e8ceddaba7a06..4f08438344e2a 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -86,6 +86,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + +@@ -142,6 +143,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +-- +2.43.0 + diff --git a/queue-5.10/arm64-cputype-add-cortex-a725-definitions.patch b/queue-5.10/arm64-cputype-add-cortex-a725-definitions.patch new file mode 100644 index 00000000000..61b889cf48c --- /dev/null +++ b/queue-5.10/arm64-cputype-add-cortex-a725-definitions.patch @@ -0,0 +1,54 @@ +From afdfa875f85b6ded82bf07490006be92fbbe1c80 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:38 +0100 +Subject: arm64: cputype: Add Cortex-A725 definitions + +From: Mark Rutland + +[ Upstream commit 9ef54a384526911095db465e77acc1cb5266b32c ] + +Add cputype definitions for Cortex-A725. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-A725 TRM: + + https://developer.arm.com/documentation/107652/0001/ + +... in table A-247 ("MIDR_EL1 bit descriptions"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 8dccfd2052691..91890e9fcb6c8 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -91,6 +91,7 @@ + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + #define ARM_CPU_PART_CORTEX_X925 0xD85 ++#define ARM_CPU_PART_CORTEX_A725 0xD87 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -150,6 +151,7 @@ + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) ++#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.10/arm64-cputype-add-cortex-x1c-definitions.patch b/queue-5.10/arm64-cputype-add-cortex-x1c-definitions.patch new file mode 100644 index 00000000000..683c25d2445 --- /dev/null +++ b/queue-5.10/arm64-cputype-add-cortex-x1c-definitions.patch @@ -0,0 +1,54 @@ +From 6495b02f74de2fcebe78e4a79175ee22529e01ef Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:37 +0100 +Subject: arm64: cputype: Add Cortex-X1C definitions + +From: Mark Rutland + +[ Upstream commit 58d245e03c324d083a0ec3b9ab8ebd46ec9848d7 ] + +Add cputype definitions for Cortex-X1C. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-X1C TRM: + + https://developer.arm.com/documentation/101968/0002/ + +... in section B2.107 ("MIDR_EL1, Main ID Register, EL1"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 35162c15ed6c6..8dccfd2052691 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -84,6 +84,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X1C 0xD4C + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_A720 0xD81 +@@ -142,6 +143,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) +-- +2.43.0 + diff --git a/queue-5.10/arm64-cputype-add-cortex-x3-definitions.patch b/queue-5.10/arm64-cputype-add-cortex-x3-definitions.patch new file mode 100644 index 00000000000..3e7519964c2 --- /dev/null +++ b/queue-5.10/arm64-cputype-add-cortex-x3-definitions.patch @@ -0,0 +1,52 @@ +From b407f88e7688542299e02c9e74e098b63e074f85 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:32 +0100 +Subject: arm64: cputype: Add Cortex-X3 definitions + +From: Mark Rutland + +[ Upstream commit be5a6f238700f38b534456608588723fba96c5ab ] + +Add cputype definitions for Cortex-X3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-263 ("MIDR_EL1 bit descriptions") +in issue 07 of the Cortex-X3 TRM, which can be found at: + + https://developer.arm.com/documentation/101593/0102/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index b2887995e575e..e8ceddaba7a06 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -84,6 +84,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 +@@ -139,6 +140,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) +-- +2.43.0 + diff --git a/queue-5.10/arm64-cputype-add-cortex-x4-definitions.patch b/queue-5.10/arm64-cputype-add-cortex-x4-definitions.patch new file mode 100644 index 00000000000..3187d3f5897 --- /dev/null +++ b/queue-5.10/arm64-cputype-add-cortex-x4-definitions.patch @@ -0,0 +1,53 @@ +From 7b596429336661d61fbba75a1d471616000cb6b2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:29 +0100 +Subject: arm64: cputype: Add Cortex-X4 definitions + +From: Mark Rutland + +[ Upstream commit 02a0a04676fa7796d9cbc9eb5ca120aaa194d2dd ] + +Add cputype definitions for Cortex-X4. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-X4 TRM, which can be found at: + + https://developer.arm.com/documentation/102484/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-3-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflict (dealt with upstream via a later merge) ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index b772159a84b9c..a6d1276751dcc 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -85,6 +85,7 @@ + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_X4 0xD82 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -138,6 +139,7 @@ + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.10/arm64-cputype-add-cortex-x925-definitions.patch b/queue-5.10/arm64-cputype-add-cortex-x925-definitions.patch new file mode 100644 index 00000000000..87e1d909764 --- /dev/null +++ b/queue-5.10/arm64-cputype-add-cortex-x925-definitions.patch @@ -0,0 +1,52 @@ +From 73c323166ec44252a4a718ab9fa4c2a0c9c2e5e8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:34 +0100 +Subject: arm64: cputype: Add Cortex-X925 definitions + +From: Mark Rutland + +[ Upstream commit fd2ff5f0b320f418288e7a1f919f648fbc8a0dfc ] + +Add cputype definitions for Cortex-X925. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-285 ("MIDR_EL1 bit descriptions") +in issue 0001-05 of the Cortex-X925 TRM, which can be found at: + + https://developer.arm.com/documentation/102807/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 4f08438344e2a..35162c15ed6c6 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -89,6 +89,7 @@ + #define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 ++#define ARM_CPU_PART_CORTEX_X925 0xD85 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -146,6 +147,7 @@ + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) ++#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.10/arm64-cputype-add-neoverse-v3-definitions.patch b/queue-5.10/arm64-cputype-add-neoverse-v3-definitions.patch new file mode 100644 index 00000000000..b1ef238490b --- /dev/null +++ b/queue-5.10/arm64-cputype-add-neoverse-v3-definitions.patch @@ -0,0 +1,53 @@ +From bb8d11f73cbdc9bf7b0eb3c5b4df35a7a79ae7b4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:30 +0100 +Subject: arm64: cputype: Add Neoverse-V3 definitions + +From: Mark Rutland + +[ Upstream commit 0ce85db6c2141b7ffb95709d76fc55a27ff3cdc1 ] + +Add cputype definitions for Neoverse-V3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0001-04 of the Neoverse-V3 TRM, which can be found at: + + https://developer.arm.com/documentation/107734/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-4-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index a6d1276751dcc..b2887995e575e 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -86,6 +86,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 ++#define ARM_CPU_PART_NEOVERSE_V3 0xD84 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -140,6 +141,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) ++#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.10/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch b/queue-5.10/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch new file mode 100644 index 00000000000..4f118860c05 --- /dev/null +++ b/queue-5.10/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch @@ -0,0 +1,225 @@ +From c4b8c28899c34e1a8754bd039b26503d073984f2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:31 +0100 +Subject: arm64: errata: Add workaround for Arm errata 3194386 and 3312417 + +From: Mark Rutland + +[ Upstream commit 7187bb7d0b5c7dfa18ca82e9e5c75e13861b1d88 ] + +Cortex-X4 and Neoverse-V3 suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. This is described in their Software Developer Errata Notice (SDEN) +documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +To workaround these errata, it is necessary to place a speculation +barrier (SB) after MSR to the SSBS special-purpose register. This patch +adds the requisite SB after writes to SSBS within the kernel, and hides +the presence of SSBS from EL0 such that userspace software which cares +about SSBS will manipulate this via prctl(PR_GET_SPECULATION_CTRL, ...). + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-5-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflicts & renames, drop unneeded cpucaps.h, fold in user_feature_fixup() ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 4 +++ + arch/arm64/Kconfig | 41 ++++++++++++++++++++++++++ + arch/arm64/include/asm/cpucaps.h | 3 +- + arch/arm64/kernel/cpu_errata.c | 19 ++++++++++++ + arch/arm64/kernel/cpufeature.c | 12 ++++++++ + arch/arm64/kernel/proton-pack.c | 12 ++++++++ + 6 files changed, 90 insertions(+), 1 deletion(-) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index 10a26d44ef4a9..0ecb714b2c426 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -98,12 +98,16 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1349291 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ + +----------------+-----------------+-----------------+-----------------------------+ +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 13cf137da999a..0d59e8ab27c88 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -691,6 +691,47 @@ config ARM64_ERRATUM_2457168 + + If unsure, say Y. + ++config ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool ++ ++config ARM64_ERRATUM_3194386 ++ bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Cortex-X4 erratum 3194386. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ ++config ARM64_ERRATUM_3312417 ++ bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h +index d2080a41f6e6f..931c88182fb8b 100644 +--- a/arch/arm64/include/asm/cpucaps.h ++++ b/arch/arm64/include/asm/cpucaps.h +@@ -69,7 +69,8 @@ + #define ARM64_SPECTRE_BHB 59 + #define ARM64_WORKAROUND_2457168 60 + #define ARM64_WORKAROUND_1742098 61 ++#define ARM64_WORKAROUND_SPECULATIVE_SSBS 62 + +-#define ARM64_NCAPS 62 ++#define ARM64_NCAPS 63 + + #endif /* __ASM_CPUCAPS_H */ +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 5d6f19bc628c2..3eabd809aee4a 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -364,6 +364,18 @@ static struct midr_range broken_aarch32_aes[] = { + }; + #endif + ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++static const struct midr_range erratum_spec_ssbs_list[] = { ++#ifdef CONFIG_ARM64_ERRATUM_3194386 ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++#endif ++#ifdef CONFIG_ARM64_ERRATUM_3312417 ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++#endif ++ {} ++}; ++#endif ++ + const struct arm64_cpu_capabilities arm64_errata[] = { + #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE + { +@@ -570,6 +582,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + CAP_MIDR_RANGE_LIST(broken_aarch32_aes), + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + }, ++#endif ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++ { ++ .desc = "ARM errata 3194386, 3312417", ++ .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, ++ ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), ++ }, + #endif + { + } +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 11a42fcf94bfc..dc92fd590f2f9 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1753,6 +1753,17 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) + } + #endif /* CONFIG_ARM64_MTE */ + ++static void user_feature_fixup(void) ++{ ++ if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { ++ struct arm64_ftr_reg *regp; ++ ++ regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); ++ if (regp) ++ regp->user_mask &= ~GENMASK(7, 4); /* SSBS */ ++ } ++} ++ + static void elf_hwcap_fixup(void) + { + #ifdef CONFIG_ARM64_ERRATUM_1742098 +@@ -2764,6 +2775,7 @@ void __init setup_cpu_features(void) + u32 cwg; + + setup_system_capabilities(); ++ user_feature_fixup(); + setup_elf_hwcaps(arm64_elf_hwcaps); + + if (system_supports_32bit_el0()) { +diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c +index 9c0e9d9eed6e2..b40310e0bdb90 100644 +--- a/arch/arm64/kernel/proton-pack.c ++++ b/arch/arm64/kernel/proton-pack.c +@@ -574,6 +574,18 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void) + + /* SCTLR_EL1.DSSBS was initialised to 0 during boot */ + asm volatile(SET_PSTATE_SSBS(0)); ++ ++ /* ++ * SSBS is self-synchronizing and is intended to affect subsequent ++ * speculative instructions, but some CPUs can speculate with a stale ++ * value of SSBS. ++ * ++ * Mitigate this with an unconditional speculation barrier, as CPUs ++ * could mis-speculate branches and bypass a conditional barrier. ++ */ ++ if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ spec_bar(); ++ + return SPECTRE_MITIGATED; + } + +-- +2.43.0 + diff --git a/queue-5.10/arm64-errata-expand-speculative-ssbs-workaround-agai.patch b/queue-5.10/arm64-errata-expand-speculative-ssbs-workaround-agai.patch new file mode 100644 index 00000000000..4c3c39c3228 --- /dev/null +++ b/queue-5.10/arm64-errata-expand-speculative-ssbs-workaround-agai.patch @@ -0,0 +1,213 @@ +From 1686fb96c88a1f5fafbe3e3bc81c3200e019e2b7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:39 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround (again) + +From: Mark Rutland + +[ Upstream commit b0672bbe133ebb6f7be21fce1d742d52f25bcdc7 ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for a number of CPUs in commits: + +* 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") +* 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") + +Since then, similar errata have been published for a number of other Arm +Ltd CPUs, for which the same mitigation is sufficient. This is described +in their respective Software Developer Errata Notice (SDEN) documents: + +* Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885749/3100/ + +* Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 + https://developer.arm.com/documentation/SDEN-1152370/1900/ + +* Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401784/2100/ + +* Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707916/1600/ + +* Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 + https://developer.arm.com/documentation/SDEN-2004089/1000/ + +* Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 + https://developer.arm.com/documentation/SDEN-2832921/0500/ + +* Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401782/2100/ + +* Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707914/1600/ + +* Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885747/3200/ + +* Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 + https://developer.arm.com/documentation/SDEN-1401781/1900/ + +Note that due to the manner in which Arm develops IP and tracks errata, +some CPUs share a common erratum number and some CPUs have multiple +erratum numbers for the same HW issue. + +On parts without SB, it is necessary to use ISB for the workaround. The +spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" +sequence in this case, which is sufficient on all affected parts. + +Enable the existing mitigation by adding the relevant MIDRs to +erratum_spec_ssbs_list. The list is sorted alphanumerically (involving +moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and +potentially extend again in future. The Kconfig text is also updated to +clarify the set of affected parts and the mitigation. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Acked-by: Will Deacon +Link: https://lore.kernel.org/r/20240801101803.1982459-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts in silicon-errata.rst ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 18 ++++++++++++++++++ + arch/arm64/Kconfig | 22 ++++++++++++++++------ + arch/arm64/kernel/cpu_errata.c | 11 ++++++++++- + 3 files changed, 44 insertions(+), 7 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index 748f9cc5877bc..14eef7e93614b 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -94,14 +94,28 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | +@@ -116,8 +130,12 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 3662cb8aa44d5..9fdf8b0364288 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -692,18 +692,28 @@ config ARM64_ERRATUM_2457168 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A76 erratum 3324349 ++ * ARM Cortex-A77 erratum 3324348 ++ * ARM Cortex-A78 erratum 3324344 ++ * ARM Cortex-A78C erratum 3324346 ++ * ARM Cortex-A78C erratum 3324347 + * ARM Cortex-A710 erratam 3324338 + * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-A725 erratum 3456106 ++ * ARM Cortex-X1 erratum 3324344 ++ * ARM Cortex-X1C erratum 3324346 + * ARM Cortex-X2 erratum 3324338 + * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 + * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse-N1 erratum 3324349 + * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse-V1 erratum 3324341 + * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + +@@ -711,11 +721,11 @@ config ARM64_ERRATUM_3194386 + subsequent speculative instructions, which may permit unexepected + speculative store bypassing. + +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. ++ Work around this problem by placing a Speculation Barrier (SB) or ++ Instruction Synchronization Barrier (ISB) after kernel changes to ++ SSBS. The presence of the SSBS special-purpose register is hidden ++ from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace ++ will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. + + If unsure, say Y. + +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 000c61ee5a1e1..6e63dc8f0e8c6 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -366,15 +366,24 @@ static struct midr_range broken_aarch32_aes[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), +- MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), + {} + }; + #endif +-- +2.43.0 + diff --git a/queue-5.10/arm64-errata-expand-speculative-ssbs-workaround.patch b/queue-5.10/arm64-errata-expand-speculative-ssbs-workaround.patch new file mode 100644 index 00000000000..812a3f62385 --- /dev/null +++ b/queue-5.10/arm64-errata-expand-speculative-ssbs-workaround.patch @@ -0,0 +1,166 @@ +From 4114794976779f20e62a1b2276cf43f564641b65 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:36 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround + +From: Mark Rutland + +[ Upstream commit 75b3c43eab594bfbd8184ec8ee1a6b820950819a ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for Cortex-X4 and Neoverse-V3, in commit: + + 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") + +... as per their Software Developer Errata Notice (SDEN) documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +Since then, similar errata have been published for a number of other Arm Ltd +CPUs, for which the mitigation is the same. This is described in their +respective SDEN documents: + +* Cortex-A710 SDEN v19.0, errataum 3324338 + https://developer.arm.com/documentation/SDEN-1775101/1900/?lang=en + +* Cortex-A720 SDEN v11.0, erratum 3456091 + https://developer.arm.com/documentation/SDEN-2439421/1100/?lang=en + +* Cortex-X2 SDEN v19.0, erratum 3324338 + https://developer.arm.com/documentation/SDEN-1775100/1900/?lang=en + +* Cortex-X3 SDEN v14.0, erratum 3324335 + https://developer.arm.com/documentation/SDEN-2055130/1400/?lang=en + +* Cortex-X925 SDEN v8.0, erratum 3324334 + https://developer.arm.com/documentation/109108/800/?lang=en + +* Neoverse-N2 SDEN v17.0, erratum 3324339 + https://developer.arm.com/documentation/SDEN-1982442/1700/?lang=en + +* Neoverse-V2 SDEN v9.0, erratum 3324336 + https://developer.arm.com/documentation/SDEN-2332927/900/?lang=en + +Note that due to shared design lineage, some CPUs share the same erratum +number. + +Add these to the existing mitigation under CONFIG_ARM64_ERRATUM_3194386. +As listing all of the erratum IDs in the runtime description would be +unwieldy, this is reduced to: + + "SSBS not fully self-synchronizing" + +... matching the description of the errata in all of the SDENs. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-6-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts and renames ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 14 ++++++++++++++ + arch/arm64/Kconfig | 9 ++++++++- + arch/arm64/kernel/cpu_errata.c | 9 ++++++++- + 3 files changed, 30 insertions(+), 2 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index 2f50eb0fce34f..748f9cc5877bc 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -98,14 +98,28 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1349291 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 4ed94e8d84c71..3662cb8aa44d5 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -692,12 +692,19 @@ config ARM64_ERRATUM_2457168 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A710 erratam 3324338 ++ * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-X2 erratum 3324338 ++ * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 ++ * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 4dc465d285d58..000c61ee5a1e1 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -366,8 +366,15 @@ static struct midr_range broken_aarch32_aes[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), + {} + }; + #endif +@@ -581,7 +588,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + #endif + #ifdef CONFIG_ARM64_ERRATUM_3194386 + { +- .desc = "ARM errata 3194386, 3312417", ++ .desc = "SSBS not fully self-synchronizing", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, + ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), + }, +-- +2.43.0 + diff --git a/queue-5.10/arm64-errata-unify-speculative-ssbs-errata-logic.patch b/queue-5.10/arm64-errata-unify-speculative-ssbs-errata-logic.patch new file mode 100644 index 00000000000..8eb49e0795d --- /dev/null +++ b/queue-5.10/arm64-errata-unify-speculative-ssbs-errata-logic.patch @@ -0,0 +1,141 @@ +From 448f7209dace802ccb560a26ba510feddde64918 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:17:35 +0100 +Subject: arm64: errata: Unify speculative SSBS errata logic + +From: Mark Rutland + +[ Upstream commit ec768766608092087dfb5c1fc45a16a6f524dee2 ] + +Cortex-X4 erratum 3194386 and Neoverse-V3 erratum 3312417 are identical, +with duplicate Kconfig text and some unsightly ifdeffery. While we try +to share code behind CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS, having +separate options results in a fair amount of boilerplate code, and this +will only get worse as we expand the set of affected CPUs. + +To reduce this boilerplate, unify the two behind a common Kconfig +option. This removes the duplicate text and Kconfig logic, and removes +the need for the intermediate ARM64_WORKAROUND_SPECULATIVE_SSBS option. +The set of affected CPUs is described as a list so that this can easily +be extended. + +I've used ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID) as +the common option, matching the way we use ARM64_ERRATUM_1319367 to +cover Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-5-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts & renames, drop unneeded cpucaps.h ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 2 +- + arch/arm64/Kconfig | 28 ++++---------------------- + arch/arm64/kernel/cpu_errata.c | 8 ++------ + arch/arm64/kernel/proton-pack.c | 2 +- + 4 files changed, 8 insertions(+), 32 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index 0ecb714b2c426..2f50eb0fce34f 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -106,7 +106,7 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | + +----------------+-----------------+-----------------+-----------------------------+ +-| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 0d59e8ab27c88..4ed94e8d84c71 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -691,34 +691,14 @@ config ARM64_ERRATUM_2457168 + + If unsure, say Y. + +-config ARM64_WORKAROUND_SPECULATIVE_SSBS +- bool +- + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help +- This option adds the workaround for ARM Cortex-X4 erratum 3194386. +- +- On affected cores "MSR SSBS, #0" instructions may not affect +- subsequent speculative instructions, which may permit unexepected +- speculative store bypassing. +- +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. ++ This option adds the workaround for the following errata: + +- If unsure, say Y. +- +-config ARM64_ERRATUM_3312417 +- bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS +- default y +- help +- This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ * ARM Cortex-X4 erratum 3194386 ++ * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect + subsequent speculative instructions, which may permit unexepected +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 3eabd809aee4a..4dc465d285d58 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -364,14 +364,10 @@ static struct midr_range broken_aarch32_aes[] = { + }; + #endif + +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS +-static const struct midr_range erratum_spec_ssbs_list[] = { + #ifdef CONFIG_ARM64_ERRATUM_3194386 ++static const struct midr_range erratum_spec_ssbs_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), +-#endif +-#ifdef CONFIG_ARM64_ERRATUM_3312417 + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), +-#endif + {} + }; + #endif +@@ -583,7 +579,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + }, + #endif +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++#ifdef CONFIG_ARM64_ERRATUM_3194386 + { + .desc = "ARM errata 3194386, 3312417", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, +diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c +index b40310e0bdb90..90337910c3f53 100644 +--- a/arch/arm64/kernel/proton-pack.c ++++ b/arch/arm64/kernel/proton-pack.c +@@ -583,7 +583,7 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void) + * Mitigate this with an unconditional speculation barrier, as CPUs + * could mis-speculate branches and bypass a conditional barrier. + */ +- if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386)) + spec_bar(); + + return SPECTRE_MITIGATED; +-- +2.43.0 + diff --git a/queue-5.10/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch b/queue-5.10/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch new file mode 100644 index 00000000000..48b87ca5df6 --- /dev/null +++ b/queue-5.10/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch @@ -0,0 +1,44 @@ +From b69d67ea8429c57c61644537676226f01e1f1ecc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Jul 2024 16:10:44 +0200 +Subject: ASoC: codecs: wsa881x: Correct Soundwire ports mask + +From: Krzysztof Kozlowski + +[ Upstream commit eb11c3bb64ad0a05aeacdb01039863aa2aa3614b ] + +Device has up to WSA881X_MAX_SWR_PORTS number of ports and the array +assigned to prop.sink_dpn_prop has 0..WSA881X_MAX_SWR_PORTS-1 elements. +On the other hand, GENMASK(high, low) creates an inclusive mask between +, so we need the mask from 0 up to WSA881X_MAX_SWR_PORTS-1. + +Theoretically, too wide mask could cause an out of bounds read in +sdw_get_slave_dpn_prop() in stream.c, however only in the case of buggy +driver, e.g. adding incorrect number of ports via +sdw_stream_add_slave(). + +Fixes: a0aab9e1404a ("ASoC: codecs: add wsa881x amplifier support") +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-4-d4d7a8b56f05@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wsa881x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c +index 9f66f6dc2c67f..77012979e1319 100644 +--- a/sound/soc/codecs/wsa881x.c ++++ b/sound/soc/codecs/wsa881x.c +@@ -1120,7 +1120,7 @@ static int wsa881x_probe(struct sdw_slave *pdev, + wsa881x->sconfig.frame_rate = 48000; + wsa881x->sconfig.direction = SDW_DATA_DIR_RX; + wsa881x->sconfig.type = SDW_STREAM_PDM; +- pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0); ++ pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS - 1, 0); + pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; + pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; + gpiod_direction_output(wsa881x->sd_n, 1); +-- +2.43.0 + diff --git a/queue-5.10/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch b/queue-5.10/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch new file mode 100644 index 00000000000..734b2cb1f47 --- /dev/null +++ b/queue-5.10/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch @@ -0,0 +1,39 @@ +From ba09344a16e00584e79d688dc4654ec6ecccb92d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Aug 2024 14:01:21 +0900 +Subject: bpf: kprobe: remove unused declaring of bpf_kprobe_override + +From: Menglong Dong + +[ Upstream commit 0e8b53979ac86eddb3fd76264025a70071a25574 ] + +After the commit 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction +pointer with original one"), "bpf_kprobe_override" is not used anywhere +anymore, and we can remove it now. + +Link: https://lore.kernel.org/all/20240710085939.11520-1-dongml2@chinatelecom.cn/ + +Fixes: 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction pointer with original one") +Signed-off-by: Menglong Dong +Acked-by: Jiri Olsa +Signed-off-by: Masami Hiramatsu (Google) +Signed-off-by: Sasha Levin +--- + include/linux/trace_events.h | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h +index dbf0993153d35..64af1e11ea13d 100644 +--- a/include/linux/trace_events.h ++++ b/include/linux/trace_events.h +@@ -729,7 +729,6 @@ do { \ + struct perf_event; + + DECLARE_PER_CPU(struct pt_regs, perf_trace_regs); +-DECLARE_PER_CPU(int, bpf_kprobe_override); + + extern int perf_trace_init(struct perf_event *event); + extern void perf_trace_destroy(struct perf_event *event); +-- +2.43.0 + diff --git a/queue-5.10/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch b/queue-5.10/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch new file mode 100644 index 00000000000..6ca365eb8e4 --- /dev/null +++ b/queue-5.10/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch @@ -0,0 +1,39 @@ +From 7e934f6bbcb032740caa860bba3700f1d3462511 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 3 Jun 2023 23:03:11 +0800 +Subject: ext4: fix wrong unit use in ext4_mb_find_by_goal + +From: Kemeng Shi + +[ Upstream commit 99c515e3a860576ba90c11acbc1d6488dfca6463 ] + +We need start in block unit while fe_start is in cluster unit. Use +ext4_grp_offs_to_block helper to convert fe_start to get start in +block unit. + +Signed-off-by: Kemeng Shi +Reviewed-by: Ojaswin Mujoo +Link: https://lore.kernel.org/r/20230603150327.3596033-4-shikemeng@huaweicloud.com +Signed-off-by: Theodore Ts'o +Signed-off-by: Sasha Levin +--- + fs/ext4/mballoc.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c +index 87378d08a414b..bc5db22df9fe7 100644 +--- a/fs/ext4/mballoc.c ++++ b/fs/ext4/mballoc.c +@@ -1927,8 +1927,7 @@ int ext4_mb_find_by_goal(struct ext4_allocation_context *ac, + if (max >= ac->ac_g_ex.fe_len && ac->ac_g_ex.fe_len == sbi->s_stripe) { + ext4_fsblk_t start; + +- start = ext4_group_first_block_no(ac->ac_sb, e4b->bd_group) + +- ex.fe_start; ++ start = ext4_grp_offs_to_block(ac->ac_sb, &ex); + /* use do_div to get remainder (would be 64-bit modulo) */ + if (do_div(start, sbi->s_stripe) == 0) { + ac->ac_found++; +-- +2.43.0 + diff --git a/queue-5.10/i2c-smbus-improve-handling-of-stuck-alerts.patch b/queue-5.10/i2c-smbus-improve-handling-of-stuck-alerts.patch new file mode 100644 index 00000000000..3666bdb795a --- /dev/null +++ b/queue-5.10/i2c-smbus-improve-handling-of-stuck-alerts.patch @@ -0,0 +1,122 @@ +From b66486c8806eed349b903a5cbbe3b52e672c2d97 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 10 Jan 2022 09:28:56 -0800 +Subject: i2c: smbus: Improve handling of stuck alerts + +From: Guenter Roeck + +[ Upstream commit 37c526f00bc1c4f847fc800085f8f009d2e11be6 ] + +The following messages were observed while testing alert functionality +on systems with multiple I2C devices on a single bus if alert was active +on more than one chip. + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! + +and: + +smbus_alert 3-000c: SMBALERT# from dev 0x28, flag 0 + +Once it starts, this message repeats forever at high rate. There is no +device at any of the reported addresses. + +Analysis shows that this is seen if multiple devices have the alert pin +active. Apparently some devices do not support SMBus arbitration correctly. +They keep sending address bits after detecting an address collision and +handle the collision not at all or too late. +Specifically, address 0x0c is seen with ADT7461A at address 0x4c and +ADM1021 at address 0x18 if alert is active on both chips. Address 0x28 is +seen with ADT7483 at address 0x2a and ADT7461 at address 0x4c if alert is +active on both chips. + +Once the system is in bad state (alert is set by more than one chip), +it often only recovers by power cycling. + +To reduce the impact of this problem, abort the endless loop in +smbus_alert() if the same address is read more than once and not +handled by a driver. + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: it also fixed an interrupt storm in one of my experiments] +Tested-by: Wolfram Sang +[wsa: rebased, moved a comment as well, improved the 'invalid' value] +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 32 +++++++++++++++++++++++++------- + 1 file changed, 25 insertions(+), 7 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index d3d06e3b4f3b3..dcbc4b29aa729 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -34,6 +34,7 @@ static int smbus_do_alert(struct device *dev, void *addrp) + struct i2c_client *client = i2c_verify_client(dev); + struct alert_data *data = addrp; + struct i2c_driver *driver; ++ int ret; + + if (!client || client->addr != data->addr) + return 0; +@@ -47,16 +48,21 @@ static int smbus_do_alert(struct device *dev, void *addrp) + device_lock(dev); + if (client->dev.driver) { + driver = to_i2c_driver(client->dev.driver); +- if (driver->alert) ++ if (driver->alert) { ++ /* Stop iterating after we find the device */ + driver->alert(client, data->type, data->data); +- else ++ ret = -EBUSY; ++ } else { + dev_warn(&client->dev, "no driver alert()!\n"); +- } else ++ ret = -EOPNOTSUPP; ++ } ++ } else { + dev_dbg(&client->dev, "alert with no driver\n"); ++ ret = -ENODEV; ++ } + device_unlock(dev); + +- /* Stop iterating after we find the device */ +- return -EBUSY; ++ return ret; + } + + /* +@@ -67,6 +73,7 @@ static irqreturn_t smbus_alert(int irq, void *d) + { + struct i2c_smbus_alert *alert = d; + struct i2c_client *ara; ++ unsigned short prev_addr = I2C_CLIENT_END; /* Not a valid address */ + + ara = alert->ara; + +@@ -94,8 +101,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + data.addr, data.data); + + /* Notify driver for the device which issued the alert */ +- device_for_each_child(&ara->adapter->dev, &data, +- smbus_do_alert); ++ status = device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert); ++ /* ++ * If we read the same address more than once, and the alert ++ * was not handled by a driver, it won't do any good to repeat ++ * the loop because it will never terminate. ++ * Bail out in this case. ++ * Note: This assumes that a driver with alert handler handles ++ * the alert properly and clears it if necessary. ++ */ ++ if (data.addr == prev_addr && status != -EBUSY) ++ break; ++ prev_addr = data.addr; + } + + return IRQ_HANDLED; +-- +2.43.0 + diff --git a/queue-5.10/i2c-smbus-send-alert-notifications-to-all-devices-if.patch b/queue-5.10/i2c-smbus-send-alert-notifications-to-all-devices-if.patch new file mode 100644 index 00000000000..8553189abbb --- /dev/null +++ b/queue-5.10/i2c-smbus-send-alert-notifications-to-all-devices-if.patch @@ -0,0 +1,106 @@ +From ce53f67846849de953ce7b3d43cad1050732fbc4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Jul 2024 07:19:41 -0700 +Subject: i2c: smbus: Send alert notifications to all devices if source not + found + +From: Guenter Roeck + +[ Upstream commit f6c29f710c1ff2590109f83be3e212b86c01e0f3 ] + +If a SMBus alert is received and the originating device is not found, +the reason may be that the address reported on the SMBus alert address +is corrupted, for example because multiple devices asserted alert and +do not correctly implement SMBus arbitration. + +If this happens, call alert handlers on all devices connected to the +given I2C bus, in the hope that this cleans up the situation. + +This change reliably fixed the problem on a system with multiple devices +on a single bus. Example log where the device on address 0x18 (ADM1021) +and on address 0x4c (ADT7461A) both had the alert line asserted: + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +lm90 3-0018: temp1 out of range, please check! +lm90 3-0018: Disabling ALERT# +lm90 3-0029: Everything OK +lm90 3-002a: Everything OK +lm90 3-004c: temp1 out of range, please check! +lm90 3-004c: temp2 out of range, please check! +lm90 3-004c: Disabling ALERT# + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: fixed a typo in the commit message] +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 38 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 35 insertions(+), 3 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index dcbc4b29aa729..44582cf29e162 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -65,6 +65,32 @@ static int smbus_do_alert(struct device *dev, void *addrp) + return ret; + } + ++/* Same as above, but call back all drivers with alert handler */ ++ ++static int smbus_do_alert_force(struct device *dev, void *addrp) ++{ ++ struct i2c_client *client = i2c_verify_client(dev); ++ struct alert_data *data = addrp; ++ struct i2c_driver *driver; ++ ++ if (!client || (client->flags & I2C_CLIENT_TEN)) ++ return 0; ++ ++ /* ++ * Drivers should either disable alerts, or provide at least ++ * a minimal handler. Lock so the driver won't change. ++ */ ++ device_lock(dev); ++ if (client->dev.driver) { ++ driver = to_i2c_driver(client->dev.driver); ++ if (driver->alert) ++ driver->alert(client, data->type, data->data); ++ } ++ device_unlock(dev); ++ ++ return 0; ++} ++ + /* + * The alert IRQ handler needs to hand work off to a task which can issue + * SMBus calls, because those sleeping calls can't be made in IRQ context. +@@ -106,13 +132,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + /* + * If we read the same address more than once, and the alert + * was not handled by a driver, it won't do any good to repeat +- * the loop because it will never terminate. +- * Bail out in this case. ++ * the loop because it will never terminate. Try again, this ++ * time calling the alert handlers of all devices connected to ++ * the bus, and abort the loop afterwards. If this helps, we ++ * are all set. If it doesn't, there is nothing else we can do, ++ * so we might as well abort the loop. + * Note: This assumes that a driver with alert handler handles + * the alert properly and clears it if necessary. + */ +- if (data.addr == prev_addr && status != -EBUSY) ++ if (data.addr == prev_addr && status != -EBUSY) { ++ device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert_force); + break; ++ } + prev_addr = data.addr; + } + +-- +2.43.0 + diff --git a/queue-5.10/kprobes-fix-to-check-symbol-prefixes-correctly.patch b/queue-5.10/kprobes-fix-to-check-symbol-prefixes-correctly.patch new file mode 100644 index 00000000000..bbe97150d59 --- /dev/null +++ b/queue-5.10/kprobes-fix-to-check-symbol-prefixes-correctly.patch @@ -0,0 +1,40 @@ +From 1c86a7835a517503378acb2d71ffc0a2a1030c15 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Aug 2024 22:53:15 +0900 +Subject: kprobes: Fix to check symbol prefixes correctly + +From: Masami Hiramatsu (Google) + +[ Upstream commit 8c8acb8f26cbde665b233dd1b9bbcbb9b86822dc ] + +Since str_has_prefix() takes the prefix as the 2nd argument and the string +as the first, is_cfi_preamble_symbol() always fails to check the prefix. +Fix the function parameter order so that it correctly check the prefix. + +Link: https://lore.kernel.org/all/172260679559.362040.7360872132937227206.stgit@devnote2/ + +Fixes: de02f2ac5d8c ("kprobes: Prohibit probing on CFI preamble symbol") +Signed-off-by: Masami Hiramatsu (Google) +Signed-off-by: Sasha Levin +--- + kernel/kprobes.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/kernel/kprobes.c b/kernel/kprobes.c +index dba6541c0fc3c..c8e62458d323f 100644 +--- a/kernel/kprobes.c ++++ b/kernel/kprobes.c +@@ -1632,8 +1632,8 @@ static bool is_cfi_preamble_symbol(unsigned long addr) + if (lookup_symbol_name(addr, symbuf)) + return false; + +- return str_has_prefix("__cfi_", symbuf) || +- str_has_prefix("__pfx_", symbuf); ++ return str_has_prefix(symbuf, "__cfi_") || ++ str_has_prefix(symbuf, "__pfx_"); + } + + static int check_kprobe_address_safe(struct kprobe *p, +-- +2.43.0 + diff --git a/queue-5.10/series b/queue-5.10/series index 50c577ca4e0..9780833d7fc 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -288,3 +288,24 @@ jbd2-avoid-memleak-in-jbd2_journal_write_metadata_bu.patch s390-sclp-prevent-release-of-buffer-in-i-o.patch sunrpc-fix-a-race-to-wake-a-sync-task.patch sched-cputime-fix-mul_u64_u64_div_u64-precision-for-cputime.patch +ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch +arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch +arm64-add-neoverse-v2-part.patch +arm64-cputype-add-cortex-x4-definitions.patch +arm64-cputype-add-neoverse-v3-definitions.patch +arm64-errata-add-workaround-for-arm-errata-3194386-a.patch +arm64-cputype-add-cortex-x3-definitions.patch +arm64-cputype-add-cortex-a720-definitions.patch +arm64-cputype-add-cortex-x925-definitions.patch +arm64-errata-unify-speculative-ssbs-errata-logic.patch +arm64-errata-expand-speculative-ssbs-workaround.patch +arm64-cputype-add-cortex-x1c-definitions.patch +arm64-cputype-add-cortex-a725-definitions.patch +arm64-errata-expand-speculative-ssbs-workaround-agai.patch +i2c-smbus-improve-handling-of-stuck-alerts.patch +asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch +i2c-smbus-send-alert-notifications-to-all-devices-if.patch +bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch +kprobes-fix-to-check-symbol-prefixes-correctly.patch +spi-spi-fsl-lpspi-fix-scldiv-calculation.patch +alsa-usb-audio-re-add-scratchamp-quirk-entries.patch diff --git a/queue-5.10/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch b/queue-5.10/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch new file mode 100644 index 00000000000..36af823f83e --- /dev/null +++ b/queue-5.10/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch @@ -0,0 +1,57 @@ +From 39ad397b52b126fe7e42aacf1858904a5c487cd1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Aug 2024 13:36:11 +0200 +Subject: spi: spi-fsl-lpspi: Fix scldiv calculation + +From: Stefan Wahren + +[ Upstream commit 730bbfaf7d4890bd99e637db7767dc68cfeb24e7 ] + +The effective SPI clock frequency should never exceed speed_hz +otherwise this might result in undefined behavior of the SPI device. + +Currently the scldiv calculation could violate this constraint. +For the example parameters perclk_rate = 24 MHz and speed_hz = 7 MHz, +the function fsl_lpspi_set_bitrate will determine perscale = 0 and +scldiv = 1, which is a effective SPI clock of 8 MHz. + +So fix this by rounding up the quotient of perclk_rate and speed_hz. +While this never change within the loop, we can pull this out. + +Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver") +Signed-off-by: Stefan Wahren +Link: https://patch.msgid.link/20240804113611.83613-1-wahrenst@gmx.net +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index c5ff6e8c45be0..c21d7959dcd23 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -297,7 +297,7 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) + static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + { + struct lpspi_config config = fsl_lpspi->config; +- unsigned int perclk_rate, scldiv; ++ unsigned int perclk_rate, scldiv, div; + u8 prescale; + + perclk_rate = clk_get_rate(fsl_lpspi->clk_per); +@@ -308,8 +308,10 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + return -EINVAL; + } + ++ div = DIV_ROUND_UP(perclk_rate, config.speed_hz); ++ + for (prescale = 0; prescale < 8; prescale++) { +- scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; ++ scldiv = div / (1 << prescale) - 2; + if (scldiv < 256) { + fsl_lpspi->config.prescale = prescale; + break; +-- +2.43.0 +