From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Thu, 24 Jan 2013 19:58:46 +0000 (-0800)
Subject: 3.4-stable patches
X-Git-Tag: v3.0.61~9
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=829cca84fc55f6f03ed8d6863025acd4aad0e482;p=thirdparty%2Fkernel%2Fstable-queue.git

3.4-stable patches

added patches:
	drm-i915-implement-wadisablehizplaneswhenmsaaenabled.patch
---

diff --git a/queue-3.4/drm-i915-implement-wadisablehizplaneswhenmsaaenabled.patch b/queue-3.4/drm-i915-implement-wadisablehizplaneswhenmsaaenabled.patch
new file mode 100644
index 00000000000..b005c3d0255
--- /dev/null
+++ b/queue-3.4/drm-i915-implement-wadisablehizplaneswhenmsaaenabled.patch
@@ -0,0 +1,55 @@
+From 4283908ef7f11a72c3b80dd4cf026f1a86429f82 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Fri, 14 Dec 2012 23:38:28 +0100
+Subject: drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled
+
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 4283908ef7f11a72c3b80dd4cf026f1a86429f82 upstream.
+
+Quoting from Bspec, 3D_CHICKEN1, bit 10
+
+This bit needs to be set always to "1", Project: DevSNB "
+
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Abdallah Chatila <abdallah.chatila@ericsson.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h      |    3 +++
+ drivers/gpu/drm/i915/intel_display.c |    4 ++++
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -27,6 +27,8 @@
+ 
+ #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+ 
++#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
++
+ /*
+  * The Bridge device's PCI config space has information about the
+  * fb aperture size and the amount of pre-reserved memory.
+@@ -433,6 +435,7 @@
+  * the enables for writing to the corresponding low bit.
+  */
+ #define _3D_CHICKEN	0x02084
++#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
+ #define _3D_CHICKEN2	0x0208c
+ /* Disables pipelining of read flushes past the SF-WIZ interface.
+  * Required on all Ironlake steppings according to the B-Spec, but the
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -8592,6 +8592,10 @@ static void gen6_init_clock_gating(struc
+ 		   I915_READ(ILK_DISPLAY_CHICKEN2) |
+ 		   ILK_ELPIN_409_SELECT);
+ 
++	/* WaDisableHiZPlanesWhenMSAAEnabled */
++	I915_WRITE(_3D_CHICKEN,
++		   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
++
+ 	I915_WRITE(WM3_LP_ILK, 0);
+ 	I915_WRITE(WM2_LP_ILK, 0);
+ 	I915_WRITE(WM1_LP_ILK, 0);
diff --git a/queue-3.4/series b/queue-3.4/series
index 267988206e1..526b1e65cbc 100644
--- a/queue-3.4/series
+++ b/queue-3.4/series
@@ -16,3 +16,4 @@ drivers-firmware-dmi_scan.c-check-dmi-version-when-get.patch
 drivers-firmware-dmi_scan.c-fetch-dmi-version-from-smbios-if-it-exists.patch
 ahci-add-identifiers-for-asm106x-devices.patch
 alsa-usb-audio-fix-regression-by-disconnection-race-fix-patch.patch
+drm-i915-implement-wadisablehizplaneswhenmsaaenabled.patch