From: Jamin Lin Date: Wed, 25 Feb 2026 02:12:13 +0000 (+0000) Subject: hw/i3c/aspeed_i3c: Add register RO field masks X-Git-Tag: v11.0.0-rc0~37^2~29 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=84001254ecbcd892fca5d0d529a856a121e36da3;p=thirdparty%2Fqemu.git hw/i3c/aspeed_i3c: Add register RO field masks Adds read-only register masks for the Aspeed I3C controller registers. Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Signed-off-by: Jamin Lin Tested-by: Jithu Joseph Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater --- diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index a2157002888..2700c5f4cde 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -74,6 +74,21 @@ REG32(I3C6_REG1, 0x64) FIELD(I3C6_REG1, SA_EN, 15, 1) FIELD(I3C6_REG1, INST_ID, 16, 4) +static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_NR_REGS] = { + [R_I3C1_REG0] = 0xcc000000, + [R_I3C1_REG1] = 0xfff00000, + [R_I3C2_REG0] = 0xcc000000, + [R_I3C2_REG1] = 0xfff00000, + [R_I3C3_REG0] = 0xcc000000, + [R_I3C3_REG1] = 0xfff00000, + [R_I3C4_REG0] = 0xcc000000, + [R_I3C4_REG1] = 0xfff00000, + [R_I3C5_REG0] = 0xcc000000, + [R_I3C5_REG1] = 0xfff00000, + [R_I3C6_REG0] = 0xcc000000, + [R_I3C6_REG1] = 0xfff00000, +}; + static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) { AspeedI3CState *s = ASPEED_I3C(opaque); @@ -97,6 +112,7 @@ static void aspeed_i3c_write(void *opaque, addr >>= 2; + data &= ~ast2600_i3c_controller_ro[addr]; /* I3C controller register */ switch (addr) { case R_I3C1_REG1: