From: Greg Kroah-Hartman Date: Fri, 8 May 2020 14:26:35 +0000 (+0200) Subject: drop 2 mips patches that broke the build X-Git-Tag: v4.4.223~2 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=84730998ea649594ff8c5574b4f7d226f29f9566;p=thirdparty%2Fkernel%2Fstable-queue.git drop 2 mips patches that broke the build --- diff --git a/queue-4.4/mips-fix-64-bit-htw-configuration.patch b/queue-4.4/mips-fix-64-bit-htw-configuration.patch deleted file mode 100644 index 3b363703922..00000000000 --- a/queue-4.4/mips-fix-64-bit-htw-configuration.patch +++ /dev/null @@ -1,78 +0,0 @@ -From aa76042a016474775ccd187c068669148c30c3bb Mon Sep 17 00:00:00 2001 -From: James Hogan -Date: Fri, 27 May 2016 22:25:23 +0100 -Subject: MIPS: Fix 64-bit HTW configuration - -From: James Hogan - -commit aa76042a016474775ccd187c068669148c30c3bb upstream. - -The Hardware page Table Walker (HTW) is being misconfigured on 64-bit -kernels. The PWSize.PS (pointer size) bit determines whether pointers -within directories are loaded as 32-bit or 64-bit addresses, but was -never being set to 1 for 64-bit kernels where the unsigned long in pgd_t -is 64-bits wide. - -This actually reduces rather than improves performance when the HTW is -enabled on P6600 since the HTW is initiated lots, but walks are all -aborted due I think to bad intermediate pointers. - -Since we were already taking the width of the PTEs into account by -setting PWSize.PTEW, which is the left shift applied to the page table -index *in addition to* the native pointer size, we also need to reduce -PTEW by 1 when PS=1. This is done by calculating PTEW based on the -relative size of pte_t compared to pgd_t. - -Finally in order for the HTW to be used when PS=1, the appropriate -XK/XS/XU bits corresponding to the different 64-bit segments need to be -set in PWCtl. We enable only XU for now to enable walking for XUSeg. - -Supporting walking for XKSeg would be a bit more involved so is left for -a future patch. It would either require the use of a per-CPU top level -base directory if supported by the HTW (a bit like pgd_current but with -a second entry pointing at swapper_pg_dir), or the HTW would prepend bit -63 of the address to the global directory index which doesn't really -match how we split user and kernel page directories. - -Fixes: cab25bc7537b ("MIPS: Extend hardware table walking support to MIPS64") -Signed-off-by: James Hogan -Cc: Paul Burton -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/13364/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/mm/tlbex.c | 14 ++++++++++++-- - 1 file changed, 12 insertions(+), 2 deletions(-) - ---- a/arch/mips/mm/tlbex.c -+++ b/arch/mips/mm/tlbex.c -@@ -2329,15 +2329,25 @@ static void config_htw_params(void) - if (CONFIG_PGTABLE_LEVELS >= 3) - pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; - -- pwsize |= ilog2(sizeof(pte_t)/4) << MIPS_PWSIZE_PTEW_SHIFT; -+ /* Set pointer size to size of directory pointers */ -+ if (config_enabled(CONFIG_64BIT)) -+ pwsize |= MIPS_PWSIZE_PS_MASK; -+ /* PTEs may be multiple pointers long (e.g. with XPA) */ -+ pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) -+ & MIPS_PWSIZE_PTEW_MASK; - - write_c0_pwsize(pwsize); - - /* Make sure everything is set before we enable the HTW */ - back_to_back_c0_hazard(); - -- /* Enable HTW and disable the rest of the pwctl fields */ -+ /* -+ * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of -+ * the pwctl fields. -+ */ - config = 1 << MIPS_PWCTL_PWEN_SHIFT; -+ if (config_enabled(CONFIG_64BIT)) -+ config |= MIPS_PWCTL_XU_MASK; - write_c0_pwctl(config); - pr_info("Hardware Page Table Walker enabled\n"); - diff --git a/queue-4.4/mips-fix-little-endian-micromips-msa-encodings.patch b/queue-4.4/mips-fix-little-endian-micromips-msa-encodings.patch deleted file mode 100644 index 526e0ef34a1..00000000000 --- a/queue-4.4/mips-fix-little-endian-micromips-msa-encodings.patch +++ /dev/null @@ -1,297 +0,0 @@ -From 6e1b29c3094688b6803fa1f9d5da676a7d0fbff9 Mon Sep 17 00:00:00 2001 -From: James Hogan -Date: Fri, 20 May 2016 23:28:39 +0100 -Subject: MIPS: Fix little endian microMIPS MSA encodings - -From: James Hogan - -commit 6e1b29c3094688b6803fa1f9d5da676a7d0fbff9 upstream. - -When the toolchain doesn't support MSA we encode MSA instructions -explicitly in assembly. Unfortunately we use .word for both MIPS and -microMIPS encodings which is wrong, since 32-bit microMIPS instructions -are made up from a pair of halfwords. - -- The most significant halfword always comes first, so for little endian - builds the halves will be emitted in the wrong order. - -- 32-bit alignment isn't guaranteed, so the assembler may insert a - 16-bit nop instruction to pad the instruction stream to a 32-bit - boundary. - -Use the new instruction encoding macros to encode microMIPS MSA -instructions correctly. - -Fixes: d96cc3d1ec5d ("MIPS: Add microMIPS MSA support.") -Signed-off-by: James Hogan -Cc: Paul Burton -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/13312/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/include/asm/asmmacro.h | 99 +++++++++++++++++++-------------------- - arch/mips/include/asm/msa.h | 21 +++----- - 2 files changed, 58 insertions(+), 62 deletions(-) - ---- a/arch/mips/include/asm/asmmacro.h -+++ b/arch/mips/include/asm/asmmacro.h -@@ -19,6 +19,28 @@ - #include - #endif - -+/* -+ * Helper macros for generating raw instruction encodings. -+ */ -+#ifdef CONFIG_CPU_MICROMIPS -+ .macro insn32_if_mm enc -+ .insn -+ .hword ((\enc) >> 16) -+ .hword ((\enc) & 0xffff) -+ .endm -+ -+ .macro insn_if_mips enc -+ .endm -+#else -+ .macro insn32_if_mm enc -+ .endm -+ -+ .macro insn_if_mips enc -+ .insn -+ .word (\enc) -+ .endm -+#endif -+ - #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) - .macro local_irq_enable reg=t0 - ei -@@ -336,38 +358,6 @@ - .endm - #else - --#ifdef CONFIG_CPU_MICROMIPS --#define CFC_MSA_INSN 0x587e0056 --#define CTC_MSA_INSN 0x583e0816 --#define LDB_MSA_INSN 0x58000807 --#define LDH_MSA_INSN 0x58000817 --#define LDW_MSA_INSN 0x58000827 --#define LDD_MSA_INSN 0x58000837 --#define STB_MSA_INSN 0x5800080f --#define STH_MSA_INSN 0x5800081f --#define STW_MSA_INSN 0x5800082f --#define STD_MSA_INSN 0x5800083f --#define COPY_SW_MSA_INSN 0x58b00056 --#define COPY_SD_MSA_INSN 0x58b80056 --#define INSERT_W_MSA_INSN 0x59300816 --#define INSERT_D_MSA_INSN 0x59380816 --#else --#define CFC_MSA_INSN 0x787e0059 --#define CTC_MSA_INSN 0x783e0819 --#define LDB_MSA_INSN 0x78000820 --#define LDH_MSA_INSN 0x78000821 --#define LDW_MSA_INSN 0x78000822 --#define LDD_MSA_INSN 0x78000823 --#define STB_MSA_INSN 0x78000824 --#define STH_MSA_INSN 0x78000825 --#define STW_MSA_INSN 0x78000826 --#define STD_MSA_INSN 0x78000827 --#define COPY_SW_MSA_INSN 0x78b00059 --#define COPY_SD_MSA_INSN 0x78b80059 --#define INSERT_W_MSA_INSN 0x79300819 --#define INSERT_D_MSA_INSN 0x79380819 --#endif -- - /* - * Temporary until all toolchains in use include MSA support. - */ -@@ -375,8 +365,8 @@ - .set push - .set noat - SET_HARDFLOAT -- .insn -- .word CFC_MSA_INSN | (\cs << 11) -+ insn_if_mips 0x787e0059 | (\cs << 11) -+ insn32_if_mm 0x587e0056 | (\cs << 11) - move \rd, $1 - .set pop - .endm -@@ -386,7 +376,8 @@ - .set noat - SET_HARDFLOAT - move $1, \rs -- .word CTC_MSA_INSN | (\cd << 6) -+ insn_if_mips 0x783e0819 | (\cd << 6) -+ insn32_if_mm 0x583e0816 | (\cd << 6) - .set pop - .endm - -@@ -395,7 +386,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word LDB_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000820 | (\wd << 6) -+ insn32_if_mm 0x58000807 | (\wd << 6) - .set pop - .endm - -@@ -404,7 +396,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word LDH_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000821 | (\wd << 6) -+ insn32_if_mm 0x58000817 | (\wd << 6) - .set pop - .endm - -@@ -413,7 +406,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word LDW_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000822 | (\wd << 6) -+ insn32_if_mm 0x58000827 | (\wd << 6) - .set pop - .endm - -@@ -422,7 +416,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word LDD_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000823 | (\wd << 6) -+ insn32_if_mm 0x58000837 | (\wd << 6) - .set pop - .endm - -@@ -431,7 +426,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word STB_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000824 | (\wd << 6) -+ insn32_if_mm 0x5800080f | (\wd << 6) - .set pop - .endm - -@@ -440,7 +436,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word STH_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000825 | (\wd << 6) -+ insn32_if_mm 0x5800081f | (\wd << 6) - .set pop - .endm - -@@ -449,7 +446,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word STW_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000826 | (\wd << 6) -+ insn32_if_mm 0x5800082f | (\wd << 6) - .set pop - .endm - -@@ -458,7 +456,8 @@ - .set noat - SET_HARDFLOAT - PTR_ADDU $1, \base, \off -- .word STD_MSA_INSN | (\wd << 6) -+ insn_if_mips 0x78000827 | (\wd << 6) -+ insn32_if_mm 0x5800083f | (\wd << 6) - .set pop - .endm - -@@ -466,8 +465,8 @@ - .set push - .set noat - SET_HARDFLOAT -- .insn -- .word COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11) -+ insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11) -+ insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11) - .set pop - .endm - -@@ -475,8 +474,8 @@ - .set push - .set noat - SET_HARDFLOAT -- .insn -- .word COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11) -+ insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11) -+ insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11) - .set pop - .endm - -@@ -484,7 +483,8 @@ - .set push - .set noat - SET_HARDFLOAT -- .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) -+ insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6) -+ insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6) - .set pop - .endm - -@@ -492,7 +492,8 @@ - .set push - .set noat - SET_HARDFLOAT -- .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) -+ insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6) -+ insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6) - .set pop - .endm - #endif ---- a/arch/mips/include/asm/msa.h -+++ b/arch/mips/include/asm/msa.h -@@ -192,13 +192,6 @@ static inline void write_msa_##name(unsi - * allow compilation with toolchains that do not support MSA. Once all - * toolchains in use support MSA these can be removed. - */ --#ifdef CONFIG_CPU_MICROMIPS --#define CFC_MSA_INSN 0x587e0056 --#define CTC_MSA_INSN 0x583e0816 --#else --#define CFC_MSA_INSN 0x787e0059 --#define CTC_MSA_INSN 0x783e0819 --#endif - - #define __BUILD_MSA_CTL_REG(name, cs) \ - static inline unsigned int read_msa_##name(void) \ -@@ -207,11 +200,12 @@ static inline unsigned int read_msa_##na - __asm__ __volatile__( \ - " .set push\n" \ - " .set noat\n" \ -- " .insn\n" \ -- " .word %1 | (" #cs " << 11)\n" \ -+ " # cfcmsa $1, $%1\n" \ -+ _ASM_INSN_IF_MIPS(0x787e0059 | %1 << 11) \ -+ _ASM_INSN32_IF_MM(0x587e0056 | %1 << 11) \ - " move %0, $1\n" \ - " .set pop\n" \ -- : "=r"(reg) : "i"(CFC_MSA_INSN)); \ -+ : "=r"(reg) : "i"(cs)); \ - return reg; \ - } \ - \ -@@ -221,10 +215,11 @@ static inline void write_msa_##name(unsi - " .set push\n" \ - " .set noat\n" \ - " move $1, %0\n" \ -- " .insn\n" \ -- " .word %1 | (" #cs " << 6)\n" \ -+ " # ctcmsa $%1, $1\n" \ -+ _ASM_INSN_IF_MIPS(0x783e0819 | %1 << 6) \ -+ _ASM_INSN32_IF_MM(0x583e0816 | %1 << 6) \ - " .set pop\n" \ -- : : "r"(val), "i"(CTC_MSA_INSN)); \ -+ : : "r"(val), "i"(cs)); \ - } - - #endif /* !TOOLCHAIN_SUPPORTS_MSA */ diff --git a/queue-4.4/series b/queue-4.4/series index dd693c4b611..9d460673ac6 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -21,8 +21,6 @@ mips-math-emu-fix-bc1-eq-ne-z-emulation.patch mips-fix-bc1-eq-ne-z-return-offset-calculation.patch mips-math-emu-fix-m-add-sub-.s-shifts.patch mips-perf-fix-i6400-event-numbers.patch -mips-fix-64-bit-htw-configuration.patch -mips-fix-little-endian-micromips-msa-encodings.patch mips-kvm-fix-translation-of-mfc0-errctl.patch mips-smp-update-cpu_foreign_map-on-cpu-disable.patch mips-c-r4k-fix-protected_writeback_scache_line-for-eva.patch