From: Greg Kroah-Hartman Date: Tue, 21 Oct 2025 19:17:55 +0000 (+0200) Subject: 6.6-stable patches X-Git-Tag: v6.6.114~6 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8714161b1624b30ffa33a19d8ba6a7c034053ca1;p=thirdparty%2Fkernel%2Fstable-queue.git 6.6-stable patches added patches: pci-j721e-enable-acspcie-refclk-if-ti-syscon-acspcie-proxy-ctrl-exists.patch pci-j721e-fix-programming-sequence-of-strap-settings.patch pci-tegra194-reset-bars-when-running-in-pcie-endpoint-mode.patch --- diff --git a/queue-6.6/pci-j721e-enable-acspcie-refclk-if-ti-syscon-acspcie-proxy-ctrl-exists.patch b/queue-6.6/pci-j721e-enable-acspcie-refclk-if-ti-syscon-acspcie-proxy-ctrl-exists.patch new file mode 100644 index 0000000000..08c691d755 --- /dev/null +++ b/queue-6.6/pci-j721e-enable-acspcie-refclk-if-ti-syscon-acspcie-proxy-ctrl-exists.patch @@ -0,0 +1,94 @@ +From stable+bounces-188406-greg=kroah.com@vger.kernel.org Tue Oct 21 20:37:29 2025 +From: Sasha Levin +Date: Tue, 21 Oct 2025 14:37:21 -0400 +Subject: PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists +To: stable@vger.kernel.org +Cc: "Siddharth Vadapalli" , "Krzysztof Wilczyński" , "Manivannan Sadhasivam" , "Sasha Levin" +Message-ID: <20251021183722.2520843-1-sashal@kernel.org> + +From: Siddharth Vadapalli + +[ Upstream commit 82c4be4168e26a5593aaa1002b5678128a638824 ] + +The ACSPCIE module is capable of driving the reference clock required by +the PCIe Endpoint device. It is an alternative to on-board and external +reference clock generators. Enabling the output from the ACSPCIE module's +PAD IO Buffers requires clearing the "PAD IO disable" bits of the +ACSPCIE_PROXY_CTRL register in the CTRL_MMR register space. + +Add support to enable the ACSPCIE reference clock output using the optional +device-tree property "ti,syscon-acspcie-proxy-ctrl". + +Link: https://lore.kernel.org/linux-pci/20240829105316.1483684-3-s-vadapalli@ti.com +Signed-off-by: Siddharth Vadapalli +Signed-off-by: Krzysztof Wilczyński +Reviewed-by: Manivannan Sadhasivam +Stable-dep-of: f842d3313ba1 ("PCI: j721e: Fix programming sequence of "strap" settings") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/cadence/pci-j721e.c | 39 ++++++++++++++++++++++++++++- + 1 file changed, 38 insertions(+), 1 deletion(-) + +--- a/drivers/pci/controller/cadence/pci-j721e.c ++++ b/drivers/pci/controller/cadence/pci-j721e.c +@@ -48,6 +48,7 @@ enum link_status { + #define J721E_MODE_RC BIT(7) + #define LANE_COUNT(n) ((n) << 8) + ++#define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0) + #define GENERATION_SEL_MASK GENMASK(1, 0) + + struct j721e_pcie { +@@ -225,6 +226,36 @@ static int j721e_pcie_set_lane_count(str + return ret; + } + ++static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie, ++ struct regmap *syscon) ++{ ++ struct device *dev = pcie->cdns_pcie->dev; ++ struct device_node *node = dev->of_node; ++ u32 mask = ACSPCIE_PAD_DISABLE_MASK; ++ struct of_phandle_args args; ++ u32 val; ++ int ret; ++ ++ ret = of_parse_phandle_with_fixed_args(node, ++ "ti,syscon-acspcie-proxy-ctrl", ++ 1, 0, &args); ++ if (ret) { ++ dev_err(dev, ++ "ti,syscon-acspcie-proxy-ctrl has invalid arguments\n"); ++ return ret; ++ } ++ ++ /* Clear PAD IO disable bits to enable refclk output */ ++ val = ~(args.args[0]); ++ ret = regmap_update_bits(syscon, 0, mask, val); ++ if (ret) { ++ dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ + static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) + { + struct device *dev = pcie->cdns_pcie->dev; +@@ -264,7 +295,13 @@ static int j721e_pcie_ctrl_init(struct j + return ret; + } + +- return 0; ++ /* Enable ACSPCIE refclk output if the optional property exists */ ++ syscon = syscon_regmap_lookup_by_phandle_optional(node, ++ "ti,syscon-acspcie-proxy-ctrl"); ++ if (!syscon) ++ return 0; ++ ++ return j721e_enable_acspcie_refclk(pcie, syscon); + } + + static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, diff --git a/queue-6.6/pci-j721e-fix-programming-sequence-of-strap-settings.patch b/queue-6.6/pci-j721e-fix-programming-sequence-of-strap-settings.patch new file mode 100644 index 0000000000..c56b881044 --- /dev/null +++ b/queue-6.6/pci-j721e-fix-programming-sequence-of-strap-settings.patch @@ -0,0 +1,90 @@ +From stable+bounces-188407-greg=kroah.com@vger.kernel.org Tue Oct 21 20:37:31 2025 +From: Sasha Levin +Date: Tue, 21 Oct 2025 14:37:22 -0400 +Subject: PCI: j721e: Fix programming sequence of "strap" settings +To: stable@vger.kernel.org +Cc: Siddharth Vadapalli , Manivannan Sadhasivam , Sasha Levin +Message-ID: <20251021183722.2520843-2-sashal@kernel.org> + +From: Siddharth Vadapalli + +[ Upstream commit f842d3313ba179d4005096357289c7ad09cec575 ] + +The Cadence PCIe Controller integrated in the TI K3 SoCs supports both +Root-Complex and Endpoint modes of operation. The Glue Layer allows +"strapping" the Mode of operation of the Controller, the Link Speed +and the Link Width. This is enabled by programming the "PCIEn_CTRL" +register (n corresponds to the PCIe instance) within the CTRL_MMR +memory-mapped register space. The "reset-values" of the registers are +also different depending on the mode of operation. + +Since the PCIe Controller latches onto the "reset-values" immediately +after being powered on, if the Glue Layer configuration is not done while +the PCIe Controller is off, it will result in the PCIe Controller latching +onto the wrong "reset-values". In practice, this will show up as a wrong +representation of the PCIe Controller's capability structures in the PCIe +Configuration Space. Some such capabilities which are supported by the PCIe +Controller in the Root-Complex mode but are incorrectly latched onto as +being unsupported are: +- Link Bandwidth Notification +- Alternate Routing ID (ARI) Forwarding Support +- Next capability offset within Advanced Error Reporting (AER) capability + +Fix this by powering off the PCIe Controller before programming the "strap" +settings and powering it on after that. The runtime PM APIs namely +pm_runtime_put_sync() and pm_runtime_get_sync() will decrement and +increment the usage counter respectively, causing GENPD to power off and +power on the PCIe Controller. + +Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver") +Signed-off-by: Siddharth Vadapalli +Signed-off-by: Manivannan Sadhasivam +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20250908120828.1471776-1-s-vadapalli@ti.com +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/cadence/pci-j721e.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/drivers/pci/controller/cadence/pci-j721e.c ++++ b/drivers/pci/controller/cadence/pci-j721e.c +@@ -277,6 +277,25 @@ static int j721e_pcie_ctrl_init(struct j + if (!ret) + offset = args.args[0]; + ++ /* ++ * The PCIe Controller's registers have different "reset-values" ++ * depending on the "strap" settings programmed into the PCIEn_CTRL ++ * register within the CTRL_MMR memory-mapped register space. ++ * The registers latch onto a "reset-value" based on the "strap" ++ * settings sampled after the PCIe Controller is powered on. ++ * To ensure that the "reset-values" are sampled accurately, power ++ * off the PCIe Controller before programming the "strap" settings ++ * and power it on after that. The runtime PM APIs namely ++ * pm_runtime_put_sync() and pm_runtime_get_sync() will decrement and ++ * increment the usage counter respectively, causing GENPD to power off ++ * and power on the PCIe Controller. ++ */ ++ ret = pm_runtime_put_sync(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to power off PCIe Controller\n"); ++ return ret; ++ } ++ + ret = j721e_pcie_set_mode(pcie, syscon, offset); + if (ret < 0) { + dev_err(dev, "Failed to set pci mode\n"); +@@ -295,6 +314,12 @@ static int j721e_pcie_ctrl_init(struct j + return ret; + } + ++ ret = pm_runtime_get_sync(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to power on PCIe Controller\n"); ++ return ret; ++ } ++ + /* Enable ACSPCIE refclk output if the optional property exists */ + syscon = syscon_regmap_lookup_by_phandle_optional(node, + "ti,syscon-acspcie-proxy-ctrl"); diff --git a/queue-6.6/pci-tegra194-reset-bars-when-running-in-pcie-endpoint-mode.patch b/queue-6.6/pci-tegra194-reset-bars-when-running-in-pcie-endpoint-mode.patch new file mode 100644 index 0000000000..0a60ebd9c0 --- /dev/null +++ b/queue-6.6/pci-tegra194-reset-bars-when-running-in-pcie-endpoint-mode.patch @@ -0,0 +1,75 @@ +From stable+bounces-188399-greg=kroah.com@vger.kernel.org Tue Oct 21 20:25:25 2025 +From: Sasha Levin +Date: Tue, 21 Oct 2025 14:25:01 -0400 +Subject: PCI: tegra194: Reset BARs when running in PCIe endpoint mode +To: stable@vger.kernel.org +Cc: Niklas Cassel , Manivannan Sadhasivam , Bjorn Helgaas , Sasha Levin +Message-ID: <20251021182501.2509096-1-sashal@kernel.org> + +From: Niklas Cassel + +[ Upstream commit 42f9c66a6d0cc45758dab77233c5460e1cf003df ] + +Tegra already defines all BARs except BAR0 as BAR_RESERVED. This is +sufficient for pci-epf-test to not allocate backing memory and to not call +set_bar() for those BARs. However, marking a BAR as BAR_RESERVED does not +mean that the BAR gets disabled. + +The host side driver, pci_endpoint_test, simply does an ioremap for all +enabled BARs and will run tests against all enabled BARs, so it will run +tests against the BARs marked as BAR_RESERVED. + +After running the BAR tests (which will write to all enabled BARs), the +inbound address translation is broken. This is because the tegra controller +exposes the ATU Port Logic Structure in BAR4, so when BAR4 is written, the +inbound address translation settings get overwritten. + +To avoid this, implement the dw_pcie_ep_ops .init() callback and start off +by disabling all BARs (pci-epf-test will later enable/configure BARs that +are not defined as BAR_RESERVED). + +This matches the behavior of other PCIe endpoint drivers: dra7xx, imx6, +layerscape-ep, artpec6, dw-rockchip, qcom-ep, rcar-gen4, and uniphier-ep. + +With this, the PCI endpoint kselftest test case CONSECUTIVE_BAR_TEST (which +was specifically made to detect address translation issues) passes. + +Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") +Signed-off-by: Niklas Cassel +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20250922140822.519796-7-cassel@kernel.org +[ changed .init field to .ep_init in pcie_ep_ops struct ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/pci/controller/dwc/pcie-tegra194.c ++++ b/drivers/pci/controller/dwc/pcie-tegra194.c +@@ -1963,6 +1963,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst + return IRQ_HANDLED; + } + ++static void tegra_pcie_ep_init(struct dw_pcie_ep *ep) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ++ enum pci_barno bar; ++ ++ for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) ++ dw_pcie_ep_reset_bar(pci, bar); ++}; ++ + static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq) + { + /* Tegra194 supports only INTA */ +@@ -2036,6 +2045,7 @@ tegra_pcie_ep_get_features(struct dw_pci + } + + static const struct dw_pcie_ep_ops pcie_ep_ops = { ++ .ep_init = tegra_pcie_ep_init, + .raise_irq = tegra_pcie_ep_raise_irq, + .get_features = tegra_pcie_ep_get_features, + }; diff --git a/queue-6.6/series b/queue-6.6/series index bd412702c5..0f1a42aae3 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -100,3 +100,6 @@ nfsd-decouple-the-xprtsec-policy-check-from-check_nfsd_access.patch pci-sysfs-ensure-devices-are-powered-for-config-reads-part-2.patch ksmbd-browse-interfaces-list-on-fsctl_query_interface_info-ioctl.patch mm-ksm-fix-flag-dropping-behavior-in-ksm_madvise.patch +pci-j721e-enable-acspcie-refclk-if-ti-syscon-acspcie-proxy-ctrl-exists.patch +pci-j721e-fix-programming-sequence-of-strap-settings.patch +pci-tegra194-reset-bars-when-running-in-pcie-endpoint-mode.patch