From: Sasha Levin Date: Sat, 13 Jul 2024 16:34:07 +0000 (-0400) Subject: Fixes for 5.15 X-Git-Tag: v6.1.99~8 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8994cc3111395d359632f465f0b2d027a0749f74;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.15 Signed-off-by: Sasha Levin --- diff --git a/queue-5.15/arm-davinci-convert-comma-to-semicolon.patch b/queue-5.15/arm-davinci-convert-comma-to-semicolon.patch new file mode 100644 index 00000000000..6734bea4943 --- /dev/null +++ b/queue-5.15/arm-davinci-convert-comma-to-semicolon.patch @@ -0,0 +1,36 @@ +From 15b2ea7cc0c2b36c01a2bc9756ef13843d7a4074 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Jul 2024 16:16:48 +0800 +Subject: ARM: davinci: Convert comma to semicolon + +From: Chen Ni + +[ Upstream commit acc3815db1a02d654fbc19726ceaadca0d7dd81c ] + +Replace a comma between expression statements by a semicolon. + +Fixes: efc1bb8a6fd5 ("davinci: add power management support") +Signed-off-by: Chen Ni +Acked-by: Bartosz Golaszewski +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/arm/mach-davinci/pm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c +index 323ee4e657c45..94d7d69b9db7c 100644 +--- a/arch/arm/mach-davinci/pm.c ++++ b/arch/arm/mach-davinci/pm.c +@@ -62,7 +62,7 @@ static void davinci_pm_suspend(void) + + /* Configure sleep count in deep sleep register */ + val = __raw_readl(pm_config.deepsleep_reg); +- val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, ++ val &= ~DEEPSLEEP_SLEEPCOUNT_MASK; + val |= pm_config.sleepcount; + __raw_writel(val, pm_config.deepsleep_reg); + +-- +2.43.0 + diff --git a/queue-5.15/octeontx2-af-extend-rss-supported-offload-types.patch b/queue-5.15/octeontx2-af-extend-rss-supported-offload-types.patch new file mode 100644 index 00000000000..e7c54498a66 --- /dev/null +++ b/queue-5.15/octeontx2-af-extend-rss-supported-offload-types.patch @@ -0,0 +1,155 @@ +From ece88d3c3109dd529d5f9c5a56f35d3799aa49aa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Jun 2023 11:34:20 +0530 +Subject: octeontx2-af: extend RSS supported offload types + +From: Kiran Kumar K + +[ Upstream commit 79bc788c038c9c87224d41ba6bbab20b6bf1a141 ] + +Add support to select L3 SRC or DST only, L4 SRC or DST only for RSS +calculation. + +AF consumer may have requirement as we can select only SRC or DST data for +RSS calculation in L3, L4 layers. With this requirement there will be +following combinations, IPV[4,6]_SRC_ONLY, IPV[4,6]_DST_ONLY, +[TCP,UDP,SCTP]_SRC_ONLY, [TCP,UDP,SCTP]_DST_ONLY. So, instead of creating +a bit for each combination, we are using upper 4 bits (31:28) in the +flow_key_cfg to represent the SRC, DST selection. 31 => L3_SRC, +30 => L3_DST, 29 => L4_SRC, 28 => L4_DST. These won't be part of flow_cfg, +so that we don't need to change the existing ABI. + +Signed-off-by: Kiran Kumar K +Signed-off-by: Geetha sowjanya +Signed-off-by: Naveen Mamindlapalli +Signed-off-by: David S. Miller +Stable-dep-of: e23ac1095b9e ("octeontx2-af: fix issue with IPv6 ext match for RSS") +Signed-off-by: Sasha Levin +--- + .../net/ethernet/marvell/octeontx2/af/mbox.h | 6 ++ + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 57 +++++++++++++++++++ + 2 files changed, 63 insertions(+) + +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +index bd37fdced37cd..fafdf36ad58bf 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h ++++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +@@ -974,6 +974,8 @@ struct nix_vtag_config_rsp { + */ + }; + ++#define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) ++ + struct nix_rss_flowkey_cfg { + struct mbox_msghdr hdr; + int mcam_index; /* MCAM entry index to modify */ +@@ -999,6 +1001,10 @@ struct nix_rss_flowkey_cfg { + #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) + #define NIX_FLOW_KEY_TYPE_AH BIT(22) + #define NIX_FLOW_KEY_TYPE_ESP BIT(23) ++#define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) ++#define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) ++#define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) ++#define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) + u32 flowkey_cfg; /* Flowkey types selected */ + u8 group; /* RSS context or group */ + }; +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +index 34a9a9164f3c6..9398dd3ae09b5 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c ++++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +@@ -3314,6 +3314,7 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + struct nix_rx_flowkey_alg *field; + struct nix_rx_flowkey_alg tmp; + u32 key_type, valid_key; ++ u32 l3_l4_src_dst; + int l4_key_offset = 0; + + if (!alg) +@@ -3341,6 +3342,15 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + * group_member - Enabled when protocol is part of a group. + */ + ++ /* Last 4 bits (31:28) are reserved to specify SRC, DST ++ * selection for L3, L4 i.e IPV[4,6]_SRC, IPV[4,6]_DST, ++ * [TCP,UDP,SCTP]_SRC, [TCP,UDP,SCTP]_DST ++ * 31 => L3_SRC, 30 => L3_DST, 29 => L4_SRC, 28 => L4_DST ++ */ ++ l3_l4_src_dst = flow_cfg; ++ /* Reset these 4 bits, so that these won't be part of key */ ++ flow_cfg &= NIX_FLOW_KEY_TYPE_L3_L4_MASK; ++ + keyoff_marker = 0; max_key_off = 0; group_member = 0; + nr_field = 0; key_off = 0; field_marker = 1; + field = &tmp; max_bit_pos = fls(flow_cfg); +@@ -3378,6 +3388,22 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + } + field->hdr_offset = 12; /* SIP offset */ + field->bytesm1 = 7; /* SIP + DIP, 8 bytes */ ++ ++ /* Only SIP */ ++ if (l3_l4_src_dst & NIX_FLOW_KEY_TYPE_L3_SRC_ONLY) ++ field->bytesm1 = 3; /* SIP, 4 bytes */ ++ ++ if (l3_l4_src_dst & NIX_FLOW_KEY_TYPE_L3_DST_ONLY) { ++ /* Both SIP + DIP */ ++ if (field->bytesm1 == 3) { ++ field->bytesm1 = 7; /* SIP + DIP, 8B */ ++ } else { ++ /* Only DIP */ ++ field->hdr_offset = 16; /* DIP off */ ++ field->bytesm1 = 3; /* DIP, 4 bytes */ ++ } ++ } ++ + field->ltype_mask = 0xF; /* Match only IPv4 */ + keyoff_marker = false; + break; +@@ -3391,6 +3417,22 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + } + field->hdr_offset = 8; /* SIP offset */ + field->bytesm1 = 31; /* SIP + DIP, 32 bytes */ ++ ++ /* Only SIP */ ++ if (l3_l4_src_dst & NIX_FLOW_KEY_TYPE_L3_SRC_ONLY) ++ field->bytesm1 = 15; /* SIP, 16 bytes */ ++ ++ if (l3_l4_src_dst & NIX_FLOW_KEY_TYPE_L3_DST_ONLY) { ++ /* Both SIP + DIP */ ++ if (field->bytesm1 == 15) { ++ /* SIP + DIP, 32 bytes */ ++ field->bytesm1 = 31; ++ } else { ++ /* Only DIP */ ++ field->hdr_offset = 24; /* DIP off */ ++ field->bytesm1 = 15; /* DIP,16 bytes */ ++ } ++ } + field->ltype_mask = 0xF; /* Match only IPv6 */ + break; + case NIX_FLOW_KEY_TYPE_TCP: +@@ -3406,6 +3448,21 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + field->lid = NPC_LID_LH; + field->bytesm1 = 3; /* Sport + Dport, 4 bytes */ + ++ if (l3_l4_src_dst & NIX_FLOW_KEY_TYPE_L4_SRC_ONLY) ++ field->bytesm1 = 1; /* SRC, 2 bytes */ ++ ++ if (l3_l4_src_dst & NIX_FLOW_KEY_TYPE_L4_DST_ONLY) { ++ /* Both SRC + DST */ ++ if (field->bytesm1 == 1) { ++ /* SRC + DST, 4 bytes */ ++ field->bytesm1 = 3; ++ } else { ++ /* Only DIP */ ++ field->hdr_offset = 2; /* DST off */ ++ field->bytesm1 = 1; /* DST, 2 bytes */ ++ } ++ } ++ + /* Enum values for NPC_LID_LD and NPC_LID_LG are same, + * so no need to change the ltype_match, just change + * the lid for inner protocols +-- +2.43.0 + diff --git a/queue-5.15/octeontx2-af-fix-a-issue-with-cpt_lf_alloc-mailbox.patch b/queue-5.15/octeontx2-af-fix-a-issue-with-cpt_lf_alloc-mailbox.patch new file mode 100644 index 00000000000..360ba407c48 --- /dev/null +++ b/queue-5.15/octeontx2-af-fix-a-issue-with-cpt_lf_alloc-mailbox.patch @@ -0,0 +1,37 @@ +From fcc6269d303daf7eef636f347b606a7ff797871f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Jul 2024 13:21:24 +0530 +Subject: octeontx2-af: fix a issue with cpt_lf_alloc mailbox + +From: Srujana Challa + +[ Upstream commit 845fe19139ab5a1ee303a3bee327e3191c3938af ] + +This patch fixes CPT_LF_ALLOC mailbox error due to +incompatible mailbox message format. Specifically, it +corrects the `blkaddr` field type from `int` to `u8`. + +Fixes: de2854c87c64 ("octeontx2-af: Mailbox changes for 98xx CPT block") +Signed-off-by: Srujana Challa +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +index 9de649ab95bc6..bd37fdced37cd 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h ++++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +@@ -1442,7 +1442,7 @@ struct cpt_lf_alloc_req_msg { + u16 nix_pf_func; + u16 sso_pf_func; + u16 eng_grpmsk; +- int blkaddr; ++ u8 blkaddr; + u8 ctx_ilen_valid : 1; + u8 ctx_ilen : 7; + }; +-- +2.43.0 + diff --git a/queue-5.15/octeontx2-af-fix-detection-of-ip-layer.patch b/queue-5.15/octeontx2-af-fix-detection-of-ip-layer.patch new file mode 100644 index 00000000000..b83e434144e --- /dev/null +++ b/queue-5.15/octeontx2-af-fix-detection-of-ip-layer.patch @@ -0,0 +1,52 @@ +From 668c6984e7bd72dfc3380da245a50a2a13d1a08d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Jul 2024 13:21:25 +0530 +Subject: octeontx2-af: fix detection of IP layer + +From: Michal Mazur + +[ Upstream commit 404dc0fd6fb0bb942b18008c6f8c0320b80aca20 ] + +Checksum and length checks are not enabled for IPv4 header with +options and IPv6 with extension headers. +To fix this a change in enum npc_kpu_lc_ltype is required which will +allow adjustment of LTYPE_MASK to detect all types of IP headers. + +Fixes: 21e6699e5cd6 ("octeontx2-af: Add NPC KPU profile") +Signed-off-by: Michal Mazur +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/marvell/octeontx2/af/npc.h | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/ethernet/marvell/octeontx2/af/npc.h +index 0f88efe39e41a..bac083c5c2785 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h ++++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h +@@ -56,8 +56,13 @@ enum npc_kpu_lb_ltype { + NPC_LT_LB_CUSTOM1 = 0xF, + }; + ++/* Don't modify ltypes up to IP6_EXT, otherwise length and checksum of IP ++ * headers may not be checked correctly. IPv4 ltypes and IPv6 ltypes must ++ * differ only at bit 0 so mask 0xE can be used to detect extended headers. ++ */ + enum npc_kpu_lc_ltype { +- NPC_LT_LC_IP = 1, ++ NPC_LT_LC_PTP = 1, ++ NPC_LT_LC_IP, + NPC_LT_LC_IP_OPT, + NPC_LT_LC_IP6, + NPC_LT_LC_IP6_EXT, +@@ -65,7 +70,6 @@ enum npc_kpu_lc_ltype { + NPC_LT_LC_RARP, + NPC_LT_LC_MPLS, + NPC_LT_LC_NSH, +- NPC_LT_LC_PTP, + NPC_LT_LC_FCOE, + NPC_LT_LC_NGIO, + NPC_LT_LC_CUSTOM0 = 0xE, +-- +2.43.0 + diff --git a/queue-5.15/octeontx2-af-fix-issue-with-ipv4-match-for-rss.patch b/queue-5.15/octeontx2-af-fix-issue-with-ipv4-match-for-rss.patch new file mode 100644 index 00000000000..3b428ee6089 --- /dev/null +++ b/queue-5.15/octeontx2-af-fix-issue-with-ipv4-match-for-rss.patch @@ -0,0 +1,57 @@ +From a2285f898a3b902a2ff7da581a4c9f0bc29a8a3e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Jul 2024 13:21:27 +0530 +Subject: octeontx2-af: fix issue with IPv4 match for RSS + +From: Satheesh Paul + +[ Upstream commit 60795bbf047654c9f8ae88d34483233a56033578 ] + +While performing RSS based on IPv4, packets with +IPv4 options are not being considered. Adding changes +to match both plain IPv4 and IPv4 with option header. + +Fixes: 41a7aa7b800d ("octeontx2-af: NIX Rx flowkey configuration for RSS") +Signed-off-by: Satheesh Paul +Reviewed-by: Kalesh AP +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +index 279d93bb74a0e..641f1d969bb75 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c ++++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +@@ -3309,6 +3309,8 @@ static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg) + + /* Mask to match ipv6(NPC_LT_LC_IP6) and ipv6 ext(NPC_LT_LC_IP6_EXT) */ + #define NPC_LT_LC_IP6_MATCH_MSK ((~(NPC_LT_LC_IP6 ^ NPC_LT_LC_IP6_EXT)) & 0xf) ++/* Mask to match both ipv4(NPC_LT_LC_IP) and ipv4 ext(NPC_LT_LC_IP_OPT) */ ++#define NPC_LT_LC_IP_MATCH_MSK ((~(NPC_LT_LC_IP ^ NPC_LT_LC_IP_OPT)) & 0xf) + + static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + { +@@ -3379,7 +3381,7 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + field->hdr_offset = 9; /* offset */ + field->bytesm1 = 0; /* 1 byte */ + field->ltype_match = NPC_LT_LC_IP; +- field->ltype_mask = 0xF; ++ field->ltype_mask = NPC_LT_LC_IP_MATCH_MSK; + break; + case NIX_FLOW_KEY_TYPE_IPV4: + case NIX_FLOW_KEY_TYPE_INNR_IPV4: +@@ -3406,8 +3408,7 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + field->bytesm1 = 3; /* DIP, 4 bytes */ + } + } +- +- field->ltype_mask = 0xF; /* Match only IPv4 */ ++ field->ltype_mask = NPC_LT_LC_IP_MATCH_MSK; + keyoff_marker = false; + break; + case NIX_FLOW_KEY_TYPE_IPV6: +-- +2.43.0 + diff --git a/queue-5.15/octeontx2-af-fix-issue-with-ipv6-ext-match-for-rss.patch b/queue-5.15/octeontx2-af-fix-issue-with-ipv6-ext-match-for-rss.patch new file mode 100644 index 00000000000..2fa7bc2771d --- /dev/null +++ b/queue-5.15/octeontx2-af-fix-issue-with-ipv6-ext-match-for-rss.patch @@ -0,0 +1,50 @@ +From 98ccb7f54e089d567ef65e9e9bfc937eed3e817d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Jul 2024 13:21:26 +0530 +Subject: octeontx2-af: fix issue with IPv6 ext match for RSS + +From: Kiran Kumar K + +[ Upstream commit e23ac1095b9eb8ac48f98c398d81d6ba062c9b5d ] + +While performing RSS based on IPv6, extension ltype +is not being considered. This will be problem for +fragmented packets or packets with extension header. +Adding changes to match IPv6 ext header along with IPv6 +ltype. + +Fixes: 41a7aa7b800d ("octeontx2-af: NIX Rx flowkey configuration for RSS") +Signed-off-by: Kiran Kumar K +Reviewed-by: Kalesh AP +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +index 9398dd3ae09b5..279d93bb74a0e 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c ++++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +@@ -3307,6 +3307,9 @@ static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg) + return -ERANGE; + } + ++/* Mask to match ipv6(NPC_LT_LC_IP6) and ipv6 ext(NPC_LT_LC_IP6_EXT) */ ++#define NPC_LT_LC_IP6_MATCH_MSK ((~(NPC_LT_LC_IP6 ^ NPC_LT_LC_IP6_EXT)) & 0xf) ++ + static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + { + int idx, nr_field, key_off, field_marker, keyoff_marker; +@@ -3433,7 +3436,7 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) + field->bytesm1 = 15; /* DIP,16 bytes */ + } + } +- field->ltype_mask = 0xF; /* Match only IPv6 */ ++ field->ltype_mask = NPC_LT_LC_IP6_MATCH_MSK; + break; + case NIX_FLOW_KEY_TYPE_TCP: + case NIX_FLOW_KEY_TYPE_UDP: +-- +2.43.0 + diff --git a/queue-5.15/octeontx2-af-replace-cpt-slot-with-lf-id-on-reg-writ.patch b/queue-5.15/octeontx2-af-replace-cpt-slot-with-lf-id-on-reg-writ.patch new file mode 100644 index 00000000000..98c249f3cfd --- /dev/null +++ b/queue-5.15/octeontx2-af-replace-cpt-slot-with-lf-id-on-reg-writ.patch @@ -0,0 +1,71 @@ +From 662772349cf5aa34d1c1ceb1e0d8903d97e70e82 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Jul 2024 13:21:23 +0530 +Subject: octeontx2-af: replace cpt slot with lf id on reg write + +From: Nithin Dabilpuram + +[ Upstream commit bc35e28af7890085dcbe5cc32373647dfb4d9af9 ] + +Replace slot id with global CPT lf id on reg read/write as +CPTPF/VF driver would send slot number instead of global +lf id in the reg offset. And also update the mailbox response +with the global lf's register offset. + +Fixes: ae454086e3c2 ("octeontx2-af: add mailbox interface for CPT") +Signed-off-by: Nithin Dabilpuram +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + .../ethernet/marvell/octeontx2/af/rvu_cpt.c | 23 +++++++++++++------ + 1 file changed, 16 insertions(+), 7 deletions(-) + +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +index 4895faa667b50..767c975ef7f38 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c ++++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +@@ -260,7 +260,8 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, + struct cpt_rd_wr_reg_msg *req, + struct cpt_rd_wr_reg_msg *rsp) + { +- int blkaddr; ++ u64 offset = req->reg_offset; ++ int blkaddr, lf; + + blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); + if (blkaddr < 0) +@@ -271,17 +272,25 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, + !is_cpt_vf(rvu, req->hdr.pcifunc)) + return CPT_AF_ERR_ACCESS_DENIED; + +- rsp->reg_offset = req->reg_offset; +- rsp->ret_val = req->ret_val; +- rsp->is_write = req->is_write; +- + if (!is_valid_offset(rvu, req)) + return CPT_AF_ERR_ACCESS_DENIED; + ++ /* Translate local LF used by VFs to global CPT LF */ ++ lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], req->hdr.pcifunc, ++ (offset & 0xFFF) >> 3); ++ ++ /* Translate local LF's offset to global CPT LF's offset */ ++ offset &= 0xFF000; ++ offset += lf << 3; ++ ++ rsp->reg_offset = offset; ++ rsp->ret_val = req->ret_val; ++ rsp->is_write = req->is_write; ++ + if (req->is_write) +- rvu_write64(rvu, blkaddr, req->reg_offset, req->val); ++ rvu_write64(rvu, blkaddr, offset, req->val); + else +- rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset); ++ rsp->val = rvu_read64(rvu, blkaddr, offset); + + return 0; + } +-- +2.43.0 + diff --git a/queue-5.15/octeontx2-af-update-cpt-lf-alloc-mailbox.patch b/queue-5.15/octeontx2-af-update-cpt-lf-alloc-mailbox.patch new file mode 100644 index 00000000000..3ad481921be --- /dev/null +++ b/queue-5.15/octeontx2-af-update-cpt-lf-alloc-mailbox.patch @@ -0,0 +1,69 @@ +From 8fe8390368b2dd7a855b676763b5be0b6266ead2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 18 Jan 2023 17:33:53 +0530 +Subject: octeontx2-af: update cpt lf alloc mailbox + +From: Srujana Challa + +[ Upstream commit c0688ec002a451d04a51d43b849765c5ce6cb36f ] + +The CN10K CPT coprocessor contains a context processor +to accelerate updates to the IPsec security association +contexts. The context processor contains a context cache. +This patch updates CPT LF ALLOC mailbox to config ctx_ilen +requested by VFs. CPT_LF_ALLOC:ctx_ilen is the size of +initial context fetch. + +Signed-off-by: Srujana Challa +Signed-off-by: David S. Miller +Stable-dep-of: 845fe19139ab ("octeontx2-af: fix a issue with cpt_lf_alloc mailbox") +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 ++ + drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c | 10 +++++++--- + 2 files changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +index 2b6cbd5af100d..9de649ab95bc6 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h ++++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +@@ -1443,6 +1443,8 @@ struct cpt_lf_alloc_req_msg { + u16 sso_pf_func; + u16 eng_grpmsk; + int blkaddr; ++ u8 ctx_ilen_valid : 1; ++ u8 ctx_ilen : 7; + }; + + /* Mailbox message request and response format for CPT stats. */ +diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +index 767c975ef7f38..19296e2cfe4de 100644 +--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c ++++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +@@ -17,7 +17,7 @@ + #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2 + + /* Length of initial context fetch in 128 byte words */ +-#define CPT_CTX_ILEN 2 ++#define CPT_CTX_ILEN 1ULL + + #define cpt_get_eng_sts(e_min, e_max, rsp, etype) \ + ({ \ +@@ -142,8 +142,12 @@ int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu, + + /* Set CPT LF group and priority */ + val = (u64)req->eng_grpmsk << 48 | 1; +- if (!is_rvu_otx2(rvu)) +- val |= (CPT_CTX_ILEN << 17); ++ if (!is_rvu_otx2(rvu)) { ++ if (req->ctx_ilen_valid) ++ val |= (req->ctx_ilen << 17); ++ else ++ val |= (CPT_CTX_ILEN << 17); ++ } + + rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); + +-- +2.43.0 + diff --git a/queue-5.15/s390-mark-psw-in-__load_psw_mask-as-__unitialized.patch b/queue-5.15/s390-mark-psw-in-__load_psw_mask-as-__unitialized.patch new file mode 100644 index 00000000000..403dae3c0a9 --- /dev/null +++ b/queue-5.15/s390-mark-psw-in-__load_psw_mask-as-__unitialized.patch @@ -0,0 +1,47 @@ +From f85850b2992a88f11c42c798a2b5d4da5af06457 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Apr 2024 16:30:01 +0200 +Subject: s390: Mark psw in __load_psw_mask() as __unitialized + +From: Sven Schnelle + +[ Upstream commit 7278a8fb8d032dfdc03d9b5d17e0bc451cdc1492 ] + +Without __unitialized, the following code is generated when +INIT_STACK_ALL_ZERO is enabled: + +86: d7 0f f0 a0 f0 a0 xc 160(16,%r15), 160(%r15) +8c: e3 40 f0 a0 00 24 stg %r4, 160(%r15) +92: c0 10 00 00 00 08 larl %r1, 0xa2 +98: e3 10 f0 a8 00 24 stg %r1, 168(%r15) +9e: b2 b2 f0 a0 lpswe 160(%r15) + +The xc is not adding any security because psw is fully initialized +with the following instructions. Add __unitialized to the psw +definitiation to avoid the superfluous clearing of psw. + +Reviewed-by: Heiko Carstens +Signed-off-by: Sven Schnelle +Signed-off-by: Alexander Gordeev +Signed-off-by: Sasha Levin +--- + arch/s390/include/asm/processor.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h +index d7ca76bb2720f..2ba16e67c96d5 100644 +--- a/arch/s390/include/asm/processor.h ++++ b/arch/s390/include/asm/processor.h +@@ -250,8 +250,8 @@ static inline void __load_psw(psw_t psw) + */ + static __always_inline void __load_psw_mask(unsigned long mask) + { ++ psw_t psw __uninitialized; + unsigned long addr; +- psw_t psw; + + psw.mask = mask; + +-- +2.43.0 + diff --git a/queue-5.15/series b/queue-5.15/series index 50ded81c486..d032078cf01 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -93,3 +93,12 @@ ppp-reject-claimed-as-lcp-but-actually-malformed-pac.patch ethtool-netlink-do-not-return-sqi-value-if-link-is-d.patch udp-set-sock_rcu_free-earlier-in-udp_lib_get_port.patch net-sched-fix-uaf-when-resolving-a-clash.patch +s390-mark-psw-in-__load_psw_mask-as-__unitialized.patch +arm-davinci-convert-comma-to-semicolon.patch +octeontx2-af-replace-cpt-slot-with-lf-id-on-reg-writ.patch +octeontx2-af-update-cpt-lf-alloc-mailbox.patch +octeontx2-af-fix-a-issue-with-cpt_lf_alloc-mailbox.patch +octeontx2-af-fix-detection-of-ip-layer.patch +octeontx2-af-extend-rss-supported-offload-types.patch +octeontx2-af-fix-issue-with-ipv6-ext-match-for-rss.patch +octeontx2-af-fix-issue-with-ipv4-match-for-rss.patch