From: H.J. Lu <hjl.tools@gmail.com>
Date: Tue, 15 May 2012 16:35:43 +0000 (-0700)
Subject: Load cache size into R8_LP
X-Git-Tag: glibc-2.16-tps~337
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8a17f34979b8425fdd74c15872d78c4d56a68079;p=thirdparty%2Fglibc.git

Load cache size into R8_LP
---

diff --git a/ChangeLog b/ChangeLog
index 7a1c154993a..51b0bd57004 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2012-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* sysdeps/x86_64/multiarch/memcmp-sse4.S: Load cache size into
+	R8_LP.
+
 2012-05-15  Adhemerval Zanella  <azanella@linux.vnet.ibm.com>
 
 	* sysdeps/powerpc/powerpc32/power7/fpu/s_logb.c: New file. Optimized
diff --git a/sysdeps/x86_64/multiarch/memcmp-sse4.S b/sysdeps/x86_64/multiarch/memcmp-sse4.S
index 530bf8ecd4b..2c8786599f9 100644
--- a/sysdeps/x86_64/multiarch/memcmp-sse4.S
+++ b/sysdeps/x86_64/multiarch/memcmp-sse4.S
@@ -319,9 +319,9 @@ L(less32bytesin256):
 	ALIGN (4)
 L(512bytesormore):
 # ifdef DATA_CACHE_SIZE_HALF
-	mov	$DATA_CACHE_SIZE_HALF, %r8
+	mov	$DATA_CACHE_SIZE_HALF, %R8_LP
 # else
-	mov	__x86_64_data_cache_size_half(%rip), %r8
+	mov	__x86_64_data_cache_size_half(%rip), %R8_LP
 # endif
 	mov	%r8, %r9
 	shr	$1, %r8
@@ -635,9 +635,9 @@ L(less32bytesin256in2alinged):
 	ALIGN (4)
 L(512bytesormorein2aligned):
 # ifdef DATA_CACHE_SIZE_HALF
-	mov	$DATA_CACHE_SIZE_HALF, %r8
+	mov	$DATA_CACHE_SIZE_HALF, %R8_LP
 # else
-	mov	__x86_64_data_cache_size_half(%rip), %r8
+	mov	__x86_64_data_cache_size_half(%rip), %R8_LP
 # endif
 	mov	%r8, %r9
 	shr	$1, %r8