From: Benoît Monin Date: Mon, 16 Mar 2026 15:25:44 +0000 (+0100) Subject: clk: eyeq: Skip post-divisor when computing PLL frequency X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8ab1e58ca9eb21d44c4716141248acac1d0635cd;p=thirdparty%2Fkernel%2Flinux.git clk: eyeq: Skip post-divisor when computing PLL frequency The output of the PLL is routed before the post-divisor so it should be ignored when computing the frequency of the PLL, functional change is implemented to reflect how the clock signal is wired internally. For the PLL of the EyeQ5, EyeQ6L, and EyeQ6H, this change has no impact as the post-divisor is either reported as disabled or set to 1. The PLL frequency is the same before and after the post-divisor. For the PLL in EyeQ6Lplus, however, the post-divisor is not 1, so it must be ignored to compute the correct frequency. Signed-off-by: Benoît Monin Acked-by: Stephen Boyd Signed-off-by: Thomas Bogendoerfer --- diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 81137269352da..5166b65382a96 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -177,8 +177,6 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, *mult = FIELD_GET(PCSR0_INTIN, r0); *div = FIELD_GET(PCSR0_REF_DIV, r0); - if (r0 & PCSR0_FOUTPOSTDIV_EN) - *div *= FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0); /* Fractional mode, in 2^20 (0x100000) parts. */ if (r0 & PCSR0_DSM_EN) {