From: Greg Kroah-Hartman Date: Mon, 4 May 2020 13:16:45 +0000 (+0200) Subject: 4.4-stable patches X-Git-Tag: v4.4.222~14 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8c4bf5ce8d0806b6e4cd938777dd64cb5e6375b4;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: exynos4-is-fix-a-format-string-bug.patch i2c-designware-pci-use-irqf_cond_suspend-flag.patch perf-hists-fix-histc_mem_dcacheline-width-setting.patch perf-x86-fix-uninitialized-value-usage.patch powerpc-perf-remove-ppmu_has_sslot-flag-for-power8.patch --- diff --git a/queue-4.4/exynos4-is-fix-a-format-string-bug.patch b/queue-4.4/exynos4-is-fix-a-format-string-bug.patch new file mode 100644 index 00000000000..0efd4f2a36f --- /dev/null +++ b/queue-4.4/exynos4-is-fix-a-format-string-bug.patch @@ -0,0 +1,37 @@ +From 76a563675485849f6f9ad5b30df220438b3628c1 Mon Sep 17 00:00:00 2001 +From: Rasmus Villemoes +Date: Tue, 8 Dec 2015 12:15:54 -0200 +Subject: [media] exynos4-is: fix a format string bug + +From: Rasmus Villemoes + +commit 76a563675485849f6f9ad5b30df220438b3628c1 upstream. + +Ironically, 7d4020c3c400 ("[media] exynos4-is: fix some warnings when +compiling on arm64") fixed some format string bugs but introduced a +new one. buf_index is a simple int, so it should be printed with %d, +not %pad (which is correctly used for dma_addr_t). + +Fixes: 7d4020c3c400 ("[media] exynos4-is: fix some warnings when compiling on arm64") + +Signed-off-by: Rasmus Villemoes +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/media/platform/exynos4-is/fimc-isp-video.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/exynos4-is/fimc-isp-video.c ++++ b/drivers/media/platform/exynos4-is/fimc-isp-video.c +@@ -221,8 +221,8 @@ static void isp_video_capture_buffer_que + ivb->dma_addr[i]; + + isp_dbg(2, &video->ve.vdev, +- "dma_buf %pad (%d/%d/%d) addr: %pad\n", +- &buf_index, ivb->index, i, vb->index, ++ "dma_buf %d (%d/%d/%d) addr: %pad\n", ++ buf_index, ivb->index, i, vb->index, + &ivb->dma_addr[i]); + } + diff --git a/queue-4.4/i2c-designware-pci-use-irqf_cond_suspend-flag.patch b/queue-4.4/i2c-designware-pci-use-irqf_cond_suspend-flag.patch new file mode 100644 index 00000000000..d016959f9f6 --- /dev/null +++ b/queue-4.4/i2c-designware-pci-use-irqf_cond_suspend-flag.patch @@ -0,0 +1,38 @@ +From 08c6e8cc66282a082484480c1a5641bc27d26c55 Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko +Date: Fri, 15 Jan 2016 22:02:12 +0200 +Subject: i2c: designware-pci: use IRQF_COND_SUSPEND flag + +From: Andy Shevchenko + +commit 08c6e8cc66282a082484480c1a5641bc27d26c55 upstream. + +This is effectively reapplies the commit b0898fdaffb2 ("i2c: designware-pci: use +IRQF_COND_SUSPEND flag") after the commit d80d134182ba ("i2c: designware: Move +common probe code into i2c_dw_probe()"). Original message as follows. + +The mentioned flag fixes a warning on Intel Edison board since one of the I2C +controller shares IRQ line with watchdog timer. + +Fixes: d80d134182ba (i2c: designware: Move common probe code into i2c_dw_probe()) +Signed-off-by: Andy Shevchenko +Acked-by: Jarkko Nikula +Signed-off-by: Wolfram Sang +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/i2c/busses/i2c-designware-core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/i2c/busses/i2c-designware-core.c ++++ b/drivers/i2c/busses/i2c-designware-core.c +@@ -865,7 +865,8 @@ int i2c_dw_probe(struct dw_i2c_dev *dev) + i2c_set_adapdata(adap, dev); + + i2c_dw_disable_int(dev); +- r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, IRQF_SHARED, ++ r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, ++ IRQF_SHARED | IRQF_COND_SUSPEND, + dev_name(dev->dev), dev); + if (r) { + dev_err(dev->dev, "failure requesting irq %i: %d\n", diff --git a/queue-4.4/perf-hists-fix-histc_mem_dcacheline-width-setting.patch b/queue-4.4/perf-hists-fix-histc_mem_dcacheline-width-setting.patch new file mode 100644 index 00000000000..716ca55112d --- /dev/null +++ b/queue-4.4/perf-hists-fix-histc_mem_dcacheline-width-setting.patch @@ -0,0 +1,36 @@ +From 0805909f59e02036a4e2660159f27dbf8b6084ac Mon Sep 17 00:00:00 2001 +From: Jiri Olsa +Date: Wed, 20 Jan 2016 12:56:33 +0100 +Subject: perf hists: Fix HISTC_MEM_DCACHELINE width setting + +From: Jiri Olsa + +commit 0805909f59e02036a4e2660159f27dbf8b6084ac upstream. + +Set correct width for unresolved mem_dcacheline addr. + +Signed-off-by: Jiri Olsa +Cc: David Ahern +Cc: Don Zickus +Cc: Namhyung Kim +Cc: Peter Zijlstra +Fixes: 9b32ba71ba90 ("perf tools: Add dcacheline sort") +Link: http://lkml.kernel.org/r/1453290995-18485-3-git-send-email-jolsa@kernel.org +Signed-off-by: Arnaldo Carvalho de Melo +Signed-off-by: Greg Kroah-Hartman + +--- + tools/perf/util/hist.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/tools/perf/util/hist.c ++++ b/tools/perf/util/hist.c +@@ -131,6 +131,8 @@ void hists__calc_col_len(struct hists *h + symlen = unresolved_col_width + 4 + 2; + hists__new_col_len(hists, HISTC_MEM_DADDR_SYMBOL, + symlen); ++ hists__new_col_len(hists, HISTC_MEM_DCACHELINE, ++ symlen); + } + + if (h->mem_info->iaddr.sym) { diff --git a/queue-4.4/perf-x86-fix-uninitialized-value-usage.patch b/queue-4.4/perf-x86-fix-uninitialized-value-usage.patch new file mode 100644 index 00000000000..9cc69b98225 --- /dev/null +++ b/queue-4.4/perf-x86-fix-uninitialized-value-usage.patch @@ -0,0 +1,54 @@ +From e01d8718de4170373cd7fbf5cf6f9cb61cebb1e9 Mon Sep 17 00:00:00 2001 +From: Peter Zijlstra +Date: Wed, 27 Jan 2016 23:24:29 +0100 +Subject: perf/x86: Fix uninitialized value usage + +From: Peter Zijlstra + +commit e01d8718de4170373cd7fbf5cf6f9cb61cebb1e9 upstream. + +When calling intel_alt_er() with .idx != EXTRA_REG_RSP_* we will not +initialize alt_idx and then use this uninitialized value to index an +array. + +When that is not fatal, it can result in an infinite loop in its +caller __intel_shared_reg_get_constraints(), with IRQs disabled. + +Alternative error modes are random memory corruption due to the +cpuc->shared_regs->regs[] array overrun, which manifest in either +get_constraints or put_constraints doing weird stuff. + +Only took 6 hours of painful debugging to find this. Neither GCC nor +Smatch warnings flagged this bug. + +Signed-off-by: Peter Zijlstra (Intel) +Cc: Arnaldo Carvalho de Melo +Cc: David Ahern +Cc: Jiri Olsa +Cc: Kan Liang +Cc: Linus Torvalds +Cc: Namhyung Kim +Cc: Peter Zijlstra +Cc: Stephane Eranian +Cc: Thomas Gleixner +Cc: Vince Weaver +Fixes: ae3f011fc251 ("perf/x86/intel: Fix SLM MSR_OFFCORE_RSP1 valid_mask") +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/cpu/perf_event_intel.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/x86/kernel/cpu/perf_event_intel.c ++++ b/arch/x86/kernel/cpu/perf_event_intel.c +@@ -1937,7 +1937,8 @@ intel_bts_constraints(struct perf_event + + static int intel_alt_er(int idx, u64 config) + { +- int alt_idx; ++ int alt_idx = idx; ++ + if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) + return idx; + diff --git a/queue-4.4/powerpc-perf-remove-ppmu_has_sslot-flag-for-power8.patch b/queue-4.4/powerpc-perf-remove-ppmu_has_sslot-flag-for-power8.patch new file mode 100644 index 00000000000..3d979315b66 --- /dev/null +++ b/queue-4.4/powerpc-perf-remove-ppmu_has_sslot-flag-for-power8.patch @@ -0,0 +1,47 @@ +From 370f06c88528b3988fe24a372c10e1303bb94cf6 Mon Sep 17 00:00:00 2001 +From: Madhavan Srinivasan +Date: Mon, 25 Jan 2016 14:03:46 +0530 +Subject: powerpc/perf: Remove PPMU_HAS_SSLOT flag for Power8 + +From: Madhavan Srinivasan + +commit 370f06c88528b3988fe24a372c10e1303bb94cf6 upstream. + +Commit 7a7868326d77 ("powerpc/perf: Add an explict flag indicating +presence of SLOT field") introduced the PPMU_HAS_SSLOT flag to remove +the assumption that MMCRA[SLOT] was present when PPMU_ALT_SIPR was not +set. + +That commit's changelog also mentions that Power8 does not support +MMCRA[SLOT]. However when the Power8 PMU support was merged, it +errnoeously included the PPMU_HAS_SSLOT flag. + +So remove PPMU_HAS_SSLOT from the Power8 flags. + +mpe: On systems where MMCRA[SLOT] exists, the field occupies bits 37:39 +(IBM numbering). On Power8 bit 37 is reserved, and 38:39 overlap with +the high bits of the Threshold Event Counter Mantissa. I am not aware of +any published events which use the threshold counting mechanism, which +would cause the mantissa bits to be set. So in practice this bug is +unlikely to trigger. + +Fixes: e05b9b9e5c10 ("powerpc/perf: Power8 PMU support") +Signed-off-by: Madhavan Srinivasan +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/perf/power8-pmu.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/powerpc/perf/power8-pmu.c ++++ b/arch/powerpc/perf/power8-pmu.c +@@ -816,7 +816,7 @@ static struct power_pmu power8_pmu = { + .get_constraint = power8_get_constraint, + .get_alternatives = power8_get_alternatives, + .disable_pmc = power8_disable_pmc, +- .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_ARCH_207S, ++ .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, + .n_generic = ARRAY_SIZE(power8_generic_events), + .generic_events = power8_generic_events, + .cache_events = &power8_cache_events, diff --git a/queue-4.4/series b/queue-4.4/series index 651ea12eb08..45fe3ab0f7e 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -7,3 +7,8 @@ vfio-type1-fix-va-pa-translation-for-pfnmap-vmas-in-vaddr_get_pfn.patch alsa-opti9xx-shut-up-gcc-10-range-warning.patch nfs-fix-potential-posix_acl-refcnt-leak-in-nfs3_set_acl.patch dmaengine-dmatest-fix-iteration-non-stop-logic.patch +i2c-designware-pci-use-irqf_cond_suspend-flag.patch +perf-hists-fix-histc_mem_dcacheline-width-setting.patch +powerpc-perf-remove-ppmu_has_sslot-flag-for-power8.patch +perf-x86-fix-uninitialized-value-usage.patch +exynos4-is-fix-a-format-string-bug.patch