From: J"orn Rennecke <joern.rennecke@superh.com>
Date: Thu, 3 Apr 2003 16:21:48 +0000 (+0000)
Subject: * Avoid clash of temp register for restoring target registers
X-Git-Tag: releases/gcc-3.4.0~7501
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8d3b0953482c3e696d4173a8de504c84e0304953;p=thirdparty%2Fgcc.git

* Avoid clash of temp register for restoring target registers
	with EH_RETURN_STACKADJ_RTX; use multiple registers in round-robin
	fashion.

From-SVN: r65202
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3d9392bf3763..286ac09ab25a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+Thu Apr  3 17:08:09 2003  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* Avoid clash of temp register for restoring target registers
+	with EH_RETURN_STACKADJ_RTX; use multiple registers in round-robin
+	fashion.
+
 2003-04-03  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
 	* gengtype-lex.l (IWORD): Add CHAR_BITFIELD.
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 501e1daeb898..d81a82acc5fe 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -5198,6 +5198,7 @@ sh_expand_epilogue ()
       int sp_in_r0 = 0;
       int align;
       rtx r0 = gen_rtx_REG (Pmode, R0_REG);
+      int tmp_regno = R20_REG;
       
       /* We loop twice: first, we save 8-byte aligned registers in the
 	 higher addresses, that are known to be aligned.  Then, we
@@ -5312,10 +5313,15 @@ sh_expand_epilogue ()
 		}
 	      else if (TARGET_REGISTER_P (i))
 		{
-		  rtx r1 = gen_rtx_REG (mode, R1_REG);
-
-		  insn = emit_move_insn (r1, mem_rtx);
-		  mem_rtx = r1;
+		  rtx tmp_reg = gen_rtx_REG (mode, tmp_regno);
+
+		  /* Give the scheduler a bit of freedom by using R20..R23
+		     in a round-robin fashion.  Don't use R1 here because
+		     we want to use it for EH_RETURN_STACKADJ_RTX.  */
+		  insn = emit_move_insn (tmp_reg, mem_rtx);
+		  mem_rtx = tmp_reg;
+		  if (++tmp_regno > R23_REG)
+		    tmp_regno = R20_REG;
 		}
 
 	      insn = emit_move_insn (reg_rtx, mem_rtx);