From: Vinod Koul Date: Mon, 23 Feb 2026 07:10:32 +0000 (+0530) Subject: phy: phy-mtk-tphy: Update names and format of kernel-doc comments X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8d869bc943cfe5db08f5aff355b1d8d3abeda865;p=thirdparty%2Fkernel%2Flinux.git phy: phy-mtk-tphy: Update names and format of kernel-doc comments mtk_phy_pdata documentation does not use correct tag for struct, while at it fix one of member wrongly documented. Warning: drivers/phy/mediatek/phy-mtk-tphy.c:289 cannot understand function prototype: 'struct mtk_phy_pdata' Warning: drivers/phy/mediatek/phy-mtk-tphy.c:296 struct member 'slew_ref_clock_mhz' not described in 'mtk_phy_pdata' Link: https://patch.msgid.link/20260223071032.408425-1-vkoul@kernel.org Signed-off-by: Vinod Koul --- diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index f6504e0ecd1a7..acf5065295072 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -276,14 +276,14 @@ enum mtk_phy_version { }; /** - * mtk_phy_pdata - SoC specific platform data + * struct mtk_phy_pdata - SoC specific platform data * @avoid_rx_sen_degradation: Avoid TX Sensitivity level degradation (MT6795/8173 only) * @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 48MHz PLL from * fractional mode to integer to output 26MHz for U2PHY * @sw_efuse_supported: Switches off eFuse auto-load from PHY and applies values * read from different nvmem (usually different eFuse array) * that is pointed at in the device tree node for this PHY - * @slew_ref_clk_mhz: Default reference clock (in MHz) for slew rate calibration + * @slew_ref_clock_mhz: Default reference clock (in MHz) for slew rate calibration * @slew_rate_coefficient: Coefficient for slew rate calibration * @version: PHY IP Version */