From: Izhar Ameer Shaikh <izhar.ameer.shaikh@xilinx.com>
Date: Fri, 14 Jun 2019 19:47:25 +0000 (-0700)
Subject: arm64: versal: Add frequency scaling support
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8e841bd8280d33b78d8e330737564cc17834855e;p=thirdparty%2Fu-boot.git

arm64: versal: Add frequency scaling support

Add CPU Operating Performance Points (OPP) table and ACPU clock for
cpu0. This is needed by cpufreq driver to manage CPU frequency scaling.

e.g.
In the design if we have 72 as the multiplier and 33.333 MHz as the ref
frequency:

pllfreq = 33.33*72 = 2399.76 MHz
It is the pll output.

Now, with the integral divisors we can achieve:

2399.76 / 2 = 1199.88 MHz
2399.76 / 3 = 799.92 MHz
2399.76 / 4 = 599.94 MHz
2399.76 / 5 = 479.95 MHz
2399.76 / 6 = 399.96 MHz
2399.76 / 7 = 342.82 MHz
etc.

Therefore, some of them are chosen to be in the device tree.

For more reference: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841831/CPU+frequency+scaling

Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/versal-clk.dtsi b/arch/arm/dts/versal-clk.dtsi
index 8363a089b74..0c04d9af683 100644
--- a/arch/arm/dts/versal-clk.dtsi
+++ b/arch/arm/dts/versal-clk.dtsi
@@ -80,6 +80,10 @@
 	};
 };
 
+&cpu0 {
+	clocks = <&versal_clk ACPU>;
+};
+
 &can0 {
 	clocks = <&versal_clk CAN0_REF>, <&versal_clk LPD_LSBUS>;
 	power-domains = <&versal_firmware PD_CAN_FD_0>;
diff --git a/arch/arm/dts/versal.dtsi b/arch/arm/dts/versal.dtsi
index 393271cabbf..54647924ca2 100644
--- a/arch/arm/dts/versal.dtsi
+++ b/arch/arm/dts/versal.dtsi
@@ -23,6 +23,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
+			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0>;
 		};
 
@@ -30,10 +31,36 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
+			operating-points-v2 = <&cpu_opp_table>;
 			reg = <1>;
 		};
 	};
 
+	cpu_opp_table: cpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 {
+			opp-hz = /bits/ 64 <1199999988>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <599999994>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <399999996>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <299999997>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+	};
+
 	dcc: dcc {
 		compatible = "arm,dcc";
 		status = "disabled";