From: Greg Kroah-Hartman Date: Sat, 31 Oct 2020 11:16:52 +0000 (+0100) Subject: 5.8-stable patches X-Git-Tag: v5.4.74~8 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=8ed3fc8038f38f2d3c46213fe9027e05a986305b;p=thirdparty%2Fkernel%2Fstable-queue.git 5.8-stable patches added patches: misc-rtsx-do-not-setting-oc_power_down-reg-in-rtsx_pci_init_ocp.patch openrisc-fix-issue-with-get_user-for-64-bit-values.patch phy-marvell-comphy-convert-internal-smcc-firmware-return-codes-to-errno.patch --- diff --git a/queue-5.8/misc-rtsx-do-not-setting-oc_power_down-reg-in-rtsx_pci_init_ocp.patch b/queue-5.8/misc-rtsx-do-not-setting-oc_power_down-reg-in-rtsx_pci_init_ocp.patch new file mode 100644 index 00000000000..83caed8547b --- /dev/null +++ b/queue-5.8/misc-rtsx-do-not-setting-oc_power_down-reg-in-rtsx_pci_init_ocp.patch @@ -0,0 +1,34 @@ +From 551b6729578a8981c46af964c10bf7d5d9ddca83 Mon Sep 17 00:00:00 2001 +From: Ricky Wu +Date: Mon, 24 Aug 2020 11:00:06 +0800 +Subject: misc: rtsx: do not setting OC_POWER_DOWN reg in rtsx_pci_init_ocp() + +From: Ricky Wu + +commit 551b6729578a8981c46af964c10bf7d5d9ddca83 upstream. + +this power saving action in rtsx_pci_init_ocp() cause INTEL-NUC6 platform +missing card reader + +Signed-off-by: Ricky Wu +Link: https://lore.kernel.org/r/20200824030006.30033-1-ricky_wu@realtek.com +Cc: Chris Clayton +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/misc/cardreader/rtsx_pcr.c | 4 ---- + 1 file changed, 4 deletions(-) + +--- a/drivers/misc/cardreader/rtsx_pcr.c ++++ b/drivers/misc/cardreader/rtsx_pcr.c +@@ -1172,10 +1172,6 @@ void rtsx_pci_init_ocp(struct rtsx_pcr * + rtsx_pci_write_register(pcr, REG_OCPGLITCH, + SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch); + rtsx_pci_enable_ocp(pcr); +- } else { +- /* OC power down */ +- rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, +- OC_POWER_DOWN); + } + } + } diff --git a/queue-5.8/openrisc-fix-issue-with-get_user-for-64-bit-values.patch b/queue-5.8/openrisc-fix-issue-with-get_user-for-64-bit-values.patch new file mode 100644 index 00000000000..7819689d2eb --- /dev/null +++ b/queue-5.8/openrisc-fix-issue-with-get_user-for-64-bit-values.patch @@ -0,0 +1,122 @@ +From d877322bc1adcab9850732275670409e8bcca4c4 Mon Sep 17 00:00:00 2001 +From: Stafford Horne +Date: Thu, 3 Sep 2020 05:54:40 +0900 +Subject: openrisc: Fix issue with get_user for 64-bit values + +From: Stafford Horne + +commit d877322bc1adcab9850732275670409e8bcca4c4 upstream. + +A build failure was raised by kbuild with the following error. + + drivers/android/binder.c: Assembler messages: + drivers/android/binder.c:3861: Error: unrecognized keyword/register name `l.lwz ?ap,4(r24)' + drivers/android/binder.c:3866: Error: unrecognized keyword/register name `l.addi ?ap,r0,0' + +The issue is with 64-bit get_user() calls on openrisc. I traced this to +a problem where in the internally in the get_user macros there is a cast +to long __gu_val this causes GCC to think the get_user call is 32-bit. +This binder code is really long and GCC allocates register r30, which +triggers the issue. The 64-bit get_user asm tries to get the 64-bit pair +register, which for r30 overflows the general register names and returns +the dummy register ?ap. + +The fix here is to move the temporary variables into the asm macros. We +use a 32-bit __gu_tmp for 32-bit and smaller macro and a 64-bit tmp in +the 64-bit macro. The cast in the 64-bit macro has a trick of casting +through __typeof__((x)-(x)) which avoids the below warning. This was +barrowed from riscv. + + arch/openrisc/include/asm/uaccess.h:240:8: warning: cast to pointer from integer of different size + +I tested this in a small unit test to check reading between 64-bit and +32-bit pointers to 64-bit and 32-bit values in all combinations. Also I +ran make C=1 to confirm no new sparse warnings came up. It all looks +clean to me. + +Link: https://lore.kernel.org/lkml/202008200453.ohnhqkjQ%25lkp@intel.com/ +Signed-off-by: Stafford Horne +Reviewed-by: Luc Van Oostenryck +Signed-off-by: Greg Kroah-Hartman + + +--- + arch/openrisc/include/asm/uaccess.h | 35 ++++++++++++++++++++++------------- + 1 file changed, 22 insertions(+), 13 deletions(-) + +--- a/arch/openrisc/include/asm/uaccess.h ++++ b/arch/openrisc/include/asm/uaccess.h +@@ -164,19 +164,19 @@ struct __large_struct { + + #define __get_user_nocheck(x, ptr, size) \ + ({ \ +- long __gu_err, __gu_val; \ +- __get_user_size(__gu_val, (ptr), (size), __gu_err); \ +- (x) = (__force __typeof__(*(ptr)))__gu_val; \ ++ long __gu_err; \ ++ __get_user_size((x), (ptr), (size), __gu_err); \ + __gu_err; \ + }) + + #define __get_user_check(x, ptr, size) \ + ({ \ +- long __gu_err = -EFAULT, __gu_val = 0; \ +- const __typeof__(*(ptr)) * __gu_addr = (ptr); \ +- if (access_ok(__gu_addr, size)) \ +- __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ +- (x) = (__force __typeof__(*(ptr)))__gu_val; \ ++ long __gu_err = -EFAULT; \ ++ const __typeof__(*(ptr)) *__gu_addr = (ptr); \ ++ if (access_ok(__gu_addr, size)) \ ++ __get_user_size((x), __gu_addr, (size), __gu_err); \ ++ else \ ++ (x) = (__typeof__(*(ptr))) 0; \ + __gu_err; \ + }) + +@@ -190,11 +190,13 @@ do { \ + case 2: __get_user_asm(x, ptr, retval, "l.lhz"); break; \ + case 4: __get_user_asm(x, ptr, retval, "l.lwz"); break; \ + case 8: __get_user_asm2(x, ptr, retval); break; \ +- default: (x) = __get_user_bad(); \ ++ default: (x) = (__typeof__(*(ptr)))__get_user_bad(); \ + } \ + } while (0) + + #define __get_user_asm(x, addr, err, op) \ ++{ \ ++ unsigned long __gu_tmp; \ + __asm__ __volatile__( \ + "1: "op" %1,0(%2)\n" \ + "2:\n" \ +@@ -208,10 +210,14 @@ do { \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".previous" \ +- : "=r"(err), "=r"(x) \ +- : "r"(addr), "i"(-EFAULT), "0"(err)) ++ : "=r"(err), "=r"(__gu_tmp) \ ++ : "r"(addr), "i"(-EFAULT), "0"(err)); \ ++ (x) = (__typeof__(*(addr)))__gu_tmp; \ ++} + + #define __get_user_asm2(x, addr, err) \ ++{ \ ++ unsigned long long __gu_tmp; \ + __asm__ __volatile__( \ + "1: l.lwz %1,0(%2)\n" \ + "2: l.lwz %H1,4(%2)\n" \ +@@ -228,8 +234,11 @@ do { \ + " .long 1b,4b\n" \ + " .long 2b,4b\n" \ + ".previous" \ +- : "=r"(err), "=&r"(x) \ +- : "r"(addr), "i"(-EFAULT), "0"(err)) ++ : "=r"(err), "=&r"(__gu_tmp) \ ++ : "r"(addr), "i"(-EFAULT), "0"(err)); \ ++ (x) = (__typeof__(*(addr)))( \ ++ (__typeof__((x)-(x)))__gu_tmp); \ ++} + + /* more complex routines */ + diff --git a/queue-5.8/phy-marvell-comphy-convert-internal-smcc-firmware-return-codes-to-errno.patch b/queue-5.8/phy-marvell-comphy-convert-internal-smcc-firmware-return-codes-to-errno.patch new file mode 100644 index 00000000000..38fccc4e7d3 --- /dev/null +++ b/queue-5.8/phy-marvell-comphy-convert-internal-smcc-firmware-return-codes-to-errno.patch @@ -0,0 +1,111 @@ +From ea17a0f153af2cd890e4ce517130dcccaa428c13 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Wed, 2 Sep 2020 16:43:43 +0200 +Subject: phy: marvell: comphy: Convert internal SMCC firmware return codes to errno +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit ea17a0f153af2cd890e4ce517130dcccaa428c13 upstream. + +Driver ->power_on and ->power_off callbacks leaks internal SMCC firmware +return codes to phy caller. This patch converts SMCC error codes to +standard linux errno codes. Include file linux/arm-smccc.h already provides +defines for SMCC error codes, so use them instead of custom driver defines. +Note that return value is signed 32bit, but stored in unsigned long type +with zero padding. + +Tested-by: Tomasz Maciej Nowak +Link: https://lore.kernel.org/r/20200902144344.16684-2-pali@kernel.org +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Rob Herring +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 14 +++++++++++--- + drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 14 +++++++++++--- + 2 files changed, 22 insertions(+), 6 deletions(-) + +--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c ++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c +@@ -26,7 +26,6 @@ + #define COMPHY_SIP_POWER_ON 0x82000001 + #define COMPHY_SIP_POWER_OFF 0x82000002 + #define COMPHY_SIP_PLL_LOCK 0x82000003 +-#define COMPHY_FW_NOT_SUPPORTED (-1) + + #define COMPHY_FW_MODE_SATA 0x1 + #define COMPHY_FW_MODE_SGMII 0x2 +@@ -112,10 +111,19 @@ static int mvebu_a3700_comphy_smc(unsign + unsigned long mode) + { + struct arm_smccc_res res; ++ s32 ret; + + arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); ++ ret = res.a0; + +- return res.a0; ++ switch (ret) { ++ case SMCCC_RET_SUCCESS: ++ return 0; ++ case SMCCC_RET_NOT_SUPPORTED: ++ return -EOPNOTSUPP; ++ default: ++ return -EINVAL; ++ } + } + + static int mvebu_a3700_comphy_get_fw_mode(int lane, int port, +@@ -220,7 +228,7 @@ static int mvebu_a3700_comphy_power_on(s + } + + ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param); +- if (ret == COMPHY_FW_NOT_SUPPORTED) ++ if (ret == -EOPNOTSUPP) + dev_err(lane->dev, + "unsupported SMC call, try updating your firmware\n"); + +--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c ++++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c +@@ -123,7 +123,6 @@ + + #define COMPHY_SIP_POWER_ON 0x82000001 + #define COMPHY_SIP_POWER_OFF 0x82000002 +-#define COMPHY_FW_NOT_SUPPORTED (-1) + + /* + * A lane is described by the following bitfields: +@@ -273,10 +272,19 @@ static int mvebu_comphy_smc(unsigned lon + unsigned long lane, unsigned long mode) + { + struct arm_smccc_res res; ++ s32 ret; + + arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); ++ ret = res.a0; + +- return res.a0; ++ switch (ret) { ++ case SMCCC_RET_SUCCESS: ++ return 0; ++ case SMCCC_RET_NOT_SUPPORTED: ++ return -EOPNOTSUPP; ++ default: ++ return -EINVAL; ++ } + } + + static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port, +@@ -819,7 +827,7 @@ static int mvebu_comphy_power_on(struct + if (!ret) + return ret; + +- if (ret == COMPHY_FW_NOT_SUPPORTED) ++ if (ret == -EOPNOTSUPP) + dev_err(priv->dev, + "unsupported SMC call, try updating your firmware\n"); + diff --git a/queue-5.8/series b/queue-5.8/series index 330da012e3d..a8812d2eb00 100644 --- a/queue-5.8/series +++ b/queue-5.8/series @@ -65,3 +65,6 @@ serial-pl011-fix-lockdep-splat-when-handling-magic-sysrq-interrupt.patch pm-runtime-fix-timer_expires-data-type-on-32-bit-arches.patch ata-sata_rcar-fix-dma-boundary-mask.patch xen-gntdev.c-mark-pages-as-dirty.patch +openrisc-fix-issue-with-get_user-for-64-bit-values.patch +misc-rtsx-do-not-setting-oc_power_down-reg-in-rtsx_pci_init_ocp.patch +phy-marvell-comphy-convert-internal-smcc-firmware-return-codes-to-errno.patch