From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Mon, 10 Nov 2014 05:58:27 +0000 (+0900)
Subject: 3.10-stable patches
X-Git-Tag: v3.10.60~27
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=90ee668a4c6d69946d7017e7314086fce597feae;p=thirdparty%2Fkernel%2Fstable-queue.git

3.10-stable patches

added patches:
	x86-apic-handle-a-bad-tsc-more-gracefully.patch
---

diff --git a/queue-3.10/series b/queue-3.10/series
index eab2ac9efe3..e55b4ed30ca 100644
--- a/queue-3.10/series
+++ b/queue-3.10/series
@@ -107,3 +107,4 @@ tty-fix-high-cpu-load-if-tty-is-unreleaseable.patch
 pm-sleep-fix-recovery-during-resuming-from-hibernation.patch
 mac80211-fix-typo-in-starting-baserate-for-rts_cts_rate_idx.patch
 posix-timers-fix-stack-info-leak-in-timer_create.patch
+x86-apic-handle-a-bad-tsc-more-gracefully.patch
diff --git a/queue-3.10/x86-apic-handle-a-bad-tsc-more-gracefully.patch b/queue-3.10/x86-apic-handle-a-bad-tsc-more-gracefully.patch
new file mode 100644
index 00000000000..a6e7c959519
--- /dev/null
+++ b/queue-3.10/x86-apic-handle-a-bad-tsc-more-gracefully.patch
@@ -0,0 +1,74 @@
+From b47dcbdc5161d3d5756f430191e2840d9b855492 Mon Sep 17 00:00:00 2001
+From: Andy Lutomirski <luto@amacapital.net>
+Date: Wed, 15 Oct 2014 10:12:07 -0700
+Subject: x86, apic: Handle a bad TSC more gracefully
+
+From: Andy Lutomirski <luto@amacapital.net>
+
+commit b47dcbdc5161d3d5756f430191e2840d9b855492 upstream.
+
+If the TSC is unusable or disabled, then this patch fixes:
+
+ - Confusion while trying to clear old APIC interrupts.
+ - Division by zero and incorrect programming of the TSC deadline
+   timer.
+
+This fixes boot if the CPU has a TSC deadline timer but a missing or
+broken TSC.  The failure to boot can be observed with qemu using
+-cpu qemu64,-tsc,+tsc-deadline
+
+This also happens to me in nested KVM for unknown reasons.
+With this patch, I can boot cleanly (although without a TSC).
+
+Signed-off-by: Andy Lutomirski <luto@amacapital.net>
+Cc: Bandan Das <bsd@redhat.com>
+Link: http://lkml.kernel.org/r/e2fa274e498c33988efac0ba8b7e3120f7f92d78.1413393027.git.luto@amacapital.net
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/apic/apic.c |    4 ++--
+ arch/x86/kernel/tsc.c       |    5 ++++-
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+--- a/arch/x86/kernel/apic/apic.c
++++ b/arch/x86/kernel/apic/apic.c
+@@ -1263,7 +1263,7 @@ void __cpuinit setup_local_APIC(void)
+ 	unsigned int value, queued;
+ 	int i, j, acked = 0;
+ 	unsigned long long tsc = 0, ntsc;
+-	long long max_loops = cpu_khz;
++	long long max_loops = cpu_khz ? cpu_khz : 1000000;
+ 
+ 	if (cpu_has_tsc)
+ 		rdtscll(tsc);
+@@ -1360,7 +1360,7 @@ void __cpuinit setup_local_APIC(void)
+ 			break;
+ 		}
+ 		if (queued) {
+-			if (cpu_has_tsc) {
++			if (cpu_has_tsc && cpu_khz) {
+ 				rdtscll(ntsc);
+ 				max_loops = (cpu_khz << 10) - (ntsc - tsc);
+ 			} else
+--- a/arch/x86/kernel/tsc.c
++++ b/arch/x86/kernel/tsc.c
+@@ -968,14 +968,17 @@ void __init tsc_init(void)
+ 
+ 	x86_init.timers.tsc_pre_init();
+ 
+-	if (!cpu_has_tsc)
++	if (!cpu_has_tsc) {
++		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
+ 		return;
++	}
+ 
+ 	tsc_khz = x86_platform.calibrate_tsc();
+ 	cpu_khz = tsc_khz;
+ 
+ 	if (!tsc_khz) {
+ 		mark_tsc_unstable("could not calculate TSC khz");
++		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
+ 		return;
+ 	}
+