From: Dinh Nguyen <dinguyen@kernel.org>
Date: Fri, 31 Jul 2020 15:26:40 +0000 (-0500)
Subject: ARM: dts: socfpga: fix register entry for timer3 on Arria10
X-Git-Tag: v5.8.10~170
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=91dff93e5584278c23b1e787435210e94369de75;p=thirdparty%2Fkernel%2Fstable.git

ARM: dts: socfpga: fix register entry for timer3 on Arria10

[ Upstream commit 0ff5a4812be4ebd4782bbb555d369636eea164f7 ]

Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 8f614c4b0e3eb..9c71472c237bd 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -819,7 +819,7 @@
 		timer3: timer3@ffd00100 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
-			reg = <0xffd01000 0x100>;
+			reg = <0xffd00100 0x100>;
 			clocks = <&l4_sys_free_clk>;
 			clock-names = "timer";
 			resets = <&rst L4SYSTIMER1_RESET>;