From: Greg Kroah-Hartman Date: Mon, 16 Nov 2020 17:30:08 +0000 (+0100) Subject: 5.9-stable patches X-Git-Tag: v4.4.244~38 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=93709df55aea4065246061d8aa7f222d6df0cf52;p=thirdparty%2Fkernel%2Fstable-queue.git 5.9-stable patches added patches: don-t-dump-the-threads-that-had-been-already-exiting-when-zapped.patch drm-amd-display-add-missing-pflip-irq.patch drm-gma500-fix-out-of-bounds-access-to-struct-drm_device.vblank.patch drm-i915-correctly-set-sfc-capability-for-video-engines.patch gpio-pcie-idio-24-enable-pex8311-interrupts.patch gpio-pcie-idio-24-fix-irq-enable-register-value.patch gpio-pcie-idio-24-fix-irq-mask-when-masking.patch gpio-sifive-fix-sifive-gpio-probe.patch hwmon-amd_energy-modify-the-visibility-of-the-counters.patch io_uring-round-up-cq-size-before-comparing-with-rounded-sq-size.patch mmc-renesas_sdhi_core-add-missing-tmio_mmc_host_free-at-remove.patch mmc-sdhci-of-esdhc-handle-pulse-width-detection-erratum-for-more-socs.patch nfsv4.2-fix-failure-to-unregister-shrinker.patch pinctrl-amd-fix-incorrect-way-to-disable-debounce-filter.patch pinctrl-amd-use-higher-precision-for-512-rtcclk.patch selinux-fix-error-return-code-in-sel_ib_pkey_sid_slow.patch --- diff --git a/queue-5.9/don-t-dump-the-threads-that-had-been-already-exiting-when-zapped.patch b/queue-5.9/don-t-dump-the-threads-that-had-been-already-exiting-when-zapped.patch new file mode 100644 index 00000000000..049276faf8e --- /dev/null +++ b/queue-5.9/don-t-dump-the-threads-that-had-been-already-exiting-when-zapped.patch @@ -0,0 +1,72 @@ +From 77f6ab8b7768cf5e6bdd0e72499270a0671506ee Mon Sep 17 00:00:00 2001 +From: Al Viro +Date: Wed, 28 Oct 2020 16:39:49 -0400 +Subject: don't dump the threads that had been already exiting when zapped. + +From: Al Viro + +commit 77f6ab8b7768cf5e6bdd0e72499270a0671506ee upstream. + +Coredump logics needs to report not only the registers of the dumping +thread, but (since 2.5.43) those of other threads getting killed. + +Doing that might require extra state saved on the stack in asm glue at +kernel entry; signal delivery logics does that (we need to be able to +save sigcontext there, at the very least) and so does seccomp. + +That covers all callers of do_coredump(). Secondary threads get hit with +SIGKILL and caught as soon as they reach exit_mm(), which normally happens +in signal delivery, so those are also fine most of the time. Unfortunately, +it is possible to end up with secondary zapped when it has already entered +exit(2) (or, worse yet, is oopsing). In those cases we reach exit_mm() +when mm->core_state is already set, but the stack contents is not what +we would have in signal delivery. + +At least on two architectures (alpha and m68k) it leads to infoleaks - we +end up with a chunk of kernel stack written into coredump, with the contents +consisting of normal C stack frames of the call chain leading to exit_mm() +instead of the expected copy of userland registers. In case of alpha we +leak 312 bytes of stack. Other architectures (including the regset-using +ones) might have similar problems - the normal user of regsets is ptrace +and the state of tracee at the time of such calls is special in the same +way signal delivery is. + +Note that had the zapper gotten to the exiting thread slightly later, +it wouldn't have been included into coredump anyway - we skip the threads +that have already cleared their ->mm. So let's pretend that zapper always +loses the race. IOW, have exit_mm() only insert into the dumper list if +we'd gotten there from handling a fatal signal[*] + +As the result, the callers of do_exit() that have *not* gone through get_signal() +are not seen by coredump logics as secondary threads. Which excludes voluntary +exit()/oopsen/traps/etc. The dumper thread itself is unaffected by that, +so seccomp is fine. + +[*] originally I intended to add a new flag in tsk->flags, but ebiederman pointed +out that PF_SIGNALED is already doing just what we need. + +Cc: stable@vger.kernel.org +Fixes: d89f3847def4 ("[PATCH] thread-aware coredumps, 2.5.43-C3") +History-tree: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git +Acked-by: "Eric W. Biederman" +Signed-off-by: Al Viro +Signed-off-by: Greg Kroah-Hartman + +--- + kernel/exit.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/kernel/exit.c ++++ b/kernel/exit.c +@@ -454,7 +454,10 @@ static void exit_mm(void) + mmap_read_unlock(mm); + + self.task = current; +- self.next = xchg(&core_state->dumper.next, &self); ++ if (self.task->flags & PF_SIGNALED) ++ self.next = xchg(&core_state->dumper.next, &self); ++ else ++ self.task = NULL; + /* + * Implies mb(), the result of xchg() must be visible + * to core_state->dumper. diff --git a/queue-5.9/drm-amd-display-add-missing-pflip-irq.patch b/queue-5.9/drm-amd-display-add-missing-pflip-irq.patch new file mode 100644 index 00000000000..87c1e2c884e --- /dev/null +++ b/queue-5.9/drm-amd-display-add-missing-pflip-irq.patch @@ -0,0 +1,36 @@ +From a422490a595600659664901b609aacccdbba4a5f Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha +Date: Fri, 16 Oct 2020 14:57:23 -0400 +Subject: drm/amd/display: Add missing pflip irq + +From: Bhawanpreet Lakha + +commit a422490a595600659664901b609aacccdbba4a5f upstream. + +If we have more than 4 displays we will run +into dummy irq calls or flip timout issues. + +Signed-off-by: Bhawanpreet Lakha +Reviewed-by: Charlene Liu +Acked-by: Qingqing Zhuo +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 5.9.x +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c ++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c +@@ -306,8 +306,8 @@ irq_source_info_dcn30[DAL_IRQ_SOURCES_NU + pflip_int_entry(1), + pflip_int_entry(2), + pflip_int_entry(3), +- [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), +- [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), ++ pflip_int_entry(4), ++ pflip_int_entry(5), + [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), + gpio_pad_int_entry(0), + gpio_pad_int_entry(1), diff --git a/queue-5.9/drm-gma500-fix-out-of-bounds-access-to-struct-drm_device.vblank.patch b/queue-5.9/drm-gma500-fix-out-of-bounds-access-to-struct-drm_device.vblank.patch new file mode 100644 index 00000000000..0d2f06a134f --- /dev/null +++ b/queue-5.9/drm-gma500-fix-out-of-bounds-access-to-struct-drm_device.vblank.patch @@ -0,0 +1,120 @@ +From 06ad8d339524bf94b89859047822c31df6ace239 Mon Sep 17 00:00:00 2001 +From: Thomas Zimmermann +Date: Thu, 5 Nov 2020 20:02:56 +0100 +Subject: drm/gma500: Fix out-of-bounds access to struct drm_device.vblank[] + +From: Thomas Zimmermann + +commit 06ad8d339524bf94b89859047822c31df6ace239 upstream. + +The gma500 driver expects 3 pipelines in several it's IRQ functions. +Accessing struct drm_device.vblank[], this fails with devices that only +have 2 pipelines. An example KASAN report is shown below. + + [ 62.267688] ================================================================== + [ 62.268856] BUG: KASAN: slab-out-of-bounds in psb_irq_postinstall+0x250/0x3c0 [gma500_gfx] + [ 62.269450] Read of size 1 at addr ffff8880012bc6d0 by task systemd-udevd/285 + [ 62.269949] + [ 62.270192] CPU: 0 PID: 285 Comm: systemd-udevd Tainted: G E 5.10.0-rc1-1-default+ #572 + [ 62.270807] Hardware name: /DN2800MT, BIOS MTCDT10N.86A.0164.2012.1213.1024 12/13/2012 + [ 62.271366] Call Trace: + [ 62.271705] dump_stack+0xae/0xe5 + [ 62.272180] print_address_description.constprop.0+0x17/0xf0 + [ 62.272987] ? psb_irq_postinstall+0x250/0x3c0 [gma500_gfx] + [ 62.273474] __kasan_report.cold+0x20/0x38 + [ 62.273989] ? psb_irq_postinstall+0x250/0x3c0 [gma500_gfx] + [ 62.274460] kasan_report+0x3a/0x50 + [ 62.274891] psb_irq_postinstall+0x250/0x3c0 [gma500_gfx] + [ 62.275380] drm_irq_install+0x131/0x1f0 + <...> + [ 62.300751] Allocated by task 285: + [ 62.301223] kasan_save_stack+0x1b/0x40 + [ 62.301731] __kasan_kmalloc.constprop.0+0xbf/0xd0 + [ 62.302293] drmm_kmalloc+0x55/0x100 + [ 62.302773] drm_vblank_init+0x77/0x210 + +Resolve the issue by only handling vblank entries up to the number of +CRTCs. + +I'm adding a Fixes tag for reference, although the bug has been present +since the driver's initial commit. + +Signed-off-by: Thomas Zimmermann +Reviewed-by: Daniel Vetter +Fixes: 5c49fd3aa0ab ("gma500: Add the core DRM files and headers") +Cc: Alan Cox +Cc: Dave Airlie +Cc: Patrik Jakobsson +Cc: dri-devel@lists.freedesktop.org +Cc: stable@vger.kernel.org#v3.3+ +Link: https://patchwork.freedesktop.org/patch/msgid/20201105190256.3893-1-tzimmermann@suse.de +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/gma500/psb_irq.c | 34 ++++++++++++---------------------- + 1 file changed, 12 insertions(+), 22 deletions(-) + +--- a/drivers/gpu/drm/gma500/psb_irq.c ++++ b/drivers/gpu/drm/gma500/psb_irq.c +@@ -347,6 +347,7 @@ int psb_irq_postinstall(struct drm_devic + { + struct drm_psb_private *dev_priv = dev->dev_private; + unsigned long irqflags; ++ unsigned int i; + + spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); + +@@ -359,20 +360,12 @@ int psb_irq_postinstall(struct drm_devic + PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); + PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); + +- if (dev->vblank[0].enabled) +- psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); +- else +- psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); +- +- if (dev->vblank[1].enabled) +- psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); +- else +- psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); +- +- if (dev->vblank[2].enabled) +- psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); +- else +- psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); ++ for (i = 0; i < dev->num_crtcs; ++i) { ++ if (dev->vblank[i].enabled) ++ psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); ++ else ++ psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); ++ } + + if (dev_priv->ops->hotplug_enable) + dev_priv->ops->hotplug_enable(dev, true); +@@ -385,6 +378,7 @@ void psb_irq_uninstall(struct drm_device + { + struct drm_psb_private *dev_priv = dev->dev_private; + unsigned long irqflags; ++ unsigned int i; + + spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); + +@@ -393,14 +387,10 @@ void psb_irq_uninstall(struct drm_device + + PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); + +- if (dev->vblank[0].enabled) +- psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); +- +- if (dev->vblank[1].enabled) +- psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); +- +- if (dev->vblank[2].enabled) +- psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); ++ for (i = 0; i < dev->num_crtcs; ++i) { ++ if (dev->vblank[i].enabled) ++ psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); ++ } + + dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG | + _PSB_IRQ_MSVDX_FLAG | diff --git a/queue-5.9/drm-i915-correctly-set-sfc-capability-for-video-engines.patch b/queue-5.9/drm-i915-correctly-set-sfc-capability-for-video-engines.patch new file mode 100644 index 00000000000..cde3b41381c --- /dev/null +++ b/queue-5.9/drm-i915-correctly-set-sfc-capability-for-video-engines.patch @@ -0,0 +1,41 @@ +From 5ce6861d36ed5207aff9e5eead4c7cc38a986586 Mon Sep 17 00:00:00 2001 +From: Venkata Sandeep Dhanalakota +Date: Thu, 5 Nov 2020 17:18:42 -0800 +Subject: drm/i915: Correctly set SFC capability for video engines + +From: Venkata Sandeep Dhanalakota + +commit 5ce6861d36ed5207aff9e5eead4c7cc38a986586 upstream. + +SFC capability of video engines is not set correctly because i915 +is testing for incorrect bits. + +Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query") +Cc: Matt Roper +Cc: Tvrtko Ursulin +Signed-off-by: Venkata Sandeep Dhanalakota +Signed-off-by: Daniele Ceraolo Spurio +Reviewed-by: Tvrtko Ursulin +Cc: # v5.3+ +Signed-off-by: Chris Wilson +Link: https://patchwork.freedesktop.org/patch/msgid/20201106011842.36203-1-daniele.ceraolospurio@intel.com +(cherry picked from commit ad18fa0f5f052046cad96fee762b5c64f42dd86a) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c +@@ -370,7 +370,8 @@ static void __setup_engine_capabilities( + * instances. + */ + if ((INTEL_GEN(i915) >= 11 && +- engine->gt->info.vdbox_sfc_access & engine->mask) || ++ (engine->gt->info.vdbox_sfc_access & ++ BIT(engine->instance))) || + (INTEL_GEN(i915) >= 9 && engine->instance == 0)) + engine->uabi_capabilities |= + I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; diff --git a/queue-5.9/gpio-pcie-idio-24-enable-pex8311-interrupts.patch b/queue-5.9/gpio-pcie-idio-24-enable-pex8311-interrupts.patch new file mode 100644 index 00000000000..e20be96c400 --- /dev/null +++ b/queue-5.9/gpio-pcie-idio-24-enable-pex8311-interrupts.patch @@ -0,0 +1,117 @@ +From 10a2f11d3c9e48363c729419e0f0530dea76e4fe Mon Sep 17 00:00:00 2001 +From: Arnaud de Turckheim +Date: Wed, 4 Nov 2020 16:24:55 +0100 +Subject: gpio: pcie-idio-24: Enable PEX8311 interrupts + +From: Arnaud de Turckheim + +commit 10a2f11d3c9e48363c729419e0f0530dea76e4fe upstream. + +This enables the PEX8311 internal PCI wire interrupt and the PEX8311 +local interrupt input so the local interrupts are forwarded to the PCI. + +Fixes: 585562046628 ("gpio: Add GPIO support for the ACCES PCIe-IDIO-24 family") +Cc: stable@vger.kernel.org +Signed-off-by: Arnaud de Turckheim +Reviewed-by: William Breathitt Gray +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpio/gpio-pcie-idio-24.c | 52 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 51 insertions(+), 1 deletion(-) + +--- a/drivers/gpio/gpio-pcie-idio-24.c ++++ b/drivers/gpio/gpio-pcie-idio-24.c +@@ -28,6 +28,47 @@ + #include + #include + ++/* ++ * PLX PEX8311 PCI LCS_INTCSR Interrupt Control/Status ++ * ++ * Bit: Description ++ * 0: Enable Interrupt Sources (Bit 0) ++ * 1: Enable Interrupt Sources (Bit 1) ++ * 2: Generate Internal PCI Bus Internal SERR# Interrupt ++ * 3: Mailbox Interrupt Enable ++ * 4: Power Management Interrupt Enable ++ * 5: Power Management Interrupt ++ * 6: Slave Read Local Data Parity Check Error Enable ++ * 7: Slave Read Local Data Parity Check Error Status ++ * 8: Internal PCI Wire Interrupt Enable ++ * 9: PCI Express Doorbell Interrupt Enable ++ * 10: PCI Abort Interrupt Enable ++ * 11: Local Interrupt Input Enable ++ * 12: Retry Abort Enable ++ * 13: PCI Express Doorbell Interrupt Active ++ * 14: PCI Abort Interrupt Active ++ * 15: Local Interrupt Input Active ++ * 16: Local Interrupt Output Enable ++ * 17: Local Doorbell Interrupt Enable ++ * 18: DMA Channel 0 Interrupt Enable ++ * 19: DMA Channel 1 Interrupt Enable ++ * 20: Local Doorbell Interrupt Active ++ * 21: DMA Channel 0 Interrupt Active ++ * 22: DMA Channel 1 Interrupt Active ++ * 23: Built-In Self-Test (BIST) Interrupt Active ++ * 24: Direct Master was the Bus Master during a Master or Target Abort ++ * 25: DMA Channel 0 was the Bus Master during a Master or Target Abort ++ * 26: DMA Channel 1 was the Bus Master during a Master or Target Abort ++ * 27: Target Abort after internal 256 consecutive Master Retrys ++ * 28: PCI Bus wrote data to LCS_MBOX0 ++ * 29: PCI Bus wrote data to LCS_MBOX1 ++ * 30: PCI Bus wrote data to LCS_MBOX2 ++ * 31: PCI Bus wrote data to LCS_MBOX3 ++ */ ++#define PLX_PEX8311_PCI_LCS_INTCSR 0x68 ++#define INTCSR_INTERNAL_PCI_WIRE BIT(8) ++#define INTCSR_LOCAL_INPUT BIT(11) ++ + /** + * struct idio_24_gpio_reg - GPIO device registers structure + * @out0_7: Read: FET Outputs 0-7 +@@ -92,6 +133,7 @@ struct idio_24_gpio_reg { + struct idio_24_gpio { + struct gpio_chip chip; + raw_spinlock_t lock; ++ __u8 __iomem *plx; + struct idio_24_gpio_reg __iomem *reg; + unsigned long irq_mask; + }; +@@ -455,6 +497,7 @@ static int idio_24_probe(struct pci_dev + struct device *const dev = &pdev->dev; + struct idio_24_gpio *idio24gpio; + int err; ++ const size_t pci_plx_bar_index = 1; + const size_t pci_bar_index = 2; + const char *const name = pci_name(pdev); + struct gpio_irq_chip *girq; +@@ -469,12 +512,13 @@ static int idio_24_probe(struct pci_dev + return err; + } + +- err = pcim_iomap_regions(pdev, BIT(pci_bar_index), name); ++ err = pcim_iomap_regions(pdev, BIT(pci_plx_bar_index) | BIT(pci_bar_index), name); + if (err) { + dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err); + return err; + } + ++ idio24gpio->plx = pcim_iomap_table(pdev)[pci_plx_bar_index]; + idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index]; + + idio24gpio->chip.label = name; +@@ -504,6 +548,12 @@ static int idio_24_probe(struct pci_dev + + /* Software board reset */ + iowrite8(0, &idio24gpio->reg->soft_reset); ++ /* ++ * enable PLX PEX8311 internal PCI wire interrupt and local interrupt ++ * input ++ */ ++ iowrite8((INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOCAL_INPUT) >> 8, ++ idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1); + + err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio); + if (err) { diff --git a/queue-5.9/gpio-pcie-idio-24-fix-irq-enable-register-value.patch b/queue-5.9/gpio-pcie-idio-24-fix-irq-enable-register-value.patch new file mode 100644 index 00000000000..6a5e58b3042 --- /dev/null +++ b/queue-5.9/gpio-pcie-idio-24-fix-irq-enable-register-value.patch @@ -0,0 +1,56 @@ +From 23a7fdc06ebcc334fa667f0550676b035510b70b Mon Sep 17 00:00:00 2001 +From: Arnaud de Turckheim +Date: Wed, 4 Nov 2020 16:24:54 +0100 +Subject: gpio: pcie-idio-24: Fix IRQ Enable Register value + +From: Arnaud de Turckheim + +commit 23a7fdc06ebcc334fa667f0550676b035510b70b upstream. + +This fixes the COS Enable Register value for enabling/disabling the +corresponding IRQs bank. + +Fixes: 585562046628 ("gpio: Add GPIO support for the ACCES PCIe-IDIO-24 family") +Cc: stable@vger.kernel.org +Signed-off-by: Arnaud de Turckheim +Reviewed-by: William Breathitt Gray +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpio/gpio-pcie-idio-24.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpio/gpio-pcie-idio-24.c ++++ b/drivers/gpio/gpio-pcie-idio-24.c +@@ -334,13 +334,13 @@ static void idio_24_irq_mask(struct irq_ + unsigned long flags; + const unsigned long bit_offset = irqd_to_hwirq(data) - 24; + unsigned char new_irq_mask; +- const unsigned long bank_offset = bit_offset/8 * 8; ++ const unsigned long bank_offset = bit_offset / 8; + unsigned char cos_enable_state; + + raw_spin_lock_irqsave(&idio24gpio->lock, flags); + + idio24gpio->irq_mask &= ~BIT(bit_offset); +- new_irq_mask = idio24gpio->irq_mask >> bank_offset; ++ new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; + + if (!new_irq_mask) { + cos_enable_state = ioread8(&idio24gpio->reg->cos_enable); +@@ -363,12 +363,12 @@ static void idio_24_irq_unmask(struct ir + unsigned long flags; + unsigned char prev_irq_mask; + const unsigned long bit_offset = irqd_to_hwirq(data) - 24; +- const unsigned long bank_offset = bit_offset/8 * 8; ++ const unsigned long bank_offset = bit_offset / 8; + unsigned char cos_enable_state; + + raw_spin_lock_irqsave(&idio24gpio->lock, flags); + +- prev_irq_mask = idio24gpio->irq_mask >> bank_offset; ++ prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; + idio24gpio->irq_mask |= BIT(bit_offset); + + if (!prev_irq_mask) { diff --git a/queue-5.9/gpio-pcie-idio-24-fix-irq-mask-when-masking.patch b/queue-5.9/gpio-pcie-idio-24-fix-irq-mask-when-masking.patch new file mode 100644 index 00000000000..e7a05602d0b --- /dev/null +++ b/queue-5.9/gpio-pcie-idio-24-fix-irq-mask-when-masking.patch @@ -0,0 +1,34 @@ +From d8f270efeac850c569c305dc0baa42ac3d607988 Mon Sep 17 00:00:00 2001 +From: Arnaud de Turckheim +Date: Wed, 4 Nov 2020 16:24:53 +0100 +Subject: gpio: pcie-idio-24: Fix irq mask when masking + +From: Arnaud de Turckheim + +commit d8f270efeac850c569c305dc0baa42ac3d607988 upstream. + +Fix the bitwise operation to remove only the corresponding bit from the +mask. + +Fixes: 585562046628 ("gpio: Add GPIO support for the ACCES PCIe-IDIO-24 family") +Cc: stable@vger.kernel.org +Signed-off-by: Arnaud de Turckheim +Reviewed-by: William Breathitt Gray +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpio/gpio-pcie-idio-24.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpio/gpio-pcie-idio-24.c ++++ b/drivers/gpio/gpio-pcie-idio-24.c +@@ -339,7 +339,7 @@ static void idio_24_irq_mask(struct irq_ + + raw_spin_lock_irqsave(&idio24gpio->lock, flags); + +- idio24gpio->irq_mask &= BIT(bit_offset); ++ idio24gpio->irq_mask &= ~BIT(bit_offset); + new_irq_mask = idio24gpio->irq_mask >> bank_offset; + + if (!new_irq_mask) { diff --git a/queue-5.9/gpio-sifive-fix-sifive-gpio-probe.patch b/queue-5.9/gpio-sifive-fix-sifive-gpio-probe.patch new file mode 100644 index 00000000000..862f7e1ead2 --- /dev/null +++ b/queue-5.9/gpio-sifive-fix-sifive-gpio-probe.patch @@ -0,0 +1,34 @@ +From b72de3ff19fdc4bbe4d4bb3f4483c7e46e00bac3 Mon Sep 17 00:00:00 2001 +From: Damien Le Moal +Date: Sat, 7 Nov 2020 17:13:57 +0900 +Subject: gpio: sifive: Fix SiFive gpio probe + +From: Damien Le Moal + +commit b72de3ff19fdc4bbe4d4bb3f4483c7e46e00bac3 upstream. + +Fix the check on the number of IRQs to allow up to the maximum (32) +instead of only the maximum minus one. + +Fixes: 96868dce644d ("gpio/sifive: Add GPIO driver for SiFive SoCs") +Cc: stable@vger.kernel.org +Signed-off-by: Damien Le Moal +Link: https://lore.kernel.org/r/20201107081420.60325-10-damien.lemoal@wdc.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpio/gpio-sifive.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpio/gpio-sifive.c ++++ b/drivers/gpio/gpio-sifive.c +@@ -183,7 +183,7 @@ static int sifive_gpio_probe(struct plat + return PTR_ERR(chip->regs); + + ngpio = of_irq_count(node); +- if (ngpio >= SIFIVE_GPIO_MAX) { ++ if (ngpio > SIFIVE_GPIO_MAX) { + dev_err(dev, "Too many GPIO interrupts (max=%d)\n", + SIFIVE_GPIO_MAX); + return -ENXIO; diff --git a/queue-5.9/hwmon-amd_energy-modify-the-visibility-of-the-counters.patch b/queue-5.9/hwmon-amd_energy-modify-the-visibility-of-the-counters.patch new file mode 100644 index 00000000000..f6e655e9c0d --- /dev/null +++ b/queue-5.9/hwmon-amd_energy-modify-the-visibility-of-the-counters.patch @@ -0,0 +1,34 @@ +From 60268b0e8258fdea9a3c9f4b51e161c123571db3 Mon Sep 17 00:00:00 2001 +From: Naveen Krishna Chatradhi +Date: Thu, 12 Nov 2020 22:51:59 +0530 +Subject: hwmon: (amd_energy) modify the visibility of the counters + +From: Naveen Krishna Chatradhi + +commit 60268b0e8258fdea9a3c9f4b51e161c123571db3 upstream. + +This patch limits the visibility to owner and groups only for the +energy counters exposed through the hwmon based amd_energy driver. + +Cc: stable@vger.kernel.org +Reviewed-by: Greg Kroah-Hartman +Signed-off-by: Naveen Krishna Chatradhi +Link: https://lore.kernel.org/r/20201112172159.8781-1-nchatrad@amd.com +Signed-off-by: Guenter Roeck +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/hwmon/amd_energy.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwmon/amd_energy.c ++++ b/drivers/hwmon/amd_energy.c +@@ -209,7 +209,7 @@ static umode_t amd_energy_is_visible(con + enum hwmon_sensor_types type, + u32 attr, int channel) + { +- return 0444; ++ return 0440; + } + + static int energy_accumulator(void *p) diff --git a/queue-5.9/io_uring-round-up-cq-size-before-comparing-with-rounded-sq-size.patch b/queue-5.9/io_uring-round-up-cq-size-before-comparing-with-rounded-sq-size.patch new file mode 100644 index 00000000000..0c6331eed2a --- /dev/null +++ b/queue-5.9/io_uring-round-up-cq-size-before-comparing-with-rounded-sq-size.patch @@ -0,0 +1,47 @@ +From 88ec3211e46344a7d10cf6cb5045f839f7785f8e Mon Sep 17 00:00:00 2001 +From: Jens Axboe +Date: Wed, 11 Nov 2020 10:38:53 -0700 +Subject: io_uring: round-up cq size before comparing with rounded sq size + +From: Jens Axboe + +commit 88ec3211e46344a7d10cf6cb5045f839f7785f8e upstream. + +If an application specifies IORING_SETUP_CQSIZE to set the CQ ring size +to a specific size, we ensure that the CQ size is at least that of the +SQ ring size. But in doing so, we compare the already rounded up to power +of two SQ size to the as-of yet unrounded CQ size. This means that if an +application passes in non power of two sizes, we can return -EINVAL when +the final value would've been fine. As an example, an application passing +in 100/100 for sq/cq size should end up with 128 for both. But since we +round the SQ size first, we compare the CQ size of 100 to 128, and return +-EINVAL as that is too small. + +Cc: stable@vger.kernel.org +Fixes: 33a107f0a1b8 ("io_uring: allow application controlled CQ ring size") +Reported-by: Dan Melnic +Signed-off-by: Jens Axboe +Signed-off-by: Greg Kroah-Hartman + +--- + fs/io_uring.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/fs/io_uring.c ++++ b/fs/io_uring.c +@@ -8878,6 +8878,7 @@ static int io_uring_create(unsigned entr + * to a power-of-two, if it isn't already. We do NOT impose + * any cq vs sq ring sizing. + */ ++ p->cq_entries = roundup_pow_of_two(p->cq_entries); + if (p->cq_entries < p->sq_entries) + return -EINVAL; + if (p->cq_entries > IORING_MAX_CQ_ENTRIES) { +@@ -8885,7 +8886,6 @@ static int io_uring_create(unsigned entr + return -EINVAL; + p->cq_entries = IORING_MAX_CQ_ENTRIES; + } +- p->cq_entries = roundup_pow_of_two(p->cq_entries); + } else { + p->cq_entries = 2 * p->sq_entries; + } diff --git a/queue-5.9/mmc-renesas_sdhi_core-add-missing-tmio_mmc_host_free-at-remove.patch b/queue-5.9/mmc-renesas_sdhi_core-add-missing-tmio_mmc_host_free-at-remove.patch new file mode 100644 index 00000000000..b2fe2d39d06 --- /dev/null +++ b/queue-5.9/mmc-renesas_sdhi_core-add-missing-tmio_mmc_host_free-at-remove.patch @@ -0,0 +1,41 @@ +From e8973201d9b281375b5a8c66093de5679423021a Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda +Date: Fri, 6 Nov 2020 18:25:30 +0900 +Subject: mmc: renesas_sdhi_core: Add missing tmio_mmc_host_free() at remove +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Yoshihiro Shimoda + +commit e8973201d9b281375b5a8c66093de5679423021a upstream. + +The commit 94b110aff867 ("mmc: tmio: add tmio_mmc_host_alloc/free()") +added tmio_mmc_host_free(), but missed the function calling in +the sh_mobile_sdhi_remove() at that time. So, fix it. Otherwise, +we cannot rebind the sdhi/mmc devices when we use aliases of mmc. + +Fixes: 94b110aff867 ("mmc: tmio: add tmio_mmc_host_alloc/free()") +Signed-off-by: Yoshihiro Shimoda +Reviewed-by: Wolfram Sang +Tested-by: Wolfram Sang +Reviewed-by: Niklas Söderlund +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/1604654730-29914-1-git-send-email-yoshihiro.shimoda.uh@renesas.com +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mmc/host/renesas_sdhi_core.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mmc/host/renesas_sdhi_core.c ++++ b/drivers/mmc/host/renesas_sdhi_core.c +@@ -997,6 +997,7 @@ int renesas_sdhi_remove(struct platform_ + + tmio_mmc_host_remove(host); + renesas_sdhi_clk_disable(host); ++ tmio_mmc_host_free(host); + + return 0; + } diff --git a/queue-5.9/mmc-sdhci-of-esdhc-handle-pulse-width-detection-erratum-for-more-socs.patch b/queue-5.9/mmc-sdhci-of-esdhc-handle-pulse-width-detection-erratum-for-more-socs.patch new file mode 100644 index 00000000000..f72cb04c93a --- /dev/null +++ b/queue-5.9/mmc-sdhci-of-esdhc-handle-pulse-width-detection-erratum-for-more-socs.patch @@ -0,0 +1,34 @@ +From 71b053276a87ddfa40c8f236315d81543219bfb9 Mon Sep 17 00:00:00 2001 +From: Yangbo Lu +Date: Tue, 10 Nov 2020 15:13:14 +0800 +Subject: mmc: sdhci-of-esdhc: Handle pulse width detection erratum for more SoCs + +From: Yangbo Lu + +commit 71b053276a87ddfa40c8f236315d81543219bfb9 upstream. + +Apply erratum workaround of unreliable pulse width detection to +more affected platforms (LX2160A Rev2.0 and LS1028A Rev1.0). + +Signed-off-by: Yangbo Lu +Fixes: 48e304cc1970 ("mmc: sdhci-of-esdhc: workaround for unreliable pulse width detection") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20201110071314.3868-1-yangbo.lu@nxp.com +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mmc/host/sdhci-of-esdhc.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-esdhc.c ++++ b/drivers/mmc/host/sdhci-of-esdhc.c +@@ -1324,6 +1324,8 @@ static struct soc_device_attribute soc_f + + static struct soc_device_attribute soc_unreliable_pulse_detection[] = { + { .family = "QorIQ LX2160A", .revision = "1.0", }, ++ { .family = "QorIQ LX2160A", .revision = "2.0", }, ++ { .family = "QorIQ LS1028A", .revision = "1.0", }, + { }, + }; + diff --git a/queue-5.9/nfsv4.2-fix-failure-to-unregister-shrinker.patch b/queue-5.9/nfsv4.2-fix-failure-to-unregister-shrinker.patch new file mode 100644 index 00000000000..7099a54aafb --- /dev/null +++ b/queue-5.9/nfsv4.2-fix-failure-to-unregister-shrinker.patch @@ -0,0 +1,43 @@ +From 70438afbf17e5194dd607dd17759560a363b7bb4 Mon Sep 17 00:00:00 2001 +From: "J. Bruce Fields" +Date: Wed, 21 Oct 2020 10:34:15 -0400 +Subject: NFSv4.2: fix failure to unregister shrinker + +From: J. Bruce Fields + +commit 70438afbf17e5194dd607dd17759560a363b7bb4 upstream. + +We forgot to unregister the nfs4_xattr_large_entry_shrinker. + +That leaves the global list of shrinkers corrupted after unload of the +nfs module, after which possibly unrelated code that calls +register_shrinker() or unregister_shrinker() gets a BUG() with +"supervisor write access in kernel mode". + +And similarly for the nfs4_xattr_large_entry_lru. + +Reported-by: Kris Karas +Tested-By: Kris Karas +Fixes: 95ad37f90c33 "NFSv4.2: add client side xattr caching." +Signed-off-by: J. Bruce Fields +CC: stable@vger.kernel.org +Signed-off-by: Anna Schumaker +Signed-off-by: Greg Kroah-Hartman + +--- + fs/nfs/nfs42xattr.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/fs/nfs/nfs42xattr.c ++++ b/fs/nfs/nfs42xattr.c +@@ -1048,8 +1048,10 @@ out4: + + void nfs4_xattr_cache_exit(void) + { ++ unregister_shrinker(&nfs4_xattr_large_entry_shrinker); + unregister_shrinker(&nfs4_xattr_entry_shrinker); + unregister_shrinker(&nfs4_xattr_cache_shrinker); ++ list_lru_destroy(&nfs4_xattr_large_entry_lru); + list_lru_destroy(&nfs4_xattr_entry_lru); + list_lru_destroy(&nfs4_xattr_cache_lru); + kmem_cache_destroy(nfs4_xattr_cache_cachep); diff --git a/queue-5.9/pinctrl-amd-fix-incorrect-way-to-disable-debounce-filter.patch b/queue-5.9/pinctrl-amd-fix-incorrect-way-to-disable-debounce-filter.patch new file mode 100644 index 00000000000..e4083fac634 --- /dev/null +++ b/queue-5.9/pinctrl-amd-fix-incorrect-way-to-disable-debounce-filter.patch @@ -0,0 +1,44 @@ +From 06abe8291bc31839950f7d0362d9979edc88a666 Mon Sep 17 00:00:00 2001 +From: Coiby Xu +Date: Fri, 6 Nov 2020 07:19:09 +0800 +Subject: pinctrl: amd: fix incorrect way to disable debounce filter + +From: Coiby Xu + +commit 06abe8291bc31839950f7d0362d9979edc88a666 upstream. + +The correct way to disable debounce filter is to clear bit 5 and 6 +of the register. + +Cc: stable@vger.kerne.org +Signed-off-by: Coiby Xu +Reviewed-by: Hans de Goede +Cc: Hans de Goede +Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/ +Link: https://lore.kernel.org/r/20201105231912.69527-2-coiby.xu@gmail.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/pinctrl-amd.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct + pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg |= BIT(DB_TMR_LARGE_OFF); + } else { +- pin_reg &= ~DB_CNTRl_MASK; ++ pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); + ret = -EINVAL; + } + } else { + pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + pin_reg &= ~DB_TMR_OUT_MASK; +- pin_reg &= ~DB_CNTRl_MASK; ++ pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); + } + writel(pin_reg, gpio_dev->base + offset * 4); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); diff --git a/queue-5.9/pinctrl-amd-use-higher-precision-for-512-rtcclk.patch b/queue-5.9/pinctrl-amd-use-higher-precision-for-512-rtcclk.patch new file mode 100644 index 00000000000..356300be0a5 --- /dev/null +++ b/queue-5.9/pinctrl-amd-use-higher-precision-for-512-rtcclk.patch @@ -0,0 +1,40 @@ +From c64a6a0d4a928c63e5bc3b485552a8903a506c36 Mon Sep 17 00:00:00 2001 +From: Coiby Xu +Date: Fri, 6 Nov 2020 07:19:10 +0800 +Subject: pinctrl: amd: use higher precision for 512 RtcClk + +From: Coiby Xu + +commit c64a6a0d4a928c63e5bc3b485552a8903a506c36 upstream. + +RTC is 32.768kHz thus 512 RtcClk equals 15625 usec. The documentation +likely has dropped precision and that's why the driver mistakenly took +the slightly deviated value. + +Cc: stable@vger.kernel.org +Reported-by: Andy Shevchenko +Suggested-by: Andy Shevchenko +Suggested-by: Hans de Goede +Signed-off-by: Coiby Xu +Reviewed-by: Andy Shevchenko +Reviewed-by: Hans de Goede +Link: https://lore.kernel.org/linux-gpio/2f4706a1-502f-75f0-9596-cc25b4933b6c@redhat.com/ +Link: https://lore.kernel.org/r/20201105231912.69527-3-coiby.xu@gmail.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/pinctrl-amd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -156,7 +156,7 @@ static int amd_gpio_set_debounce(struct + pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg &= ~BIT(DB_TMR_LARGE_OFF); + } else if (debounce < 250000) { +- time = debounce / 15600; ++ time = debounce / 15625; + pin_reg |= time & DB_TMR_OUT_MASK; + pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); + pin_reg |= BIT(DB_TMR_LARGE_OFF); diff --git a/queue-5.9/selinux-fix-error-return-code-in-sel_ib_pkey_sid_slow.patch b/queue-5.9/selinux-fix-error-return-code-in-sel_ib_pkey_sid_slow.patch new file mode 100644 index 00000000000..91843603dbe --- /dev/null +++ b/queue-5.9/selinux-fix-error-return-code-in-sel_ib_pkey_sid_slow.patch @@ -0,0 +1,38 @@ +From c350f8bea271782e2733419bd2ab9bf4ec2051ef Mon Sep 17 00:00:00 2001 +From: Chen Zhou +Date: Thu, 12 Nov 2020 21:53:32 +0800 +Subject: selinux: Fix error return code in sel_ib_pkey_sid_slow() + +From: Chen Zhou + +commit c350f8bea271782e2733419bd2ab9bf4ec2051ef upstream. + +Fix to return a negative error code from the error handling case +instead of 0 in function sel_ib_pkey_sid_slow(), as done elsewhere +in this function. + +Cc: stable@vger.kernel.org +Fixes: 409dcf31538a ("selinux: Add a cache for quicker retreival of PKey SIDs") +Reported-by: Hulk Robot +Signed-off-by: Chen Zhou +Signed-off-by: Paul Moore +Signed-off-by: Greg Kroah-Hartman + +--- + security/selinux/ibpkey.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/security/selinux/ibpkey.c ++++ b/security/selinux/ibpkey.c +@@ -151,8 +151,10 @@ static int sel_ib_pkey_sid_slow(u64 subn + * is valid, it just won't be added to the cache. + */ + new = kzalloc(sizeof(*new), GFP_ATOMIC); +- if (!new) ++ if (!new) { ++ ret = -ENOMEM; + goto out; ++ } + + new->psec.subnet_prefix = subnet_prefix; + new->psec.pkey = pkey_num; diff --git a/queue-5.9/series b/queue-5.9/series index bac52db0db9..efb64497758 100644 --- a/queue-5.9/series +++ b/queue-5.9/series @@ -216,3 +216,19 @@ revert-kernel-reboot.c-convert-simple_strtoul-to-kstrtoint.patch reboot-fix-overflow-parsing-reboot-cpu-number.patch hugetlbfs-fix-anon-huge-page-migration-race.patch ocfs2-initialize-ip_next_orphan.patch +hwmon-amd_energy-modify-the-visibility-of-the-counters.patch +selinux-fix-error-return-code-in-sel_ib_pkey_sid_slow.patch +io_uring-round-up-cq-size-before-comparing-with-rounded-sq-size.patch +gpio-sifive-fix-sifive-gpio-probe.patch +gpio-pcie-idio-24-fix-irq-mask-when-masking.patch +gpio-pcie-idio-24-fix-irq-enable-register-value.patch +gpio-pcie-idio-24-enable-pex8311-interrupts.patch +mmc-sdhci-of-esdhc-handle-pulse-width-detection-erratum-for-more-socs.patch +mmc-renesas_sdhi_core-add-missing-tmio_mmc_host_free-at-remove.patch +don-t-dump-the-threads-that-had-been-already-exiting-when-zapped.patch +drm-amd-display-add-missing-pflip-irq.patch +drm-i915-correctly-set-sfc-capability-for-video-engines.patch +drm-gma500-fix-out-of-bounds-access-to-struct-drm_device.vblank.patch +nfsv4.2-fix-failure-to-unregister-shrinker.patch +pinctrl-amd-use-higher-precision-for-512-rtcclk.patch +pinctrl-amd-fix-incorrect-way-to-disable-debounce-filter.patch