From: VMware, Inc <> Date: Mon, 21 May 2012 22:19:50 +0000 (-0700) Subject: Add support for BMI2 instructions. X-Git-Tag: 2012.05.21-724730~53 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=95979ca689ab1fb600aa649f693f2b42bbdcc64d;p=thirdparty%2Fopen-vm-tools.git Add support for BMI2 instructions. The upcoming Haswell CPU adds 8 new instructions advertised via a new BMI2 bit from the cpuid instruction. This change set adds the definitions for 6 of the 8 that can be methodically added to the existing decoder tables. The remaining 2 instructions require a bit of custom code and will appear upcoming reviews. Instruction definitions taken from: "Intel Architecture Instruction Set Extensions Programming Reference" February 2012. New instructions: BZHI,PDEP,PEXT,SARX,SHLX,SHRX Signed-off-by: Dmitry Torokhov --- diff --git a/open-vm-tools/lib/include/x86cpuid.h b/open-vm-tools/lib/include/x86cpuid.h index 23cb49968..7e18a1e10 100644 --- a/open-vm-tools/lib/include/x86cpuid.h +++ b/open-vm-tools/lib/include/x86cpuid.h @@ -398,6 +398,7 @@ FLAG( 7, 0, EBX, INTEL, 0, 1, FSGSBASE, YES, FALSE) \ FLAG( 7, 0, EBX, AMD, 3, 1, BMI1, YES, TRUE ) \ FLAG( 7, 0, EBX, INTEL, 4, 1, HLE, YES, TRUE) \ FLAG( 7, 0, EBX, INTEL, 7, 1, SMEP, YES, FALSE) \ +FLAG( 7, 0, EBX, INTEL, 8, 1, BMI2, YES, TRUE) \ FLAG( 7, 0, EBX, INTEL, 9, 1, ENFSTRG, YES, FALSE) \ FLAG( 7, 0, EBX, INTEL, 10, 1, INVPCID, NO, FALSE) \ FLAG( 7, 0, EBX, INTEL, 11, 1, RTM, NO, TRUE)