From: Julian Seward <jseward@acm.org>
Date: Sat, 28 Dec 2002 00:19:00 +0000 (+0000)
Subject: synth_jcond_lit: fix bug in the sequences generated for LE/NLE.
X-Git-Tag: svn/VALGRIND_1_9_4~51
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=96b5ae06ffe4b2a8f0bf991fa56e538499a5aff8;p=thirdparty%2Fvalgrind.git

synth_jcond_lit: fix bug in the sequences generated for LE/NLE.
These assumed that ROR sets the P and Z flags and in fact it
sets neither.  Add an extra OR insn to really set those flags.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1397
---

diff --git a/coregrind/vg_from_ucode.c b/coregrind/vg_from_ucode.c
index 1153139170..63a82ae3a2 100644
--- a/coregrind/vg_from_ucode.c
+++ b/coregrind/vg_from_ucode.c
@@ -2156,6 +2156,10 @@ static void synth_jcond_lit ( Condcode cond,
             VG_(emit_shiftopv_lit_reg)( False, 4, ROR, 7, R_EAX );
             /* eax has OF and SF in lower 8 bits, and ZF in MSB */
 
+	    /* actually set the real cpu flags, since ROR changes
+	       neither P nor Z */
+	    VG_(emit_nonshiftopv_reg_reg)( False, 4, OR, R_EAX, R_EAX );
+
 	    if (cond == CondLE) {
 	       /* test Z */
 	       VG_(emit_jcondshort_target)(False, CondS, &tgt_jump);
@@ -2183,6 +2187,7 @@ static void synth_jcond_lit ( Condcode cond,
 	    VG_(emit_testb_lit_reg) ( False, 0x11, R_EAX);
 	    /* PF = OF == SF */
 
+	    /* Testing P now is OK since SHR sets it */
             if (cond == CondL) cond = CondP; else cond = CondNP;
 	    break;