From: James Greenhalgh Date: Wed, 23 Apr 2014 16:37:05 +0000 (+0000) Subject: [ARM] Initialize new tune_params values X-Git-Tag: releases/gcc-5.1.0~7970 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=984c2f30636fcc1decc552001660b216a54c80d2;p=thirdparty%2Fgcc.git [ARM] Initialize new tune_params values gcc/ * config/arm/arm.c (arm_cortex_a57_tune): Initialize all fields. (arm_cortex_a12_tune): Likewise. From-SVN: r209710 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 99f4b0d75e1f..021427b3ac5b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-04-23 James Greenhalgh + + * config/arm/arm.c (arm_cortex_a57_tune): Initialize all fields. + (arm_cortex_a12_tune): Likewise. + 2014-04-23 Kyrylo Tkachov * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle BSWAP. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 849176346c72..14dd90174373 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1781,7 +1781,8 @@ const struct tune_params arm_cortex_a57_tune = true, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + true, true /* Prefer 32-bit encodings. */ }; /* Branches can be dual-issued on Cortex-A5, so conditional execution is @@ -1834,7 +1835,8 @@ const struct tune_params arm_cortex_a12_tune = true, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ - false /* Prefer Neon for 64-bits bitops. */ + false, /* Prefer Neon for 64-bits bitops. */ + false, false /* Prefer 32-bit encodings. */ }; /* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single