From: Greg Kroah-Hartman Date: Mon, 20 Jul 2020 13:09:02 +0000 (+0200) Subject: 4.9-stable patches X-Git-Tag: v4.4.231~10 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=999fa060ce01da44507c6c9ff091a8cc48515391;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: x86-cpu-move-x86_cache_bits-settings.patch --- diff --git a/queue-4.9/series b/queue-4.9/series index 97a85283a81..bbc41c86c3d 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -84,3 +84,4 @@ misc-atmel-ssc-lock-with-mutex-instead-of-spinlock.patch arm64-ptrace-override-spsr.ss-when-single-stepping-is-enabled.patch sched-fair-handle-case-of-task_h_load-returning-0.patch irqchip-gic-atomically-update-affinity.patch +x86-cpu-move-x86_cache_bits-settings.patch diff --git a/queue-4.9/x86-cpu-move-x86_cache_bits-settings.patch b/queue-4.9/x86-cpu-move-x86_cache_bits-settings.patch new file mode 100644 index 00000000000..c89b48a724b --- /dev/null +++ b/queue-4.9/x86-cpu-move-x86_cache_bits-settings.patch @@ -0,0 +1,91 @@ +From surajjs@amazon.com Mon Jul 20 15:02:03 2020 +From: Suraj Jitindar Singh +Date: Tue, 14 Jul 2020 22:05:28 +0000 +Subject: x86/cpu: Move x86_cache_bits settings +To: +Cc: , Suraj Jitindar Singh , Samuel Mendoza-Jonas , Frank van der Linden +Message-ID: <20200714220528.32534-1-surajjs@amazon.com> + +From: Suraj Jitindar Singh + +This patch is to fix the backport of the upstream patch: +cc51e5428ea5 x86/speculation/l1tf: Increase l1tf memory limit for Nehalem+ + +When this was backported to the 4.9 and 4.14 stable branches the line ++ c->x86_cache_bits = c->x86_phys_bits; +was applied in the wrong place, being added to the +identify_cpu_without_cpuid() function instead of the get_cpu_cap() +function which it was correctly applied to in the 4.4 backport. + +This means that x86_cache_bits is not set correctly resulting in the +following warning due to the cache bits being left uninitalised (zero). + + WARNING: CPU: 0 PID: 7566 at arch/x86/kvm/mmu.c:284 kvm_mmu_set_mmio_spte_mask+0x4e/0x60 [kvm + Modules linked in: kvm_intel(+) kvm irqbypass ipv6 crc_ccitt binfmt_misc evdev lpc_ich mfd_core ioatdma pcc_cpufreq dca ena acpi_power_meter hwmon acpi_pad button ext4 crc16 mbcache jbd2 fscrypto nvme nvme_core dm_mirror dm_region_hash dm_log dm_mod dax + Hardware name: Amazon EC2 i3.metal/Not Specified, BIOS 1.0 10/16/2017 + task: ffff88ff77704c00 task.stack: ffffc9000edac000 + RIP: 0010:kvm_mmu_set_mmio_spte_mask+0x4e/0x60 [kvm + RSP: 0018:ffffc9000edafc60 EFLAGS: 00010206 + RAX: 0000000000000000 RBX: 0000000000000000 RCX: 00000000ffffff45 + RDX: 000000000000002e RSI: 0008000000000001 RDI: 0008000000000001 + RBP: ffffffffa036f000 R08: ffffffffffffff80 R09: ffffe8ffffccb3c0 + R10: 0000000000000038 R11: 0000000000000000 R12: 0000000000005b80 + R13: ffffffffa0370e40 R14: 0000000000000001 R15: ffff88bf7c0927e0 + FS: 00007fa316f24740(0000) GS:ffff88bf7f600000(0000) knlGS:0000000000000000 + CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 + CR2: 00007fa316ea0000 CR3: 0000003f7e986004 CR4: 00000000003606f0 + DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 + DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 + Call Trace: + kvm_mmu_module_init+0x166/0x230 [kvm + kvm_arch_init+0x5d/0x150 [kvm + kvm_init+0x1c/0x2d0 [kvm + ? hardware_setup+0x4a6/0x4a6 [kvm_intel + vmx_init+0x23/0x6aa [kvm_intel + ? hardware_setup+0x4a6/0x4a6 [kvm_intel + do_one_initcall+0x3e/0x15d + do_init_module+0x5b/0x1e5 + load_module+0x19e6/0x1dc0 + ? SYSC_init_module+0x13b/0x170 + SYSC_init_module+0x13b/0x170 + do_syscall_64+0x67/0x110 + entry_SYSCALL_64_after_hwframe+0x41/0xa6 + RIP: 0033:0x7fa316828f3a + RSP: 002b:00007ffc9d65c1f8 EFLAGS: 00000246 ORIG_RAX: 00000000000000af + RAX: ffffffffffffffda RBX: 00007fa316b08849 RCX: 00007fa316828f3a + RDX: 00007fa316b08849 RSI: 0000000000071328 RDI: 00007fa316e37000 + RBP: 0000000000b47e80 R08: 0000000000000003 R09: 0000000000000000 + R10: 00007fa316822dba R11: 0000000000000246 R12: 0000000000b46340 + R13: 0000000000b464c0 R14: 0000000000000000 R15: 0000000000040000 + Code: e9 65 06 00 75 25 48 b8 00 00 00 00 00 00 00 40 48 09 c6 48 09 c7 48 89 35 f8 65 06 00 48 89 3d f9 65 06 00 c3 0f 0b 0f 0b eb d2 <0f> 0b eb d7 0f 1f 40 00 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 + +Fixes: 4.9.x ef3d45c95764 x86/speculation/l1tf: Increase l1tf memory limit for Nehalem+ +Fixes: 4.14.x ec4034835eaf x86/speculation/l1tf: Increase l1tf memory limit for Nehalem+ +Cc: stable@vger.kernel.org # 4.9.x-4.14.x +Signed-off-by: Suraj Jitindar Singh +Reviewed-by: Samuel Mendoza-Jonas +Reviewed-by: Frank van der Linden +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/cpu/common.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -849,6 +849,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) + c->x86_phys_bits = 36; + #endif ++ c->x86_cache_bits = c->x86_phys_bits; + + if (c->extended_cpuid_level >= 0x8000000a) + c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); +@@ -888,7 +889,6 @@ static void identify_cpu_without_cpuid(s + } + } + #endif +- c->x86_cache_bits = c->x86_phys_bits; + } + + #define NO_SPECULATION BIT(0)