From: Philippe Mathieu-Daudé Date: Sun, 14 Dec 2025 09:34:56 +0000 (+0100) Subject: target/loongarch: Replace target_ulong -> uint64_t for DMW and TLBRBADV X-Git-Tag: v11.0.0-rc0~113^2~35 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=99d8a33fe686c6e3b0739da94e98bcb2c2ed4074;p=thirdparty%2Fqemu.git target/loongarch: Replace target_ulong -> uint64_t for DMW and TLBRBADV The Direct Mapping Configuration Window and Bad Virtual Address CSR registers are declared as uint64_t since their introduction in commit 398cecb9c3e ("target/loongarch: Add CSRs definition"): 296 typedef struct CPUArchState { ... 345 uint64_t CSR_TLBRBADV; ... 359 uint64_t CSR_DMW[4]; ... 385 } CPULoongArchState; Use the proper uint64_t type instead of target_ulong (which would otherwise be truncated on 32-bit builds). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Message-Id: <20251224161456.89707-3-philmd@linaro.org> --- diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index a6eba4f4160..4864f4d6d87 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -289,7 +289,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *env, return TLBRET_NOMATCH; } -static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, target_ulong dmw) +static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, uint64_t dmw) { if (is_la64(env)) { return va & TARGET_VIRT_MASK; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 01e0a27f0bd..873a0a1b0c4 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -690,7 +690,8 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base, uint32_t level, uint32_t mem_idx) { CPUState *cs = env_cpu(env); - target_ulong badvaddr, index, phys; + uint64_t badvaddr; + target_ulong index, phys; uint64_t dir_base, dir_width; if (unlikely((level == 0) || (level > 4))) { @@ -725,7 +726,8 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd, uint32_t mem_idx) { CPUState *cs = env_cpu(env); - target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, badv; + target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1; + uint64_t badv; uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE); uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH); uint64_t dir_base, dir_width;