From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 25 Feb 2015 13:17:29 +0000 (+0100)
Subject: arm: Use more accurate types introduced in mainline
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=9bd41631778671b525496a9648c1ed088d616da7;p=thirdparty%2Fu-boot.git

arm: Use more accurate types introduced in mainline

"ARM: cache-cp15: Use more accurate types"
(sha1: 25026fa9f16dd5f9182b47f76ce5043cb35da3f4)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index d2bf7ffe2ba..bd66b5ff6be 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -135,7 +135,7 @@ int dcache_status(void)
 	return (get_sctlr() & CR_C) != 0;
 }
 
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
 	/* get the level2_table0 start address */
@@ -184,7 +184,7 @@ int dcache_status(void)
 	return 0;
 }
 
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
 }
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 4bec1d947f3..e4204d9d4cd 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -200,16 +200,6 @@ enum {
 	MMU_SECTION_SIZE	= 1 << MMU_SECTION_SHIFT,
 };
 
-/**
- * Change the cache settings for a region.
- *
- * \param start		start address of memory region to change
- * \param size		size of memory region to change
- * \param option	dcache option to select
- */
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-				     enum dcache_option option);
-
 /**
  * Register an update to the page tables, and flush the TLB
  *
@@ -239,7 +229,7 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
  * \param size		size of memory region to change
  * \param option	dcache option to select
  */
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option);
 #endif /* __ASSEMBLY__ */
 
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 7c3c3b473e7..bae5bdad0f0 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -539,7 +539,8 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
 
 	/* Align bd_space to MMU_SECTION_SHIFT */
 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
+					BD_SPACE, DCACHE_OFF);
 
 	/* Initialize the bd spaces for tx and rx bd's */
 	priv->tx_bd = (struct emac_bd *)bd_space;