From: Sasha Levin Date: Fri, 10 Nov 2023 17:35:04 +0000 (-0500) Subject: Fixes for 5.10 X-Git-Tag: v4.14.330~67 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=9c129675f65db29c628af87d5e0751a3500870fe;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.10 Signed-off-by: Sasha Levin --- diff --git a/queue-5.10/acpi-sysfs-fix-create_pnp_modalias-and-create_of_mod.patch b/queue-5.10/acpi-sysfs-fix-create_pnp_modalias-and-create_of_mod.patch new file mode 100644 index 00000000000..e0c9fca942b --- /dev/null +++ b/queue-5.10/acpi-sysfs-fix-create_pnp_modalias-and-create_of_mod.patch @@ -0,0 +1,62 @@ +From 5f29433cffff4f8f79fd654147d79c436b3ff336 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 Oct 2023 20:32:54 +0200 +Subject: ACPI: sysfs: Fix create_pnp_modalias() and create_of_modalias() + +From: Christophe JAILLET + +[ Upstream commit 48cf49d31994ff97b33c4044e618560ec84d35fb ] + +snprintf() does not return negative values on error. + +To know if the buffer was too small, the returned value needs to be +compared with the length of the passed buffer. If it is greater or +equal, the output has been truncated, so add checks for the truncation +to create_pnp_modalias() and create_of_modalias(). Also make them +return -ENOMEM in that case, as they already do that elsewhere. + +Moreover, the remaining size of the buffer used by snprintf() needs to +be updated after the first write to avoid out-of-bounds access as +already done correctly in create_pnp_modalias(), but not in +create_of_modalias(), so change the latter accordingly. + +Fixes: 8765c5ba1949 ("ACPI / scan: Rework modalias creation when "compatible" is present") +Signed-off-by: Christophe JAILLET +[ rjw: Merge two patches into one, combine changelogs, add subject ] +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/device_sysfs.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +diff --git a/drivers/acpi/device_sysfs.c b/drivers/acpi/device_sysfs.c +index fe8c7e79f4726..566067a855a13 100644 +--- a/drivers/acpi/device_sysfs.c ++++ b/drivers/acpi/device_sysfs.c +@@ -156,8 +156,8 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias, + return 0; + + len = snprintf(modalias, size, "acpi:"); +- if (len <= 0) +- return len; ++ if (len >= size) ++ return -ENOMEM; + + size -= len; + +@@ -210,8 +210,10 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias, + len = snprintf(modalias, size, "of:N%sT", (char *)buf.pointer); + ACPI_FREE(buf.pointer); + +- if (len <= 0) +- return len; ++ if (len >= size) ++ return -ENOMEM; ++ ++ size -= len; + + of_compatible = acpi_dev->data.of_compatible; + if (of_compatible->type == ACPI_TYPE_PACKAGE) { +-- +2.42.0 + diff --git a/queue-5.10/arm-9321-1-memset-cast-the-constant-byte-to-unsigned.patch b/queue-5.10/arm-9321-1-memset-cast-the-constant-byte-to-unsigned.patch new file mode 100644 index 00000000000..efab51a0ef0 --- /dev/null +++ b/queue-5.10/arm-9321-1-memset-cast-the-constant-byte-to-unsigned.patch @@ -0,0 +1,63 @@ +From 0b228326e158d0517f99564bc0697698b87ba81c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 22 Aug 2023 15:06:06 +0100 +Subject: ARM: 9321/1: memset: cast the constant byte to unsigned char + +From: Kursad Oney + +[ Upstream commit c0e824661f443b8cab3897006c1bbc69fd0e7bc4 ] + +memset() description in ISO/IEC 9899:1999 (and elsewhere) says: + + The memset function copies the value of c (converted to an + unsigned char) into each of the first n characters of the + object pointed to by s. + +The kernel's arm32 memset does not cast c to unsigned char. This results +in the following code to produce erroneous output: + + char a[128]; + memset(a, -128, sizeof(a)); + +This is because gcc will generally emit the following code before +it calls memset() : + + mov r0, r7 + mvn r1, #127 ; 0x7f + bl 00000000 + +r1 ends up with 0xffffff80 before being used by memset() and the +'a' array will have -128 once in every four bytes while the other +bytes will be set incorrectly to -1 like this (printing the first +8 bytes) : + + test_module: -128 -1 -1 -1 + test_module: -1 -1 -1 -128 + +The change here is to 'and' r1 with 255 before it is used. + +Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") +Reviewed-by: Ard Biesheuvel +Reviewed-by: Linus Walleij +Signed-off-by: Kursad Oney +Signed-off-by: Russell King (Oracle) +Signed-off-by: Sasha Levin +--- + arch/arm/lib/memset.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S +index 6ca4535c47fb6..e36d053a8a903 100644 +--- a/arch/arm/lib/memset.S ++++ b/arch/arm/lib/memset.S +@@ -16,6 +16,7 @@ + ENTRY(mmioset) + ENTRY(memset) + UNWIND( .fnstart ) ++ and r1, r1, #255 @ cast to unsigned char + ands r3, r0, #3 @ 1 unaligned? + mov ip, r0 @ preserve r0 as return value + bne 6f @ 1 +-- +2.42.0 + diff --git a/queue-5.10/arm-dts-qcom-mdm9615-populate-vsdcc-fixed-regulator.patch b/queue-5.10/arm-dts-qcom-mdm9615-populate-vsdcc-fixed-regulator.patch new file mode 100644 index 00000000000..d6f25c0f19b --- /dev/null +++ b/queue-5.10/arm-dts-qcom-mdm9615-populate-vsdcc-fixed-regulator.patch @@ -0,0 +1,51 @@ +From c89a24999574e36aac9dc8759922f23a753fc8b1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Sep 2023 20:39:13 +0200 +Subject: ARM: dts: qcom: mdm9615: populate vsdcc fixed regulator + +From: Krzysztof Kozlowski + +[ Upstream commit 09f8ee81b6da5f76de8b83c8bfc4475b54e101e0 ] + +Fixed regulator put under "regulators" node will not be populated, +unless simple-bus or something similar is used. Drop the "regulators" +wrapper node to fix this. + +Fixes: 2c5e596524e7 ("ARM: dts: Add MDM9615 dtsi") +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230924183914.51414-3-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/qcom-mdm9615.dtsi | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi +index ad9b52d53ef9b..982f3c3921965 100644 +--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi ++++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi +@@ -82,14 +82,12 @@ cxo_board { + }; + }; + +- regulators { +- vsdcc_fixed: vsdcc-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "SDCC Power"; +- regulator-min-microvolt = <2700000>; +- regulator-max-microvolt = <2700000>; +- regulator-always-on; +- }; ++ vsdcc_fixed: vsdcc-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "SDCC Power"; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <2700000>; ++ regulator-always-on; + }; + + soc: soc { +-- +2.42.0 + diff --git a/queue-5.10/arm64-arm-xen-enlighten-fix-kpti-checks.patch b/queue-5.10/arm64-arm-xen-enlighten-fix-kpti-checks.patch new file mode 100644 index 00000000000..2742a3208d2 --- /dev/null +++ b/queue-5.10/arm64-arm-xen-enlighten-fix-kpti-checks.patch @@ -0,0 +1,128 @@ +From 5dbcea57f7a9c0cfc4ad7d1c63b9237a3aae48b0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Oct 2023 11:24:25 +0100 +Subject: arm64/arm: xen: enlighten: Fix KPTI checks + +From: Mark Rutland + +[ Upstream commit 20f3b8eafe0ba5d3c69d5011a9b07739e9645132 ] + +When KPTI is in use, we cannot register a runstate region as XEN +requires that this is always a valid VA, which we cannot guarantee. Due +to this, xen_starting_cpu() must avoid registering each CPU's runstate +region, and xen_guest_init() must avoid setting up features that depend +upon it. + +We tried to ensure that in commit: + + f88af7229f6f22ce (" xen/arm: do not setup the runstate info page if kpti is enabled") + +... where we added checks for xen_kernel_unmapped_at_usr(), which wraps +arm64_kernel_unmapped_at_el0() on arm64 and is always false on 32-bit +arm. + +Unfortunately, as xen_guest_init() is an early_initcall, this happens +before secondary CPUs are booted and arm64 has finalized the +ARM64_UNMAP_KERNEL_AT_EL0 cpucap which backs +arm64_kernel_unmapped_at_el0(), and so this can subsequently be set as +secondary CPUs are onlined. On a big.LITTLE system where the boot CPU +does not require KPTI but some secondary CPUs do, this will result in +xen_guest_init() intializing features that depend on the runstate +region, and xen_starting_cpu() registering the runstate region on some +CPUs before KPTI is subsequent enabled, resulting the the problems the +aforementioned commit tried to avoid. + +Handle this more robsutly by deferring the initialization of the +runstate region until secondary CPUs have been initialized and the +ARM64_UNMAP_KERNEL_AT_EL0 cpucap has been finalized. The per-cpu work is +moved into a new hotplug starting function which is registered later +when we're certain that KPTI will not be used. + +Fixes: f88af7229f6f ("xen/arm: do not setup the runstate info page if kpti is enabled") +Signed-off-by: Mark Rutland +Cc: Bertrand Marquis +Cc: Boris Ostrovsky +Cc: Juergen Gross +Cc: Stefano Stabellini +Cc: Suzuki K Poulose +Cc: Will Deacon +Signed-off-by: Catalin Marinas +Signed-off-by: Sasha Levin +--- + arch/arm/xen/enlighten.c | 25 ++++++++++++++++--------- + include/linux/cpuhotplug.h | 1 + + 2 files changed, 17 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c +index 8ad576ecd0f1d..3d25fd615250a 100644 +--- a/arch/arm/xen/enlighten.c ++++ b/arch/arm/xen/enlighten.c +@@ -158,9 +158,6 @@ static int xen_starting_cpu(unsigned int cpu) + BUG_ON(err); + per_cpu(xen_vcpu, cpu) = vcpup; + +- if (!xen_kernel_unmapped_at_usr()) +- xen_setup_runstate_info(cpu); +- + after_register_vcpu_info: + enable_percpu_irq(xen_events_irq, 0); + return 0; +@@ -386,9 +383,6 @@ static int __init xen_guest_init(void) + return -EINVAL; + } + +- if (!xen_kernel_unmapped_at_usr()) +- xen_time_setup_guest(); +- + if (xen_initial_domain()) + pvclock_gtod_register_notifier(&xen_pvclock_gtod_notifier); + +@@ -398,7 +392,13 @@ static int __init xen_guest_init(void) + } + early_initcall(xen_guest_init); + +-static int __init xen_pm_init(void) ++static int xen_starting_runstate_cpu(unsigned int cpu) ++{ ++ xen_setup_runstate_info(cpu); ++ return 0; ++} ++ ++static int __init xen_late_init(void) + { + if (!xen_domain()) + return -ENODEV; +@@ -411,9 +411,16 @@ static int __init xen_pm_init(void) + do_settimeofday64(&ts); + } + +- return 0; ++ if (xen_kernel_unmapped_at_usr()) ++ return 0; ++ ++ xen_time_setup_guest(); ++ ++ return cpuhp_setup_state(CPUHP_AP_ARM_XEN_RUNSTATE_STARTING, ++ "arm/xen_runstate:starting", ++ xen_starting_runstate_cpu, NULL); + } +-late_initcall(xen_pm_init); ++late_initcall(xen_late_init); + + + /* empty stubs */ +diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h +index cb87247da5ba1..7cc2889608e0f 100644 +--- a/include/linux/cpuhotplug.h ++++ b/include/linux/cpuhotplug.h +@@ -144,6 +144,7 @@ enum cpuhp_state { + /* Must be the last timer callback */ + CPUHP_AP_DUMMY_TIMER_STARTING, + CPUHP_AP_ARM_XEN_STARTING, ++ CPUHP_AP_ARM_XEN_RUNSTATE_STARTING, + CPUHP_AP_ARM_CORESIGHT_STARTING, + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, + CPUHP_AP_ARM64_ISNDEP_STARTING, +-- +2.42.0 + diff --git a/queue-5.10/arm64-dts-qcom-msm8916-fix-iommu-local-address-range.patch b/queue-5.10/arm64-dts-qcom-msm8916-fix-iommu-local-address-range.patch new file mode 100644 index 00000000000..7e698189f25 --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-msm8916-fix-iommu-local-address-range.patch @@ -0,0 +1,40 @@ +From bd79841902fa7681db1aa5409473c74276e7cdf3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Sep 2023 20:03:04 +0530 +Subject: arm64: dts: qcom: msm8916: Fix iommu local address range + +From: Gaurav Kohli + +[ Upstream commit 2de8ee9f58fa51f707c71f8fbcd8470ab0078102 ] + +Fix the apps iommu local address space range as per data sheet. + +Fixes: 6a6729f38436 ("arm64: dts: qcom: msm8916: Add IOMMU support") +Reviewed-by: Bryan O'Donoghue +Tested-by: Bryan O'Donoghue +Signed-off-by: Gaurav Kohli +Reviewed-by: Stephan Gerhold +Acked-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230915143304.477-1-quic_gkohli@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi +index 5b79e4a373311..c39a299fc636f 100644 +--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi +@@ -1175,7 +1175,7 @@ apps_iommu: iommu@1ef0000 { + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; +- ranges = <0 0x01e20000 0x40000>; ++ ranges = <0 0x01e20000 0x20000>; + reg = <0x01ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; +-- +2.42.0 + diff --git a/queue-5.10/arm64-dts-qcom-sdm845-mtp-fix-wifi-configuration.patch b/queue-5.10/arm64-dts-qcom-sdm845-mtp-fix-wifi-configuration.patch new file mode 100644 index 00000000000..1eea49344bd --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-sdm845-mtp-fix-wifi-configuration.patch @@ -0,0 +1,37 @@ +From 7f6e88970b541bf0f8ec56c978d0872ca4677221 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 27 Aug 2023 01:19:11 +0300 +Subject: arm64: dts: qcom: sdm845-mtp: fix WiFi configuration + +From: Dmitry Baryshkov + +[ Upstream commit b33868a52f342d9b1f20aa5bffe40cbd69bd0a4b ] + +Enable the host-cap-8bit quirk on this device. It is required for the +WiFi to function properly. + +Fixes: 022bccb840b7 ("arm64: dts: sdm845: Add WCN3990 WLAN module device node") +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230826221915.846937-2-dmitry.baryshkov@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +index 1372fe8601f50..e3d2fb9aafe42 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts ++++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +@@ -564,6 +564,8 @@ &wifi { + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; ++ ++ qcom,snoc-host-cap-8bit-quirk; + }; + + /* PINCTRL - additions to nodes defined in sdm845.dtsi */ +-- +2.42.0 + diff --git a/queue-5.10/asoc-ams-delta.c-use-component-after-check.patch b/queue-5.10/asoc-ams-delta.c-use-component-after-check.patch new file mode 100644 index 00000000000..583bb8ff3ce --- /dev/null +++ b/queue-5.10/asoc-ams-delta.c-use-component-after-check.patch @@ -0,0 +1,56 @@ +From 17f3130bd80c5bbf7cd4a76d0a42bb08203cdbf9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 27 Oct 2023 00:09:56 +0000 +Subject: ASoC: ams-delta.c: use component after check + +From: Kuninori Morimoto + +[ Upstream commit bd0f7498bc9084d8cccc5484cd004b40f314b763 ] + + static void cx81801_close() + { + ... +(A) struct snd_soc_dapm_context *dapm = &component->card->dapm; + ... +(B) if (!component) + return; + } + +(A) uses component before NULL check (B). This patch moves it after (B). + +Fixes: d0fdfe34080c ("ASoC: cx20442: replace codec to component") +Reported-by: Dan Carpenter +Closes: https://lore.kernel.org/r/3e608474-e99a-4866-ae98-3054a4221f09@moroto.mountain +Signed-off-by: Kuninori Morimoto +Link: https://lore.kernel.org/r/87ttqdq623.wl-kuninori.morimoto.gx@renesas.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/ti/ams-delta.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/ti/ams-delta.c b/sound/soc/ti/ams-delta.c +index 57feb473a579c..fbd75732a68b3 100644 +--- a/sound/soc/ti/ams-delta.c ++++ b/sound/soc/ti/ams-delta.c +@@ -303,7 +303,7 @@ static int cx81801_open(struct tty_struct *tty) + static void cx81801_close(struct tty_struct *tty) + { + struct snd_soc_component *component = tty->disc_data; +- struct snd_soc_dapm_context *dapm = &component->card->dapm; ++ struct snd_soc_dapm_context *dapm; + + del_timer_sync(&cx81801_timer); + +@@ -315,6 +315,8 @@ static void cx81801_close(struct tty_struct *tty) + + v253_ops.close(tty); + ++ dapm = &component->card->dapm; ++ + /* Revert back to default audio input/output constellation */ + snd_soc_dapm_mutex_lock(dapm); + +-- +2.42.0 + diff --git a/queue-5.10/asoc-fsl-fix-pm-disable-depth-imbalance-in-fsl_easrc.patch b/queue-5.10/asoc-fsl-fix-pm-disable-depth-imbalance-in-fsl_easrc.patch new file mode 100644 index 00000000000..7984b60e72e --- /dev/null +++ b/queue-5.10/asoc-fsl-fix-pm-disable-depth-imbalance-in-fsl_easrc.patch @@ -0,0 +1,54 @@ +From faecc0af8642336f368d7c27f7f2ccb4286e1383 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 12 Oct 2023 21:03:15 +0800 +Subject: ASoC: fsl: Fix PM disable depth imbalance in fsl_easrc_probe + +From: Zhang Shurong + +[ Upstream commit 9e630efb5a4af56fdb15aa10405f5cfd3f5f5b83 ] + +The pm_runtime_enable will increase power disable depth. Thus +a pairing decrement is needed on the error handling path to +keep it balanced according to context. We fix it by calling +pm_runtime_disable when error returns. + +Fixes: 955ac624058f ("ASoC: fsl_easrc: Add EASRC ASoC CPU DAI drivers") +Signed-off-by: Zhang Shurong +Link: https://lore.kernel.org/r/tencent_C0D62E6D89818179A02A04A0C248F0DDC40A@qq.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/fsl/fsl_easrc.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/fsl/fsl_easrc.c b/sound/soc/fsl/fsl_easrc.c +index 3cf1f40e68924..acd500c3b9d04 100644 +--- a/sound/soc/fsl/fsl_easrc.c ++++ b/sound/soc/fsl/fsl_easrc.c +@@ -1971,17 +1971,21 @@ static int fsl_easrc_probe(struct platform_device *pdev) + &fsl_easrc_dai, 1); + if (ret) { + dev_err(dev, "failed to register ASoC DAI\n"); +- return ret; ++ goto err_pm_disable; + } + + ret = devm_snd_soc_register_component(dev, &fsl_asrc_component, + NULL, 0); + if (ret) { + dev_err(&pdev->dev, "failed to register ASoC platform\n"); +- return ret; ++ goto err_pm_disable; + } + + return 0; ++ ++err_pm_disable: ++ pm_runtime_disable(&pdev->dev); ++ return ret; + } + + static int fsl_easrc_remove(struct platform_device *pdev) +-- +2.42.0 + diff --git a/queue-5.10/asoc-fsl-mpc5200_dma.c-fix-warning-of-function-param.patch b/queue-5.10/asoc-fsl-mpc5200_dma.c-fix-warning-of-function-param.patch new file mode 100644 index 00000000000..609833192b0 --- /dev/null +++ b/queue-5.10/asoc-fsl-mpc5200_dma.c-fix-warning-of-function-param.patch @@ -0,0 +1,45 @@ +From c18dfbef3bbcdbc0319a6ce4befb734d4951be4f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 9 Oct 2023 23:39:43 +0000 +Subject: ASoC: fsl: mpc5200_dma.c: Fix warning of Function parameter or member + not described + +From: Kuninori Morimoto + +[ Upstream commit 4a221b2e3340f4a3c2b414c46c846a26c6caf820 ] + +This patch fixes the warnings of "Function parameter or member 'xxx' +not described". + +>> sound/soc/fsl/mpc5200_dma.c:116: warning: Function parameter or member 'component' not described in 'psc_dma_trigger' + sound/soc/fsl/mpc5200_dma.c:116: warning: Function parameter or member 'substream' not described in 'psc_dma_trigger' + sound/soc/fsl/mpc5200_dma.c:116: warning: Function parameter or member 'cmd' not described in 'psc_dma_trigger' + +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202310061914.jJuekdHs-lkp@intel.com/ +Signed-off-by: Kuninori Morimoto +Fixes: 6d1048bc1152 ("ASoC: fsl: mpc5200_dma: remove snd_pcm_ops") +Link: https://lore.kernel.org/r/87il7fcqm8.wl-kuninori.morimoto.gx@renesas.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/fsl/mpc5200_dma.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/sound/soc/fsl/mpc5200_dma.c b/sound/soc/fsl/mpc5200_dma.c +index 2319848821762..2e82731072c98 100644 +--- a/sound/soc/fsl/mpc5200_dma.c ++++ b/sound/soc/fsl/mpc5200_dma.c +@@ -107,6 +107,9 @@ static int psc_dma_hw_free(struct snd_soc_component *component, + + /** + * psc_dma_trigger: start and stop the DMA transfer. ++ * @component: triggered component ++ * @substream: triggered substream ++ * @cmd: triggered command + * + * This function is called by ALSA to start, stop, pause, and resume the DMA + * transfer of data. +-- +2.42.0 + diff --git a/queue-5.10/asoc-intel-skylake-fix-mem-leak-when-parsing-uuids-f.patch b/queue-5.10/asoc-intel-skylake-fix-mem-leak-when-parsing-uuids-f.patch new file mode 100644 index 00000000000..8b7de70b2d9 --- /dev/null +++ b/queue-5.10/asoc-intel-skylake-fix-mem-leak-when-parsing-uuids-f.patch @@ -0,0 +1,40 @@ +From 3874cff801ce672c514e465c3fcbf7a76d0aa0d7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 26 Oct 2023 10:25:58 +0200 +Subject: ASoC: Intel: Skylake: Fix mem leak when parsing UUIDs fails +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Cezary Rojewski + +[ Upstream commit 168d97844a61db302dec76d44406e9d4d7106b8e ] + +Error path in snd_skl_parse_uuids() shall free last allocated module if +its instance_id allocation fails. + +Fixes: f8e066521192 ("ASoC: Intel: Skylake: Fix uuid_module memory leak in failure case") +Signed-off-by: Cezary Rojewski +Signed-off-by: Amadeusz Sławiński +Link: https://lore.kernel.org/r/20231026082558.1864910-1-amadeuszx.slawinski@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/intel/skylake/skl-sst-utils.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/soc/intel/skylake/skl-sst-utils.c b/sound/soc/intel/skylake/skl-sst-utils.c +index 57ea815d3f041..b776c58dcf47a 100644 +--- a/sound/soc/intel/skylake/skl-sst-utils.c ++++ b/sound/soc/intel/skylake/skl-sst-utils.c +@@ -299,6 +299,7 @@ int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, + module->instance_id = devm_kzalloc(ctx->dev, size, GFP_KERNEL); + if (!module->instance_id) { + ret = -ENOMEM; ++ kfree(module); + goto free_uuid_list; + } + +-- +2.42.0 + diff --git a/queue-5.10/can-dev-can_restart-don-t-crash-kernel-if-carrier-is.patch b/queue-5.10/can-dev-can_restart-don-t-crash-kernel-if-carrier-is.patch new file mode 100644 index 00000000000..2b0a8d0be2c --- /dev/null +++ b/queue-5.10/can-dev-can_restart-don-t-crash-kernel-if-carrier-is.patch @@ -0,0 +1,46 @@ +From 9843280826aa5461f9242e79394d2baa06289d4d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Sep 2023 21:58:23 +0200 +Subject: can: dev: can_restart(): don't crash kernel if carrier is OK + +From: Marc Kleine-Budde + +[ Upstream commit fe5c9940dfd8ba0c73672dddb30acd1b7a11d4c7 ] + +During testing, I triggered a can_restart() with the netif carrier +being OK [1]. The BUG_ON, which checks if the carrier is OK, results +in a fatal kernel crash. This is neither helpful for debugging nor for +a production system. + +[1] The root cause is a race condition in can_restart() which will be +fixed in the next patch. + +Do not crash the kernel, issue an error message instead, and continue +restarting the CAN device anyway. + +Fixes: 39549eef3587 ("can: CAN Network device driver and Netlink interface") +Link: https://lore.kernel.org/all/20231005-can-dev-fix-can-restart-v2-1-91b5c1fd922c@pengutronix.de +Reviewed-by: Vincent Mailhol +Signed-off-by: Marc Kleine-Budde +Signed-off-by: Sasha Levin +--- + drivers/net/can/dev/dev.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/can/dev/dev.c b/drivers/net/can/dev/dev.c +index 2b38a99884f2f..2af3ac4e52330 100644 +--- a/drivers/net/can/dev/dev.c ++++ b/drivers/net/can/dev/dev.c +@@ -578,7 +578,8 @@ static void can_restart(struct net_device *dev) + struct can_frame *cf; + int err; + +- BUG_ON(netif_carrier_ok(dev)); ++ if (netif_carrier_ok(dev)) ++ netdev_err(dev, "Attempt to restart for bus-off recovery, but carrier is OK?\n"); + + /* No synchronization needed because the device is bus-off and + * no messages can come in or go out. +-- +2.42.0 + diff --git a/queue-5.10/can-dev-can_restart-fix-race-condition-between-contr.patch b/queue-5.10/can-dev-can_restart-fix-race-condition-between-contr.patch new file mode 100644 index 00000000000..56a38de35e5 --- /dev/null +++ b/queue-5.10/can-dev-can_restart-fix-race-condition-between-contr.patch @@ -0,0 +1,102 @@ +From e91e6898652a3680655a2bc66e5833225a7e8837 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 29 Sep 2023 10:25:11 +0200 +Subject: can: dev: can_restart(): fix race condition between controller + restart and netif_carrier_on() + +From: Marc Kleine-Budde + +[ Upstream commit 6841cab8c4504835e4011689cbdb3351dec693fd ] + +This race condition was discovered while updating the at91_can driver +to use can_bus_off(). The following scenario describes how the +converted at91_can driver would behave. + +When a CAN device goes into BUS-OFF state, the driver usually +stops/resets the CAN device and calls can_bus_off(). + +This function sets the netif carrier to off, and (if configured by +user space) schedules a delayed work that calls can_restart() to +restart the CAN device. + +The can_restart() function first checks if the carrier is off and +triggers an error message if the carrier is OK. + +Then it calls the driver's do_set_mode() function to restart the +device, then it sets the netif carrier to on. There is a race window +between these two calls. + +The at91 CAN controller (observed on the sama5d3, a single core 32 bit +ARM CPU) has a hardware limitation. If the device goes into bus-off +while sending a CAN frame, there is no way to abort the sending of +this frame. After the controller is enabled again, another attempt is +made to send it. + +If the bus is still faulty, the device immediately goes back to the +bus-off state. The driver calls can_bus_off(), the netif carrier is +switched off and another can_restart is scheduled. This occurs within +the race window before the original can_restart() handler marks the +netif carrier as OK. This would cause the 2nd can_restart() to be +called with an OK netif carrier, resulting in an error message. + +The flow of the 1st can_restart() looks like this: + +can_restart() + // bail out if netif_carrier is OK + + netif_carrier_ok(dev) + priv->do_set_mode(dev, CAN_MODE_START) + // enable CAN controller + // sama5d3 restarts sending old message + + // CAN devices goes into BUS_OFF, triggers IRQ + +// IRQ handler start + at91_irq() + at91_irq_err_line() + can_bus_off() + netif_carrier_off() + schedule_delayed_work() +// IRQ handler end + + netif_carrier_on() + +The 2nd can_restart() will be called with an OK netif carrier and the +error message will be printed. + +To close the race window, first set the netif carrier to on, then +restart the controller. In case the restart fails with an error code, +roll back the netif carrier to off. + +Fixes: 39549eef3587 ("can: CAN Network device driver and Netlink interface") +Link: https://lore.kernel.org/all/20231005-can-dev-fix-can-restart-v2-2-91b5c1fd922c@pengutronix.de +Reviewed-by: Vincent Mailhol +Signed-off-by: Marc Kleine-Budde +Signed-off-by: Sasha Levin +--- + drivers/net/can/dev/dev.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/can/dev/dev.c b/drivers/net/can/dev/dev.c +index 2af3ac4e52330..b5e79d63d59b5 100644 +--- a/drivers/net/can/dev/dev.c ++++ b/drivers/net/can/dev/dev.c +@@ -603,11 +603,12 @@ static void can_restart(struct net_device *dev) + priv->can_stats.restarts++; + + /* Now restart the device */ +- err = priv->do_set_mode(dev, CAN_MODE_START); +- + netif_carrier_on(dev); +- if (err) ++ err = priv->do_set_mode(dev, CAN_MODE_START); ++ if (err) { + netdev_err(dev, "Error %d during restart", err); ++ netif_carrier_off(dev); ++ } + } + + static void can_restart_work(struct work_struct *work) +-- +2.42.0 + diff --git a/queue-5.10/chtls-fix-tp-rcv_tstamp-initialization.patch b/queue-5.10/chtls-fix-tp-rcv_tstamp-initialization.patch new file mode 100644 index 00000000000..9fa5a054dec --- /dev/null +++ b/queue-5.10/chtls-fix-tp-rcv_tstamp-initialization.patch @@ -0,0 +1,36 @@ +From af3bf14b22824cdf732514b6257a92f71d274eb9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 Oct 2023 12:57:36 +0000 +Subject: chtls: fix tp->rcv_tstamp initialization + +From: Eric Dumazet + +[ Upstream commit 225d9ddbacb102621af6d28ff7bf5a0b4ce249d8 ] + +tp->rcv_tstamp should be set to tcp_jiffies, not tcp_time_stamp(). + +Fixes: cc35c88ae4db ("crypto : chtls - CPL handler definition") +Signed-off-by: Eric Dumazet +Cc: Ayush Sawal +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c +index cd6e016e62103..ccf2bec283d35 100644 +--- a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c ++++ b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c +@@ -2259,7 +2259,7 @@ static void chtls_rx_ack(struct sock *sk, struct sk_buff *skb) + + if (tp->snd_una != snd_una) { + tp->snd_una = snd_una; +- tp->rcv_tstamp = tcp_time_stamp(tp); ++ tp->rcv_tstamp = tcp_jiffies32; + if (tp->snd_una == tp->snd_nxt && + !csk_flag_nochk(csk, CSK_TX_FAILOVER)) + csk_reset_flag(csk, CSK_TX_WAIT_IDLE); +-- +2.42.0 + diff --git a/queue-5.10/clk-asm9260-use-parent-index-to-link-the-reference-c.patch b/queue-5.10/clk-asm9260-use-parent-index-to-link-the-reference-c.patch new file mode 100644 index 00000000000..074c2f337d4 --- /dev/null +++ b/queue-5.10/clk-asm9260-use-parent-index-to-link-the-reference-c.patch @@ -0,0 +1,139 @@ +From bb29b98c79097956f41bb4fe65ef0fa22a010f36 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 09:17:38 +0300 +Subject: clk: asm9260: use parent index to link the reference clock + +From: Dmitry Baryshkov + +[ Upstream commit f5290d8e4f0caa81a491448a27dd70e726095d07 ] + +Rewrite clk-asm9260 to use parent index to use the reference clock. +During this rework two helpers are added: + +- clk_hw_register_mux_table_parent_data() to supplement + clk_hw_register_mux_table() but using parent_data instead of + parent_names + +- clk_hw_register_fixed_rate_parent_accuracy() to be used instead of + directly calling __clk_hw_register_fixed_rate(). The later function is + an internal API, which is better not to be called directly. + +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220916061740.87167-2-dmitry.baryshkov@linaro.org +Signed-off-by: Stephen Boyd +Stable-dep-of: 84aefafe6b29 ("clk: linux/clk-provider.h: fix kernel-doc warnings and typos") +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-asm9260.c | 29 ++++++++++++----------------- + include/linux/clk-provider.h | 21 +++++++++++++++++++++ + 2 files changed, 33 insertions(+), 17 deletions(-) + +diff --git a/drivers/clk/clk-asm9260.c b/drivers/clk/clk-asm9260.c +index bacebd457e6f3..8b3c059e19a12 100644 +--- a/drivers/clk/clk-asm9260.c ++++ b/drivers/clk/clk-asm9260.c +@@ -80,7 +80,7 @@ struct asm9260_mux_clock { + u8 mask; + u32 *table; + const char *name; +- const char **parent_names; ++ const struct clk_parent_data *parent_data; + u8 num_parents; + unsigned long offset; + unsigned long flags; +@@ -232,10 +232,10 @@ static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = { + HW_AHBCLKCTRL1, 16 }, + }; + +-static const char __initdata *main_mux_p[] = { NULL, NULL }; +-static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"}; +-static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"}; +-static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"}; ++static struct clk_parent_data __initdata main_mux_p[] = { { .index = 0, }, { .name = "pll" } }; ++static struct clk_parent_data __initdata i2s0_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s0m_div"} }; ++static struct clk_parent_data __initdata i2s1_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s1m_div"} }; ++static struct clk_parent_data __initdata clkout_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "rtc"} }; + static u32 three_mux_table[] = {0, 1, 3}; + + static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = { +@@ -255,9 +255,10 @@ static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = { + + static void __init asm9260_acc_init(struct device_node *np) + { +- struct clk_hw *hw; ++ struct clk_hw *hw, *pll_hw; + struct clk_hw **hws; +- const char *ref_clk, *pll_clk = "pll"; ++ const char *pll_clk = "pll"; ++ struct clk_parent_data pll_parent_data = { .index = 0 }; + u32 rate; + int n; + +@@ -274,21 +275,15 @@ static void __init asm9260_acc_init(struct device_node *np) + /* register pll */ + rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000; + +- /* TODO: Convert to DT parent scheme */ +- ref_clk = of_clk_get_parent_name(np, 0); +- hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk, +- ref_clk, NULL, NULL, 0, rate, 0, +- CLK_FIXED_RATE_PARENT_ACCURACY); +- +- if (IS_ERR(hw)) ++ pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data, ++ 0, rate); ++ if (IS_ERR(pll_hw)) + panic("%pOFn: can't register REFCLK. Check DT!", np); + + for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) { + const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n]; + +- mc->parent_names[0] = ref_clk; +- mc->parent_names[1] = pll_clk; +- hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names, ++ hw = clk_hw_register_mux_table_parent_data(NULL, mc->name, mc->parent_data, + mc->num_parents, mc->flags, base + mc->offset, + 0, mc->mask, 0, mc->table, &asm9260_clk_lock); + } +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index 03a5de5f99f4a..d199f79c70915 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -439,6 +439,20 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ + (parent_data), NULL, (flags), \ + (fixed_rate), (fixed_accuracy), 0) ++/** ++ * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with ++ * the clock framework ++ * @dev: device that is registering this clock ++ * @name: name of this clock ++ * @parent_name: name of clock's parent ++ * @flags: framework-specific flags ++ * @fixed_rate: non-adjustable clock rate ++ */ ++#define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \ ++ flags, fixed_rate) \ ++ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ ++ (parent_data), (flags), (fixed_rate), 0, \ ++ CLK_FIXED_RATE_PARENT_ACCURACY) + + void clk_unregister_fixed_rate(struct clk *clk); + void clk_hw_unregister_fixed_rate(struct clk_hw *hw); +@@ -858,6 +872,13 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, + (parent_names), NULL, NULL, (flags), (reg), \ + (shift), (mask), (clk_mux_flags), (table), \ + (lock)) ++#define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \ ++ num_parents, flags, reg, shift, mask, \ ++ clk_mux_flags, table, lock) \ ++ __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ ++ NULL, NULL, (parent_data), (flags), (reg), \ ++ (shift), (mask), (clk_mux_flags), (table), \ ++ (lock)) + #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ + shift, width, clk_mux_flags, lock) \ + __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ +-- +2.42.0 + diff --git a/queue-5.10/clk-imx-imx8mq-correct-error-handling-path.patch b/queue-5.10/clk-imx-imx8mq-correct-error-handling-path.patch new file mode 100644 index 00000000000..a86fd036e06 --- /dev/null +++ b/queue-5.10/clk-imx-imx8mq-correct-error-handling-path.patch @@ -0,0 +1,71 @@ +From 37d22cd7083d23c52da53e04b83b0b08ce71ce95 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 1 Oct 2023 20:26:18 +0800 +Subject: clk: imx: imx8mq: correct error handling path + +From: Peng Fan + +[ Upstream commit 577ad169966e6e75b10e004389a3f79813e84b5d ] + +Avoid memory leak in error handling path. It does not make +much sense for the SoC without clk driver, to make program behavior +correct, let's fix it. + +Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM") +Reported-by: kernel test robot +Reported-by: Dan Carpenter +Closes: https://lore.kernel.org/r/202309240551.e46NllPa-lkp@intel.com/ +Signed-off-by: Peng Fan +Link: https://lore.kernel.org/r/20231001122618.194498-1-peng.fan@oss.nxp.com +Signed-off-by: Abel Vesa +Signed-off-by: Sasha Levin +--- + drivers/clk/imx/clk-imx8mq.c | 17 ++++++++++------- + 1 file changed, 10 insertions(+), 7 deletions(-) + +diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c +index f679e5cc320b5..89313dd7a57f6 100644 +--- a/drivers/clk/imx/clk-imx8mq.c ++++ b/drivers/clk/imx/clk-imx8mq.c +@@ -280,8 +280,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + void __iomem *base; + int err; + +- clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, +- IMX8MQ_CLK_END), GFP_KERNEL); ++ clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + +@@ -298,10 +297,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); +- base = of_iomap(np, 0); ++ base = devm_of_iomap(dev, np, 0, NULL); + of_node_put(np); +- if (WARN_ON(!base)) +- return -ENOMEM; ++ if (WARN_ON(IS_ERR(base))) { ++ err = PTR_ERR(base); ++ goto unregister_hws; ++ } + + hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +@@ -373,8 +374,10 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + + np = dev->of_node; + base = devm_platform_ioremap_resource(pdev, 0); +- if (WARN_ON(IS_ERR(base))) +- return PTR_ERR(base); ++ if (WARN_ON(IS_ERR(base))) { ++ err = PTR_ERR(base); ++ goto unregister_hws; ++ } + + /* CORE */ + hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000); +-- +2.42.0 + diff --git a/queue-5.10/clk-imx-select-mxc_clk-for-clk_imx8qxp.patch b/queue-5.10/clk-imx-select-mxc_clk-for-clk_imx8qxp.patch new file mode 100644 index 00000000000..ab5360588b4 --- /dev/null +++ b/queue-5.10/clk-imx-select-mxc_clk-for-clk_imx8qxp.patch @@ -0,0 +1,43 @@ +From 4ad9be68de57e541945cf933dd3be639e9bf1747 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Sep 2023 12:23:54 +0300 +Subject: clk: imx: Select MXC_CLK for CLK_IMX8QXP + +From: Abel Vesa + +[ Upstream commit 317e69c49b4ceef8aebb47d771498ccb3571bdf9 ] + +If the i.MX8QXP clock provider is built-in but the MXC_CLK is +built as module, build fails: + +aarch64-linux-ld: drivers/clk/imx/clk-imx8-acm.o: in function `imx8_acm_clk_probe': +clk-imx8-acm.c:(.text+0x3d0): undefined reference to `imx_check_clk_hws' + +Fix that by selecting MXC_CLK in case of CLK_IMX8QXP. + +Fixes: c2cccb6d0b33 ("clk: imx: add imx8qxp clk driver") +Closes: https://lore.kernel.org/all/8b77219e-b59e-40f1-96f1-980a0b2debcf@infradead.org/ +Reported-by: Randy Dunlap +Reviewed-by: Peng Fan +Acked-by: Randy Dunlap +Tested-by: Randy Dunlap +Signed-off-by: Abel Vesa +Signed-off-by: Sasha Levin +--- + drivers/clk/imx/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig +index 47d9ec3abd2f7..d3d730610cb4f 100644 +--- a/drivers/clk/imx/Kconfig ++++ b/drivers/clk/imx/Kconfig +@@ -96,5 +96,6 @@ config CLK_IMX8QXP + depends on (ARCH_MXC && ARM64) || COMPILE_TEST + depends on IMX_SCU && HAVE_ARM_SMCCC + select MXC_CLK_SCU ++ select MXC_CLK + help + Build the driver for IMX8QXP SCU based clocks. +-- +2.42.0 + diff --git a/queue-5.10/clk-keystone-pll-fix-a-couple-null-vs-is_err-checks.patch b/queue-5.10/clk-keystone-pll-fix-a-couple-null-vs-is_err-checks.patch new file mode 100644 index 00000000000..c2067f3c6dc --- /dev/null +++ b/queue-5.10/clk-keystone-pll-fix-a-couple-null-vs-is_err-checks.patch @@ -0,0 +1,61 @@ +From c48f97bc92372c32dd7c5b25c7cb0212f0f2243b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 5 Oct 2023 17:01:57 +0300 +Subject: clk: keystone: pll: fix a couple NULL vs IS_ERR() checks + +From: Dan Carpenter + +[ Upstream commit a5d14f8b551eb1551c10053653ee8e27f19672fa ] + +The clk_register_divider() and clk_register_mux() functions returns +error pointers on error but this code checks for NULL. Fix that. + +Fixes: b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver") +Signed-off-by: Dan Carpenter +Link: https://lore.kernel.org/r/d9da4c97-0da9-499f-9a21-1f8e3f148dc1@moroto.mountain +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/keystone/pll.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c +index ee5c72369334f..6bbdd4705d71f 100644 +--- a/drivers/clk/keystone/pll.c ++++ b/drivers/clk/keystone/pll.c +@@ -281,12 +281,13 @@ static void __init of_pll_div_clk_init(struct device_node *node) + + clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, + mask, 0, NULL); +- if (clk) { +- of_clk_add_provider(node, of_clk_src_simple_get, clk); +- } else { ++ if (IS_ERR(clk)) { + pr_err("%s: error registering divider %s\n", __func__, clk_name); + iounmap(reg); ++ return; + } ++ ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); + } + CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init); + +@@ -328,10 +329,12 @@ static void __init of_pll_mux_clk_init(struct device_node *node) + clk = clk_register_mux(NULL, clk_name, (const char **)&parents, + ARRAY_SIZE(parents) , 0, reg, shift, mask, + 0, NULL); +- if (clk) +- of_clk_add_provider(node, of_clk_src_simple_get, clk); +- else ++ if (IS_ERR(clk)) { + pr_err("%s: error registering mux %s\n", __func__, clk_name); ++ return; ++ } ++ ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); + } + CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init); + +-- +2.42.0 + diff --git a/queue-5.10/clk-linux-clk-provider.h-fix-kernel-doc-warnings-and.patch b/queue-5.10/clk-linux-clk-provider.h-fix-kernel-doc-warnings-and.patch new file mode 100644 index 00000000000..41547cd910b --- /dev/null +++ b/queue-5.10/clk-linux-clk-provider.h-fix-kernel-doc-warnings-and.patch @@ -0,0 +1,117 @@ +From 935585f3a8f294a2208e56e3691b728ebd8587ed Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 30 Sep 2023 15:14:26 -0700 +Subject: clk: linux/clk-provider.h: fix kernel-doc warnings and typos + +From: Randy Dunlap + +[ Upstream commit 84aefafe6b294041b7fa0757414c4a29c1bdeea2 ] + +Fix spelling of "Structure". + +Fix multiple kernel-doc warnings: + +clk-provider.h:269: warning: Function parameter or member 'recalc_rate' not described in 'clk_ops' +clk-provider.h:468: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_with_accuracy_parent_data' +clk-provider.h:468: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_with_accuracy_parent_data' +clk-provider.h:482: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_parent_accuracy' +clk-provider.h:482: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_parent_accuracy' +clk-provider.h:687: warning: Function parameter or member 'flags' not described in 'clk_divider' +clk-provider.h:1164: warning: Function parameter or member 'flags' not described in 'clk_fractional_divider' +clk-provider.h:1164: warning: Function parameter or member 'approximation' not described in 'clk_fractional_divider' +clk-provider.h:1213: warning: Function parameter or member 'flags' not described in 'clk_multiplier' + +Fixes: 9fba738a53dd ("clk: add duty cycle support") +Fixes: b2476490ef11 ("clk: introduce the common clock framework") +Fixes: 2d34f09e79c9 ("clk: fixed-rate: Add support for specifying parents via DT/pointers") +Fixes: f5290d8e4f0c ("clk: asm9260: use parent index to link the reference clock") +Fixes: 9d9f78ed9af0 ("clk: basic clock hardware types") +Fixes: e2d0e90fae82 ("clk: new basic clk type for fractional divider") +Fixes: f2e0a53271a4 ("clk: Add a basic multiplier clock") + +Signed-off-by: Randy Dunlap +Cc: Michael Turquette +Cc: Stephen Boyd +Cc: linux-clk@vger.kernel.org +Link: https://lore.kernel.org/r/20230930221428.18463-1-rdunlap@infradead.org +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + include/linux/clk-provider.h | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index d199f79c70915..aa8cbf8829145 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -61,7 +61,7 @@ struct clk_rate_request { + }; + + /** +- * struct clk_duty - Struture encoding the duty cycle ratio of a clock ++ * struct clk_duty - Structure encoding the duty cycle ratio of a clock + * + * @num: Numerator of the duty cycle ratio + * @den: Denominator of the duty cycle ratio +@@ -116,7 +116,7 @@ struct clk_duty { + * @restore_context: Restore the context of the clock after a restoration + * of power. + * +- * @recalc_rate Recalculate the rate of this clock, by querying hardware. The ++ * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The + * parent rate is an input parameter. It is up to the caller to + * ensure that the prepare_mutex is held across this call. + * Returns the calculated rate. Optional, but recommended - if +@@ -429,7 +429,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + * clock with the clock framework + * @dev: device that is registering this clock + * @name: name of this clock +- * @parent_name: name of clock's parent ++ * @parent_data: name of clock's parent + * @flags: framework-specific flags + * @fixed_rate: non-adjustable clock rate + * @fixed_accuracy: non-adjustable clock accuracy +@@ -444,7 +444,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + * the clock framework + * @dev: device that is registering this clock + * @name: name of this clock +- * @parent_name: name of clock's parent ++ * @parent_data: name of clock's parent + * @flags: framework-specific flags + * @fixed_rate: non-adjustable clock rate + */ +@@ -580,7 +580,7 @@ struct clk_div_table { + * Clock with an adjustable divider affecting its output frequency. Implements + * .recalc_rate, .set_rate and .round_rate + * +- * Flags: ++ * @flags: + * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the + * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is + * the raw value read from the register, with the value of zero considered +@@ -945,11 +945,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); + * @mwidth: width of the numerator bit field + * @nshift: shift to the denominator bit field + * @nwidth: width of the denominator bit field ++ * @approximation: clk driver's callback for calculating the divider clock + * @lock: register lock + * + * Clock with adjustable fractional divider affecting its output frequency. + * +- * Flags: ++ * @flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read +@@ -1002,7 +1003,7 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw); + * Clock with an adjustable multiplier affecting its output frequency. + * Implements .recalc_rate, .set_rate and .round_rate + * +- * Flags: ++ * @flags: + * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read + * from the register, with 0 being a valid value effectively + * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is +-- +2.42.0 + diff --git a/queue-5.10/clk-mediatek-clk-mt2701-add-check-for-mtk_alloc_clk_.patch b/queue-5.10/clk-mediatek-clk-mt2701-add-check-for-mtk_alloc_clk_.patch new file mode 100644 index 00000000000..eb76ff542a1 --- /dev/null +++ b/queue-5.10/clk-mediatek-clk-mt2701-add-check-for-mtk_alloc_clk_.patch @@ -0,0 +1,66 @@ +From 5498fc2b55115d335d47eb6fcb0fa7c4079f5d78 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Sep 2023 10:46:58 +0800 +Subject: clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_data + +From: Jiasheng Jiang + +[ Upstream commit 0d6e24b422a2166a9297a8286ff2e6ab9a5e8cd3 ] + +Add the check for the return value of mtk_alloc_clk_data() in order to +avoid NULL pointer dereference. + +Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/20230901024658.23405-1-jiasheng@iscas.ac.cn +Reviewed-by: Markus Schneider-Pargmann +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/mediatek/clk-mt2701.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c +index 695be0f774270..c67cd73aca171 100644 +--- a/drivers/clk/mediatek/clk-mt2701.c ++++ b/drivers/clk/mediatek/clk-mt2701.c +@@ -675,6 +675,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_TOP_NR); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); +@@ -742,6 +744,8 @@ static void __init mtk_infrasys_init_early(struct device_node *node) + + if (!infra_clk_data) { + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); ++ if (!infra_clk_data) ++ return; + + for (i = 0; i < CLK_INFRA_NR; i++) + infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); +@@ -768,6 +772,8 @@ static int mtk_infrasys_init(struct platform_device *pdev) + + if (!infra_clk_data) { + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); ++ if (!infra_clk_data) ++ return -ENOMEM; + } else { + for (i = 0; i < CLK_INFRA_NR; i++) { + if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) +@@ -896,6 +902,8 @@ static int mtk_pericfg_init(struct platform_device *pdev) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_PERI_NR); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), + clk_data); +-- +2.42.0 + diff --git a/queue-5.10/clk-mediatek-clk-mt6765-add-check-for-mtk_alloc_clk_.patch b/queue-5.10/clk-mediatek-clk-mt6765-add-check-for-mtk_alloc_clk_.patch new file mode 100644 index 00000000000..6368a082d6a --- /dev/null +++ b/queue-5.10/clk-mediatek-clk-mt6765-add-check-for-mtk_alloc_clk_.patch @@ -0,0 +1,56 @@ +From 358e9d24aa9d4887bafac78ce651c1a6a397eb10 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Sep 2023 17:34:03 +0800 +Subject: clk: mediatek: clk-mt6765: Add check for mtk_alloc_clk_data + +From: Jiasheng Jiang + +[ Upstream commit b82681042724924ae3ba0f2f2eeec217fa31e830 ] + +Add the check for the return value of mtk_alloc_clk_data() in order to +avoid NULL pointer dereference. + +Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/20230912093407.21505-1-jiasheng@iscas.ac.cn +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/mediatek/clk-mt6765.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c +index d77ea5aff2920..17352342b6989 100644 +--- a/drivers/clk/mediatek/clk-mt6765.c ++++ b/drivers/clk/mediatek/clk-mt6765.c +@@ -785,6 +785,8 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev) + } + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + +@@ -820,6 +822,8 @@ static int clk_mt6765_top_probe(struct platform_device *pdev) + } + + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), + clk_data); +@@ -860,6 +864,8 @@ static int clk_mt6765_ifr_probe(struct platform_device *pdev) + } + + clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), + clk_data); +-- +2.42.0 + diff --git a/queue-5.10/clk-mediatek-clk-mt6779-add-check-for-mtk_alloc_clk_.patch b/queue-5.10/clk-mediatek-clk-mt6779-add-check-for-mtk_alloc_clk_.patch new file mode 100644 index 00000000000..1b399369776 --- /dev/null +++ b/queue-5.10/clk-mediatek-clk-mt6779-add-check-for-mtk_alloc_clk_.patch @@ -0,0 +1,47 @@ +From c89307390507a3c5c18f51775ffe289622f28fb9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Sep 2023 17:34:04 +0800 +Subject: clk: mediatek: clk-mt6779: Add check for mtk_alloc_clk_data + +From: Jiasheng Jiang + +[ Upstream commit 1f57f78fbacf630430bf954e5a84caafdfea30c0 ] + +Add the check for the return value of mtk_alloc_clk_data() in order to +avoid NULL pointer dereference. + +Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/20230912093407.21505-2-jiasheng@iscas.ac.cn +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/mediatek/clk-mt6779.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c +index 6e0d3a1667291..cf720651fc536 100644 +--- a/drivers/clk/mediatek/clk-mt6779.c ++++ b/drivers/clk/mediatek/clk-mt6779.c +@@ -1216,6 +1216,8 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev) + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + +@@ -1236,6 +1238,8 @@ static int clk_mt6779_top_probe(struct platform_device *pdev) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); +-- +2.42.0 + diff --git a/queue-5.10/clk-mediatek-clk-mt6797-add-check-for-mtk_alloc_clk_.patch b/queue-5.10/clk-mediatek-clk-mt6797-add-check-for-mtk_alloc_clk_.patch new file mode 100644 index 00000000000..32afd150e84 --- /dev/null +++ b/queue-5.10/clk-mediatek-clk-mt6797-add-check-for-mtk_alloc_clk_.patch @@ -0,0 +1,56 @@ +From 7ce1ede029e971fed4146eb6dee66b902d952e73 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Sep 2023 17:34:05 +0800 +Subject: clk: mediatek: clk-mt6797: Add check for mtk_alloc_clk_data + +From: Jiasheng Jiang + +[ Upstream commit 606f6366a35a3329545e38129804d65ef26ed7d2 ] + +Add the check for the return value of mtk_alloc_clk_data() in order to +avoid NULL pointer dereference. + +Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/20230912093407.21505-3-jiasheng@iscas.ac.cn +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/mediatek/clk-mt6797.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c +index 428eb24ffec55..98d456023f4e4 100644 +--- a/drivers/clk/mediatek/clk-mt6797.c ++++ b/drivers/clk/mediatek/clk-mt6797.c +@@ -391,6 +391,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_TOP_NR); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), + clk_data); +@@ -563,6 +565,8 @@ static void mtk_infrasys_init_early(struct device_node *node) + + if (!infra_clk_data) { + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); ++ if (!infra_clk_data) ++ return; + + for (i = 0; i < CLK_INFRA_NR; i++) + infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); +@@ -587,6 +591,8 @@ static int mtk_infrasys_init(struct platform_device *pdev) + + if (!infra_clk_data) { + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); ++ if (!infra_clk_data) ++ return -ENOMEM; + } else { + for (i = 0; i < CLK_INFRA_NR; i++) { + if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) +-- +2.42.0 + diff --git a/queue-5.10/clk-mediatek-clk-mt7629-add-check-for-mtk_alloc_clk_.patch b/queue-5.10/clk-mediatek-clk-mt7629-add-check-for-mtk_alloc_clk_.patch new file mode 100644 index 00000000000..1ede89dee91 --- /dev/null +++ b/queue-5.10/clk-mediatek-clk-mt7629-add-check-for-mtk_alloc_clk_.patch @@ -0,0 +1,56 @@ +From 7db60764657a907c3f6742bf1ba779b1f4102b5b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Sep 2023 17:34:07 +0800 +Subject: clk: mediatek: clk-mt7629: Add check for mtk_alloc_clk_data + +From: Jiasheng Jiang + +[ Upstream commit 2befa515c1bb6cdd33c262b909d93d1973a219aa ] + +Add the check for the return value of mtk_alloc_clk_data() in order to +avoid NULL pointer dereference. + +Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/20230912093407.21505-5-jiasheng@iscas.ac.cn +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/mediatek/clk-mt7629.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c +index a0ee079670c7e..f791e53b812ab 100644 +--- a/drivers/clk/mediatek/clk-mt7629.c ++++ b/drivers/clk/mediatek/clk-mt7629.c +@@ -580,6 +580,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); +@@ -603,6 +605,8 @@ static int mtk_infrasys_init(struct platform_device *pdev) + struct clk_onecell_data *clk_data; + + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + clk_data); +@@ -626,6 +630,8 @@ static int mtk_pericfg_init(struct platform_device *pdev) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), + clk_data); +-- +2.42.0 + diff --git a/queue-5.10/clk-mediatek-clk-mt7629-eth-add-check-for-mtk_alloc_.patch b/queue-5.10/clk-mediatek-clk-mt7629-eth-add-check-for-mtk_alloc_.patch new file mode 100644 index 00000000000..a7ca515eeb8 --- /dev/null +++ b/queue-5.10/clk-mediatek-clk-mt7629-eth-add-check-for-mtk_alloc_.patch @@ -0,0 +1,47 @@ +From 0236931555fb09a0a5bfe85b96897032a9a90b24 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Sep 2023 17:34:06 +0800 +Subject: clk: mediatek: clk-mt7629-eth: Add check for mtk_alloc_clk_data + +From: Jiasheng Jiang + +[ Upstream commit 0884393c63cc9a1772f7121a6645ba7bd76feeb9 ] + +Add the check for the return value of mtk_alloc_clk_data() in order to +avoid NULL pointer dereference. + +Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/20230912093407.21505-4-jiasheng@iscas.ac.cn +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/mediatek/clk-mt7629-eth.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c +index 88279d0ea1a76..3ab7b672f8c70 100644 +--- a/drivers/clk/mediatek/clk-mt7629-eth.c ++++ b/drivers/clk/mediatek/clk-mt7629-eth.c +@@ -83,6 +83,8 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) + int r; + + clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); + +@@ -105,6 +107,8 @@ static int clk_mt7629_sgmiisys_init(struct platform_device *pdev) + int r; + + clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; + + mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, + clk_data); +-- +2.42.0 + diff --git a/queue-5.10/clk-npcm7xx-fix-incorrect-kfree.patch b/queue-5.10/clk-npcm7xx-fix-incorrect-kfree.patch new file mode 100644 index 00000000000..81615e3859e --- /dev/null +++ b/queue-5.10/clk-npcm7xx-fix-incorrect-kfree.patch @@ -0,0 +1,45 @@ +From 638fea7b45b77368a8fa75effbe262aa630767ff Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 23 Sep 2023 15:31:27 +0200 +Subject: clk: npcm7xx: Fix incorrect kfree +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jonathan Neuschäfer + +[ Upstream commit bbc5080bef4a245106aa8e8d424ba8847ca7c0ca ] + +The corresponding allocation is: + +> npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws, +> NPCM7XX_NUM_CLOCKS), GFP_KERNEL); + +... so, kfree should be applied to npcm7xx_clk_data, not +npcm7xx_clk_data->hws. + +Fixes: fcfd14369856 ("clk: npcm7xx: add clock controller") +Signed-off-by: Jonathan Neuschäfer +Link: https://lore.kernel.org/r/20230923133127.1815621-1-j.neuschaefer@gmx.net +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-npcm7xx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c +index 27a86b7a34dbf..c82df105b0a21 100644 +--- a/drivers/clk/clk-npcm7xx.c ++++ b/drivers/clk/clk-npcm7xx.c +@@ -647,7 +647,7 @@ static void __init npcm7xx_clk_init(struct device_node *clk_np) + return; + + npcm7xx_init_fail: +- kfree(npcm7xx_clk_data->hws); ++ kfree(npcm7xx_clk_data); + npcm7xx_init_np_err: + iounmap(clk_base); + npcm7xx_init_error: +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-clk-rcg2-fix-clock-rate-overflow-for-high-p.patch b/queue-5.10/clk-qcom-clk-rcg2-fix-clock-rate-overflow-for-high-p.patch new file mode 100644 index 00000000000..d40320149e0 --- /dev/null +++ b/queue-5.10/clk-qcom-clk-rcg2-fix-clock-rate-overflow-for-high-p.patch @@ -0,0 +1,57 @@ +From 38aedfeea5f7421755062ef5da506f3deb760341 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Sep 2023 13:06:40 +0530 +Subject: clk: qcom: clk-rcg2: Fix clock rate overflow for high parent + frequencies + +From: Devi Priya + +[ Upstream commit f7b7d30158cff246667273bd2a62fc93ee0725d2 ] + +If the parent clock rate is greater than unsigned long max/2 then +integer overflow happens when calculating the clock rate on 32-bit systems. +As RCG2 uses half integer dividers, the clock rate is first being +multiplied by 2 which will overflow the unsigned long max value. +Hence, replace the common pattern of doing 64-bit multiplication +and then a do_div() call with simpler mult_frac call. + +Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") +Signed-off-by: Devi Priya +Reviewed-by: Marijn Suijten +Link: https://lore.kernel.org/r/20230901073640.4973-1-quic_devipriy@quicinc.com +[bjorn: Also drop unnecessary {} around single statements] +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/clk-rcg2.c | 14 ++++---------- + 1 file changed, 4 insertions(+), 10 deletions(-) + +diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c +index 71a0d30cf44df..eb4fd803bae0d 100644 +--- a/drivers/clk/qcom/clk-rcg2.c ++++ b/drivers/clk/qcom/clk-rcg2.c +@@ -147,17 +147,11 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) + static unsigned long + calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) + { +- if (hid_div) { +- rate *= 2; +- rate /= hid_div + 1; +- } ++ if (hid_div) ++ rate = mult_frac(rate, 2, hid_div + 1); + +- if (mode) { +- u64 tmp = rate; +- tmp *= m; +- do_div(tmp, n); +- rate = tmp; +- } ++ if (mode) ++ rate = mult_frac(rate, m, n); + + return rate; + } +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-config-ipq_apss_6018-should-depend-on-qcom_.patch b/queue-5.10/clk-qcom-config-ipq_apss_6018-should-depend-on-qcom_.patch new file mode 100644 index 00000000000..83890445804 --- /dev/null +++ b/queue-5.10/clk-qcom-config-ipq_apss_6018-should-depend-on-qcom_.patch @@ -0,0 +1,41 @@ +From 6ec57772c02f78f8b12cbcb325204299678a21d7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 Oct 2023 11:49:31 +0530 +Subject: clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM + +From: Varadarajan Narayanan + +[ Upstream commit 6a15647d0adc686226045e8046369f34d6ab03ed ] + +The config IPQ_APSS_6018 should depend on QCOM_SMEM, to +avoid the following error reported by 'kernel test robot' + + loongarch64-linux-ld: drivers/clk/qcom/apss-ipq6018.o: in function `apss_ipq6018_probe': + >> apss-ipq6018.c:(.text+0xd0): undefined reference to `qcom_smem_get_soc_id' + +Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/r/202310181650.g8THtfsm-lkp@intel.com/ +Signed-off-by: Varadarajan Narayanan +Link: https://lore.kernel.org/r/f4c4d65a7cb71e807d6d472c63c7718408c8f5f0.1697781921.git.quic_varada@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig +index 3a965bd326d5f..3998e25c4192f 100644 +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -110,6 +110,7 @@ config IPQ_APSS_6018 + tristate "IPQ APSS Clock Controller" + select IPQ_APSS_PLL + depends on QCOM_APCS_IPC || COMPILE_TEST ++ depends on QCOM_SMEM + help + Support for APSS clock controller on IPQ platforms. The + APSS clock controller manages the Mux and enable block that feeds the +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-gcc-msm8996-drop-unsupported-clock-sources.patch b/queue-5.10/clk-qcom-gcc-msm8996-drop-unsupported-clock-sources.patch new file mode 100644 index 00000000000..9ddb8c46f00 --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-msm8996-drop-unsupported-clock-sources.patch @@ -0,0 +1,123 @@ +From 0dfa9ebb251240ebcef8877e48d2a5c4fdb19c5b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Dec 2021 07:54:12 +0300 +Subject: clk: qcom: gcc-msm8996: drop unsupported clock sources + +From: Dmitry Baryshkov + +[ Upstream commit b554a687b4971ae137e92ee3feddc38e85a38d60 ] + +In preparation of updating the msm8996 gcc driver, drop all unsupported +GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3). +Downstream kernel also does not provide support for these GPLL sources, +so it is safe to drop them. + +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org +Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-msm8996.c | 55 ++++------------------------------ + 1 file changed, 6 insertions(+), 49 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c +index d95814025c65e..4c85b3935a819 100644 +--- a/drivers/clk/qcom/gcc-msm8996.c ++++ b/drivers/clk/qcom/gcc-msm8996.c +@@ -27,15 +27,10 @@ + enum { + P_XO, + P_GPLL0, +- P_GPLL2, +- P_GPLL3, +- P_GPLL1, +- P_GPLL2_EARLY, + P_GPLL0_EARLY_DIV, + P_SLEEP_CLK, + P_GPLL4, + P_AUD_REF_CLK, +- P_GPLL1_EARLY_DIV + }; + + static const struct parent_map gcc_sleep_clk_map[] = { +@@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { + "gpll0_early_div" + }; + +-static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL1_EARLY_DIV, 3 }, +- { P_GPLL1, 4 }, +- { P_GPLL4, 5 }, +- { P_GPLL0_EARLY_DIV, 6 } +-}; +- +-static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll1_early_div", +- "gpll1", +- "gpll4", +- "gpll0_early_div" +-}; +- +-static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL2, 2 }, +- { P_GPLL3, 3 }, +- { P_GPLL1, 4 }, +- { P_GPLL2_EARLY, 5 }, +- { P_GPLL0_EARLY_DIV, 6 } +-}; +- +-static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll2", +- "gpll3", +- "gpll1", +- "gpll2_early", +- "gpll0_early_div" +-}; +- + static struct clk_fixed_factor xo = { + .mult = 1, + .div = 1, +@@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = { + static struct clk_rcg2 system_noc_clk_src = { + .cmd_rcgr = 0x0401c, + .hid_width = 5, +- .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map, ++ .parent_map = gcc_xo_gpll0_gpll0_early_div_map, + .freq_tbl = ftbl_system_noc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_clk_src", +- .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, +- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div), ++ .parent_names = gcc_xo_gpll0_gpll0_early_div, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { + static struct clk_rcg2 qspi_ser_clk_src = { + .cmd_rcgr = 0x8b00c, + .hid_width = 5, +- .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map, ++ .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map, + .freq_tbl = ftbl_qspi_ser_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", +- .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, +- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div), ++ .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-gcc-msm8996-move-clock-parent-tables-down.patch b/queue-5.10/clk-qcom-gcc-msm8996-move-clock-parent-tables-down.patch new file mode 100644 index 00000000000..180ba77701b --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-msm8996-move-clock-parent-tables-down.patch @@ -0,0 +1,228 @@ +From 3bee5dfab0b5aad9aa78a9ad9b322f763d616f27 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Dec 2021 07:54:13 +0300 +Subject: clk: qcom: gcc-msm8996: move clock parent tables down + +From: Dmitry Baryshkov + +[ Upstream commit 1a2789cff03ccdeb70084157387f4a7bf4d2099f ] + +Move clock parent tables down, after the GPLL declrataions, so that we +can use gpll hw clock fields in the next commit. + +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Marijn Suijten +Reviewed-by: Stephen Boyd +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20211228045415.20543-15-dmitry.baryshkov@linaro.org +Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-msm8996.c | 184 ++++++++++++++++----------------- + 1 file changed, 92 insertions(+), 92 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c +index 4c85b3935a819..8531f2f3665fe 100644 +--- a/drivers/clk/qcom/gcc-msm8996.c ++++ b/drivers/clk/qcom/gcc-msm8996.c +@@ -33,98 +33,6 @@ enum { + P_AUD_REF_CLK, + }; + +-static const struct parent_map gcc_sleep_clk_map[] = { +- { P_SLEEP_CLK, 5 } +-}; +- +-static const char * const gcc_sleep_clk[] = { +- "sleep_clk" +-}; +- +-static const struct parent_map gcc_xo_gpll0_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 } +-}; +- +-static const char * const gcc_xo_gpll0[] = { +- "xo", +- "gpll0" +-}; +- +-static const struct parent_map gcc_xo_sleep_clk_map[] = { +- { P_XO, 0 }, +- { P_SLEEP_CLK, 5 } +-}; +- +-static const char * const gcc_xo_sleep_clk[] = { +- "xo", +- "sleep_clk" +-}; +- +-static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL0_EARLY_DIV, 6 } +-}; +- +-static const char * const gcc_xo_gpll0_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll0_early_div" +-}; +- +-static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL4, 5 } +-}; +- +-static const char * const gcc_xo_gpll0_gpll4[] = { +- "xo", +- "gpll0", +- "gpll4" +-}; +- +-static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_AUD_REF_CLK, 2 } +-}; +- +-static const char * const gcc_xo_gpll0_aud_ref_clk[] = { +- "xo", +- "gpll0", +- "aud_ref_clk" +-}; +- +-static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_SLEEP_CLK, 5 }, +- { P_GPLL0_EARLY_DIV, 6 } +-}; +- +-static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "sleep_clk", +- "gpll0_early_div" +-}; +- +-static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL4, 5 }, +- { P_GPLL0_EARLY_DIV, 6 } +-}; +- +-static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll4", +- "gpll0_early_div" +-}; +- + static struct clk_fixed_factor xo = { + .mult = 1, + .div = 1, +@@ -229,6 +137,98 @@ static struct clk_alpha_pll_postdiv gpll4 = { + }, + }; + ++static const struct parent_map gcc_sleep_clk_map[] = { ++ { P_SLEEP_CLK, 5 } ++}; ++ ++static const char * const gcc_sleep_clk[] = { ++ "sleep_clk" ++}; ++ ++static const struct parent_map gcc_xo_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 } ++}; ++ ++static const char * const gcc_xo_gpll0[] = { ++ "xo", ++ "gpll0" ++}; ++ ++static const struct parent_map gcc_xo_sleep_clk_map[] = { ++ { P_XO, 0 }, ++ { P_SLEEP_CLK, 5 } ++}; ++ ++static const char * const gcc_xo_sleep_clk[] = { ++ "xo", ++ "sleep_clk" ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_EARLY_DIV, 6 } ++}; ++ ++static const char * const gcc_xo_gpll0_gpll0_early_div[] = { ++ "xo", ++ "gpll0", ++ "gpll0_early_div" ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 5 } ++}; ++ ++static const char * const gcc_xo_gpll0_gpll4[] = { ++ "xo", ++ "gpll0", ++ "gpll4" ++}; ++ ++static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_AUD_REF_CLK, 2 } ++}; ++ ++static const char * const gcc_xo_gpll0_aud_ref_clk[] = { ++ "xo", ++ "gpll0", ++ "aud_ref_clk" ++}; ++ ++static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_SLEEP_CLK, 5 }, ++ { P_GPLL0_EARLY_DIV, 6 } ++}; ++ ++static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { ++ "xo", ++ "gpll0", ++ "sleep_clk", ++ "gpll0_early_div" ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 5 }, ++ { P_GPLL0_EARLY_DIV, 6 } ++}; ++ ++static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { ++ "xo", ++ "gpll0", ++ "gpll4", ++ "gpll0_early_div" ++}; ++ + static const struct freq_tbl ftbl_system_noc_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-gcc-msm8996-remove-rpm-bus-clocks.patch b/queue-5.10/clk-qcom-gcc-msm8996-remove-rpm-bus-clocks.patch new file mode 100644 index 00000000000..9e23d54321b --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-msm8996-remove-rpm-bus-clocks.patch @@ -0,0 +1,521 @@ +From 6ccd83d3606d1c7bc50f28cda2ebf5be59c53e25 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 31 Aug 2023 11:39:14 +0200 +Subject: clk: qcom: gcc-msm8996: Remove RPM bus clocks + +From: Konrad Dybcio + +[ Upstream commit 4afda5f6bcdf673ef2556fcfa458daf3a5a648d8 ] + +The GCC driver contains clocks that are owned (meaning configured and +scaled) by the RPM core. + +Remove them from Linux to stop interjecting the RPM's logic. + +Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") +Signed-off-by: Konrad Dybcio +Reviewed-by: Dmitry Baryshkov +Tested-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230830-topic-rpmbusclocks8996gcc-v1-1-9e99bedcdc3b@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-msm8996.c | 237 +-------------------------------- + 1 file changed, 5 insertions(+), 232 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c +index 6b36024583b4a..2d79a73da1055 100644 +--- a/drivers/clk/qcom/gcc-msm8996.c ++++ b/drivers/clk/qcom/gcc-msm8996.c +@@ -245,71 +245,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = { + { .hw = &gpll0_early_div.hw } + }; + +-static const struct freq_tbl ftbl_system_noc_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), +- F(100000000, P_GPLL0, 6, 0, 0), +- F(150000000, P_GPLL0, 4, 0, 0), +- F(200000000, P_GPLL0, 3, 0, 0), +- F(240000000, P_GPLL0, 2.5, 0, 0), +- { } +-}; +- +-static struct clk_rcg2 system_noc_clk_src = { +- .cmd_rcgr = 0x0401c, +- .hid_width = 5, +- .parent_map = gcc_xo_gpll0_gpll0_early_div_map, +- .freq_tbl = ftbl_system_noc_clk_src, +- .clkr.hw.init = &(struct clk_init_data){ +- .name = "system_noc_clk_src", +- .parent_data = gcc_xo_gpll0_gpll0_early_div, +- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), +- .ops = &clk_rcg2_ops, +- }, +-}; +- +-static const struct freq_tbl ftbl_config_noc_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(37500000, P_GPLL0, 16, 0, 0), +- F(75000000, P_GPLL0, 8, 0, 0), +- { } +-}; +- +-static struct clk_rcg2 config_noc_clk_src = { +- .cmd_rcgr = 0x0500c, +- .hid_width = 5, +- .parent_map = gcc_xo_gpll0_map, +- .freq_tbl = ftbl_config_noc_clk_src, +- .clkr.hw.init = &(struct clk_init_data){ +- .name = "config_noc_clk_src", +- .parent_data = gcc_xo_gpll0, +- .num_parents = ARRAY_SIZE(gcc_xo_gpll0), +- .ops = &clk_rcg2_ops, +- }, +-}; +- +-static const struct freq_tbl ftbl_periph_noc_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(37500000, P_GPLL0, 16, 0, 0), +- F(50000000, P_GPLL0, 12, 0, 0), +- F(75000000, P_GPLL0, 8, 0, 0), +- F(100000000, P_GPLL0, 6, 0, 0), +- { } +-}; +- +-static struct clk_rcg2 periph_noc_clk_src = { +- .cmd_rcgr = 0x06014, +- .hid_width = 5, +- .parent_map = gcc_xo_gpll0_map, +- .freq_tbl = ftbl_periph_noc_clk_src, +- .clkr.hw.init = &(struct clk_init_data){ +- .name = "periph_noc_clk_src", +- .parent_data = gcc_xo_gpll0, +- .num_parents = ARRAY_SIZE(gcc_xo_gpll0), +- .ops = &clk_rcg2_ops, +- }, +-}; +- + static const struct freq_tbl ftbl_usb30_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(120000000, P_GPLL0, 5, 0, 0), +@@ -1298,11 +1233,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_noc_cfg_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .flags = CLK_IGNORE_UNUSED, + .ops = &clk_branch2_ops, + }, + }, +@@ -1465,11 +1396,6 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_phy_cfg_ahb2phy_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -1499,11 +1425,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -1550,11 +1471,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -1584,11 +1500,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc3_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -1618,11 +1529,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc4_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -1636,11 +1542,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = { + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -1978,11 +1879,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = { + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2319,11 +2215,6 @@ static struct clk_branch gcc_pdm_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2354,11 +2245,6 @@ static struct clk_branch gcc_prng_ahb_clk = { + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2371,11 +2257,6 @@ static struct clk_branch gcc_tsif_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2423,11 +2304,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2521,11 +2397,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_slv_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2538,11 +2409,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_mstr_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2555,11 +2421,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_cfg_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2607,11 +2468,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_slv_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2624,11 +2480,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_mstr_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2641,11 +2492,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_cfg_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2693,11 +2539,6 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_slv_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2710,11 +2551,6 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_mstr_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2727,11 +2563,6 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_cfg_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2779,11 +2610,6 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_phy_cfg_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2830,11 +2656,6 @@ static struct clk_branch gcc_ufs_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -3061,11 +2882,7 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre0_snoc_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +@@ -3078,11 +2895,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre0_cnoc_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +@@ -3095,11 +2908,7 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_smmu_aggre0_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +@@ -3112,11 +2921,7 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_smmu_aggre0_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +@@ -3163,10 +2968,6 @@ static struct clk_branch gcc_dcc_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_dcc_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +@@ -3179,10 +2980,6 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +@@ -3195,11 +2992,6 @@ static struct clk_branch gcc_qspi_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &periph_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -3348,10 +3140,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_cfg_ahb_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &config_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +@@ -3364,10 +3152,6 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_mnoc_bimc_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +@@ -3380,10 +3164,6 @@ static struct clk_branch gcc_mss_snoc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_snoc_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +@@ -3396,10 +3176,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_q6_bimc_axi_clk", +- .parent_hws = (const struct clk_hw*[]){ +- &system_noc_clk_src.clkr.hw, +- }, +- .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +@@ -3495,9 +3271,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = { + [GPLL0] = &gpll0.clkr, + [GPLL4_EARLY] = &gpll4_early.clkr, + [GPLL4] = &gpll4.clkr, +- [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, +- [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, +- [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-gcc-msm8996-use-array_size-instead-of-speci.patch b/queue-5.10/clk-qcom-gcc-msm8996-use-array_size-instead-of-speci.patch new file mode 100644 index 00000000000..76fe06fbd00 --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-msm8996-use-array_size-instead-of-speci.patch @@ -0,0 +1,579 @@ +From c4230c7cbbd3a56e1203f942c449d429d0f7e522 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Dec 2021 07:54:11 +0300 +Subject: clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying + num_parents + +From: Dmitry Baryshkov + +[ Upstream commit ed96df3d461eeb2c40cb06ca5fd51644d0f4a2c0 ] + +Use ARRAY_SIZE() instead of manually specifying num_parents. This makes +adding/removing entries to/from parent_data easy and errorproof. + +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Marijn Suijten +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20211228045415.20543-13-dmitry.baryshkov@linaro.org +Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++----------------- + 1 file changed, 61 insertions(+), 61 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c +index 9b1674b28d45d..d95814025c65e 100644 +--- a/drivers/clk/qcom/gcc-msm8996.c ++++ b/drivers/clk/qcom/gcc-msm8996.c +@@ -290,7 +290,7 @@ static struct clk_rcg2 system_noc_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_clk_src", + .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, +- .num_parents = 7, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -310,7 +310,7 @@ static struct clk_rcg2 config_noc_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "config_noc_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -332,7 +332,7 @@ static struct clk_rcg2 periph_noc_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "periph_noc_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -353,7 +353,7 @@ static struct clk_rcg2 usb30_master_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_master_clk_src", + .parent_names = gcc_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -371,7 +371,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_mock_utmi_clk_src", + .parent_names = gcc_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -389,7 +389,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb3_phy_aux_clk_src", + .parent_names = gcc_xo_sleep_clk, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), + .ops = &clk_rcg2_ops, + }, + }; +@@ -408,7 +408,7 @@ static struct clk_rcg2 usb20_master_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_master_clk_src", + .parent_names = gcc_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -421,7 +421,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_mock_utmi_clk_src", + .parent_names = gcc_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -447,7 +447,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", + .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_floor_ops, + }, + }; +@@ -467,7 +467,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", + .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -492,7 +492,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", + .parent_names = gcc_xo_gpll0_gpll4, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), + .ops = &clk_rcg2_floor_ops, + }, + }; +@@ -506,7 +506,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc3_apps_clk_src", + .parent_names = gcc_xo_gpll0_gpll4, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), + .ops = &clk_rcg2_floor_ops, + }, + }; +@@ -530,7 +530,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc4_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_floor_ops, + }, + }; +@@ -555,7 +555,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -574,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -634,7 +634,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -675,7 +675,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart3_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -716,7 +716,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart4_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -757,7 +757,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart5_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -798,7 +798,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -812,7 +812,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart6_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -839,7 +839,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart1_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -880,7 +880,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart2_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -921,7 +921,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart3_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -962,7 +962,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart4_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup5_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1003,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup5_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart5_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup6_spi_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1044,7 +1044,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup6_i2c_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1058,7 +1058,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart6_apps_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1076,7 +1076,7 @@ static struct clk_rcg2 pdm2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1095,7 +1095,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "tsif_ref_clk_src", + .parent_names = gcc_xo_gpll0_aud_ref_clk, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1107,7 +1107,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sleep_clk_src", + .parent_names = gcc_sleep_clk, +- .num_parents = 1, ++ .num_parents = ARRAY_SIZE(gcc_sleep_clk), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1120,7 +1120,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_rbcpr_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1132,7 +1132,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll0_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1153,7 +1153,7 @@ static struct clk_rcg2 gp1_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", + .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1167,7 +1167,7 @@ static struct clk_rcg2 gp2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", + .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1181,7 +1181,7 @@ static struct clk_rcg2 gp3_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", + .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1200,7 +1200,7 @@ static struct clk_rcg2 pcie_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcie_aux_clk_src", + .parent_names = gcc_xo_sleep_clk, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1221,7 +1221,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_axi_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1241,7 +1241,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_clk_src", + .parent_names = gcc_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -1262,7 +1262,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", + .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, +- .num_parents = 6, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-gcc-msm8996-use-parent_hws-_data-instead-of.patch b/queue-5.10/clk-qcom-gcc-msm8996-use-parent_hws-_data-instead-of.patch new file mode 100644 index 00000000000..b8a81bfd019 --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-msm8996-use-parent_hws-_data-instead-of.patch @@ -0,0 +1,2060 @@ +From 53f0f100154c9d71ca6b983b88fa6a71330270c6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Dec 2021 07:54:14 +0300 +Subject: clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names + +From: Dmitry Baryshkov + +[ Upstream commit b3867679d460d67aaef5aa76e4512197a5375514 ] + +Convert the clock driver to specify parent data rather than parent +names, to actually bind using 'clock-names' specified in the DTS rather +than global clock names. Use parent_hws where possible to refer parent +clocks directly, skipping the lookup. + +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Marijn Suijten +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20211228045415.20543-16-dmitry.baryshkov@linaro.org +Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++----------- + 1 file changed, 463 insertions(+), 215 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c +index 8531f2f3665fe..6b36024583b4a 100644 +--- a/drivers/clk/qcom/gcc-msm8996.c ++++ b/drivers/clk/qcom/gcc-msm8996.c +@@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = { + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "xo", +- .parent_names = (const char *[]){ "xo_board" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "cxo", .name = "xo_board", ++ }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +@@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_early", +- .parent_names = (const char *[]){ "xo" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &xo.hw, ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, +@@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = { + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_early_div", +- .parent_names = (const char *[]){ "gpll0_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll0_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +@@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = { + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0", +- .parent_names = (const char *[]){ "gpll0_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll0_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ops, + }, +@@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_div_clk", +- .parent_names = (const char *[]){ "gpll0" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll0.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = { + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_gpll0_div_clk", +- .parent_names = (const char *[]){ "gpll0" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll0.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops +@@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = { + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_early", +- .parent_names = (const char *[]){ "xo" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &xo.hw, ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, +@@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = { + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", +- .parent_names = (const char *[]){ "gpll4_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll4_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ops, + }, +@@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = { + { P_SLEEP_CLK, 5 } + }; + +-static const char * const gcc_sleep_clk[] = { +- "sleep_clk" ++static const struct clk_parent_data gcc_sleep_clk[] = { ++ { .fw_name = "sleep_clk", .name = "sleep_clk" } + }; + + static const struct parent_map gcc_xo_gpll0_map[] = { +@@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = { + { P_GPLL0, 1 } + }; + +-static const char * const gcc_xo_gpll0[] = { +- "xo", +- "gpll0" ++static const struct clk_parent_data gcc_xo_gpll0[] = { ++ { .hw = &xo.hw }, ++ { .hw = &gpll0.clkr.hw } + }; + + static const struct parent_map gcc_xo_sleep_clk_map[] = { +@@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = { + { P_SLEEP_CLK, 5 } + }; + +-static const char * const gcc_xo_sleep_clk[] = { +- "xo", +- "sleep_clk" ++static const struct clk_parent_data gcc_xo_sleep_clk[] = { ++ { .hw = &xo.hw }, ++ { .fw_name = "sleep_clk", .name = "sleep_clk" } + }; + + static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { +@@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { + { P_GPLL0_EARLY_DIV, 6 } + }; + +-static const char * const gcc_xo_gpll0_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll0_early_div" ++static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = { ++ { .hw = &xo.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_early_div.hw } + }; + + static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { +@@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_GPLL4, 5 } + }; + +-static const char * const gcc_xo_gpll0_gpll4[] = { +- "xo", +- "gpll0", +- "gpll4" ++static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { ++ { .hw = &xo.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll4.clkr.hw } + }; + + static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { +@@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { + { P_AUD_REF_CLK, 2 } + }; + +-static const char * const gcc_xo_gpll0_aud_ref_clk[] = { +- "xo", +- "gpll0", +- "aud_ref_clk" ++static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = { ++ { .hw = &xo.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" } + }; + + static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { +@@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { + { P_GPLL0_EARLY_DIV, 6 } + }; + +-static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "sleep_clk", +- "gpll0_early_div" ++static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { ++ { .hw = &xo.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .fw_name = "sleep_clk", .name = "sleep_clk" }, ++ { .hw = &gpll0_early_div.hw } + }; + + static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { +@@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { + { P_GPLL0_EARLY_DIV, 6 } + }; + +-static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll4", +- "gpll0_early_div" ++static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = { ++ { .hw = &xo.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll4.clkr.hw }, ++ { .hw = &gpll0_early_div.hw } + }; + + static const struct freq_tbl ftbl_system_noc_clk_src[] = { +@@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = { + .freq_tbl = ftbl_system_noc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_clk_src", +- .parent_names = gcc_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = { + .freq_tbl = ftbl_config_noc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "config_noc_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = { + .freq_tbl = ftbl_periph_noc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "periph_noc_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = { + .freq_tbl = ftbl_usb30_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_master_clk_src", +- .parent_names = gcc_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_mock_utmi_clk_src", +- .parent_names = gcc_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { + .freq_tbl = ftbl_usb3_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb3_phy_aux_clk_src", +- .parent_names = gcc_xo_sleep_clk, ++ .parent_data = gcc_xo_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), + .ops = &clk_rcg2_ops, + }, +@@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = { + .freq_tbl = ftbl_usb20_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_master_clk_src", +- .parent_names = gcc_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_mock_utmi_clk_src", +- .parent_names = gcc_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { + .freq_tbl = ftbl_sdcc1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", +- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_floor_ops, + }, +@@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .freq_tbl = ftbl_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", +- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { + .freq_tbl = ftbl_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", +- .parent_names = gcc_xo_gpll0_gpll4, ++ .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), + .ops = &clk_rcg2_floor_ops, + }, +@@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { + .freq_tbl = ftbl_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc3_apps_clk_src", +- .parent_names = gcc_xo_gpll0_gpll4, ++ .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), + .ops = &clk_rcg2_floor_ops, + }, +@@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { + .freq_tbl = ftbl_sdcc4_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc4_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_floor_ops, + }, +@@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart3_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart4_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart5_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart6_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart1_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart2_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart3_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart4_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup5_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup5_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart5_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup6_spi_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup6_i2c_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart6_apps_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = { + .freq_tbl = ftbl_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { + .freq_tbl = ftbl_tsif_ref_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "tsif_ref_clk_src", +- .parent_names = gcc_xo_gpll0_aud_ref_clk, ++ .parent_data = gcc_xo_gpll0_aud_ref_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), + .ops = &clk_rcg2_ops, + }, +@@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = { + .parent_map = gcc_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sleep_clk_src", +- .parent_names = gcc_sleep_clk, ++ .parent_data = gcc_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_sleep_clk), + .ops = &clk_rcg2_ops, + }, +@@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_rbcpr_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll0_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = { + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", +- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = { + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", +- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = { + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", +- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = { + .freq_tbl = ftbl_pcie_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcie_aux_clk_src", +- .parent_names = gcc_xo_sleep_clk, ++ .parent_data = gcc_xo_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), + .ops = &clk_rcg2_ops, + }, +@@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { + .freq_tbl = ftbl_ufs_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_axi_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { + .freq_tbl = ftbl_ufs_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_clk_src", +- .parent_names = gcc_xo_gpll0, ++ .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +@@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { + .freq_tbl = ftbl_qspi_ser_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", +- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, ++ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, +@@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_usb3_axi_clk", +- .parent_names = (const char *[]){ "usb30_master_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_ufs_axi_clk", +- .parent_names = (const char *[]){ "ufs_axi_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_axi_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_periph_noc_usb20_ahb_clk", +- .parent_names = (const char *[]){ "usb20_master_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb20_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_noc_cfg_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .ops = &clk_branch2_ops, +@@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_master_clk", +- .parent_names = (const char *[]){ "usb30_master_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sleep_clk", +- .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gcc_sleep_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mock_utmi_clk", +- .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_mock_utmi_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_aux_clk", +- .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb3_phy_aux_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_pipe_clk", +- .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src", ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_master_clk", +- .parent_names = (const char *[]){ "usb20_master_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb20_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_sleep_clk", +- .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gcc_sleep_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_mock_utmi_clk", +- .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb20_mock_utmi_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_phy_cfg_ahb2phy_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", +- .parent_names = (const char *[]){ "sdcc1_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdcc1_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", +- .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdcc1_ice_core_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", +- .parent_names = (const char *[]){ "sdcc2_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdcc2_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc3_apps_clk", +- .parent_names = (const char *[]){ "sdcc3_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdcc3_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc3_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc4_apps_clk", +- .parent_names = (const char *[]){ "sdcc4_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdcc4_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc4_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = { + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = { + .enable_mask = BIT(16), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_sleep_clk", +- .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gcc_sleep_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup1_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup1_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", +- .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_uart1_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup2_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup2_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", +- .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_uart2_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup3_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup3_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart3_apps_clk", +- .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_uart3_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup4_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup4_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart4_apps_clk", +- .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_uart4_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup5_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup5_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup5_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup5_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart5_apps_clk", +- .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_uart5_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup6_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup6_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup6_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_qup6_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart6_apps_clk", +- .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp1_uart6_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = { + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = { + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_sleep_clk", +- .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gcc_sleep_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup1_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup1_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart1_apps_clk", +- .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_uart1_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup2_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup2_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart2_apps_clk", +- .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_uart2_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup3_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup3_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart3_apps_clk", +- .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_uart3_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup4_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup4_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart4_apps_clk", +- .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_uart4_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup5_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup5_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup5_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup5_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart5_apps_clk", +- .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_uart5_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup6_spi_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup6_spi_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup6_i2c_apps_clk", +- .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_qup6_i2c_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart6_apps_clk", +- .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &blsp2_uart6_apps_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", +- .parent_names = (const char *[]){ "pdm2_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pdm2_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = { + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_ref_clk", +- .parent_names = (const char *[]){ "tsif_ref_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &tsif_ref_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_inactivity_timers_clk", +- .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gcc_sleep_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_rbcpr_clk", +- .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &hmss_rbcpr_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", +- .parent_names = (const char *[]){ "gp1_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp1_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", +- .parent_names = (const char *[]){ "gp2_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp2_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", +- .parent_names = (const char *[]){ "gp3_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp3_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_slv_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_mstr_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_cfg_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_aux_clk", +- .parent_names = (const char *[]){ "pcie_aux_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie_aux_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_pipe_clk", +- .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src", ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_slv_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_mstr_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_cfg_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_aux_clk", +- .parent_names = (const char *[]){ "pcie_aux_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie_aux_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_pipe_clk", +- .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src", ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_slv_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_mstr_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_cfg_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_aux_clk", +- .parent_names = (const char *[]){ "pcie_aux_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie_aux_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_pipe_clk", +- .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src", ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_phy_cfg_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_phy_aux_clk", +- .parent_names = (const char *[]){ "pcie_aux_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie_aux_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_clk", +- .parent_names = (const char *[]){ "ufs_axi_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_axi_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = { + .div = 16, + .hw.init = &(struct clk_init_data){ + .name = "ufs_tx_cfg_clk_src", +- .parent_names = (const char *[]){ "ufs_axi_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_axi_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, +@@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_tx_cfg_clk", +- .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_tx_cfg_clk_src.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = { + .div = 16, + .hw.init = &(struct clk_init_data){ + .name = "ufs_rx_cfg_clk_src", +- .parent_names = (const char *[]){ "ufs_axi_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_axi_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, +@@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_cfg_clk", +- .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_rx_cfg_clk_src.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_tx_symbol_0_clk", +- .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src", ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_0_clk", +- .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src", ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_1_clk", +- .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src", ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = { + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_postdiv_clk_src", +- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_ice_core_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, +@@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_clk", +- .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_ice_core_postdiv_clk_src.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_clk", +- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_ice_core_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre0_snoc_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, +@@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre0_cnoc_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, +@@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_smmu_aggre0_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, +@@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_smmu_aggre0_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, +@@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_ufs_axi_clk", +- .parent_names = (const char *[]){ "ufs_axi_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &ufs_axi_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_usb3_axi_clk", +- .parent_names = (const char *[]){ "usb30_master_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_dcc_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, +@@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, +@@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ahb_clk", +- .parent_names = (const char *[]){ "periph_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &periph_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ser_clk", +- .parent_names = (const char *[]){ "qspi_ser_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &qspi_ser_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, +@@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_cfg_ahb_clk", +- .parent_names = (const char *[]){ "config_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &config_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, +@@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_mnoc_bimc_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, +@@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_snoc_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, +@@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_q6_bimc_axi_clk", +- .parent_names = (const char *[]){ "system_noc_clk_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &system_noc_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-gcc-sm8150-fix-gcc_sdcc2_apps_clk_src.patch b/queue-5.10/clk-qcom-gcc-sm8150-fix-gcc_sdcc2_apps_clk_src.patch new file mode 100644 index 00000000000..1146d1fe0ba --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-sm8150-fix-gcc_sdcc2_apps_clk_src.patch @@ -0,0 +1,39 @@ +From f6907d37e3fc45605b516e6d4290afd76729cc8c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Sep 2023 20:56:11 +0300 +Subject: clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src + +From: Danila Tikhonov + +[ Upstream commit 7138c244fb293f24ce8ab782961022eff00a10c4 ] + +Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg +didn't update its configuration" error. + +Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") +Tested-by: Arseniy Velikanov +Signed-off-by: Danila Tikhonov +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230913175612.8685-1-danila@jiaxyga.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sm8150.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c +index dc25c40984f27..3d9ba3ccb6b68 100644 +--- a/drivers/clk/qcom/gcc-sm8150.c ++++ b/drivers/clk/qcom/gcc-sm8150.c +@@ -792,7 +792,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .name = "gcc_sdcc2_apps_clk_src", + .parent_data = gcc_parents_6, + .num_parents = ARRAY_SIZE(gcc_parents_6), +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_floor_ops, + }, + }; +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-gcc-sm8150-use-array_size-instead-of-specif.patch b/queue-5.10/clk-qcom-gcc-sm8150-use-array_size-instead-of-specif.patch new file mode 100644 index 00000000000..7bf3b6e467c --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-sm8150-use-array_size-instead-of-specif.patch @@ -0,0 +1,461 @@ +From 5b65d577b34fbfa10944e5b1f19b8d8f97cc466c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Apr 2021 01:47:41 +0300 +Subject: clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying + num_parents + +From: Dmitry Baryshkov + +[ Upstream commit 60ca4670fd6436c07cea38472ebcee3b00f03bc7 ] + +Use ARRAY_SIZE() instead of manually specifying num_parents. This makes +adding/removing entries to/from parent_data easy and errorproof. + +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20210405224743.590029-32-dmitry.baryshkov@linaro.org +Signed-off-by: Stephen Boyd +Stable-dep-of: 7138c244fb29 ("clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sm8150.c | 96 +++++++++++++++++------------------ + 1 file changed, 48 insertions(+), 48 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c +index 8e9b5b3cceaf7..dc25c40984f27 100644 +--- a/drivers/clk/qcom/gcc-sm8150.c ++++ b/drivers/clk/qcom/gcc-sm8150.c +@@ -241,7 +241,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -264,7 +264,7 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_emac_ptp_clk_src", + .parent_data = gcc_parents_5, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_parents_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -290,7 +290,7 @@ static struct clk_rcg2 gcc_emac_rgmii_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_emac_rgmii_clk_src", + .parent_data = gcc_parents_5, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_parents_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -314,7 +314,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parents_1, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_parents_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -329,7 +329,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parents_1, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_parents_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -344,7 +344,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk_src", + .parent_data = gcc_parents_1, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_parents_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -365,7 +365,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_aux_clk_src", + .parent_data = gcc_parents_2, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parents_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -380,7 +380,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_aux_clk_src", + .parent_data = gcc_parents_2, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parents_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_phy_refgen_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -423,7 +423,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -446,7 +446,7 @@ static struct clk_rcg2 gcc_qspi_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_core_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -480,7 +480,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -495,7 +495,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -510,7 +510,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -525,7 +525,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -540,7 +540,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -555,7 +555,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -570,7 +570,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s6_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -585,7 +585,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s7_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s0_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -615,7 +615,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s1_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -630,7 +630,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s2_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -645,7 +645,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s3_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -660,7 +660,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s4_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -675,7 +675,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s5_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -690,7 +690,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s0_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -705,7 +705,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s1_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -720,7 +720,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s2_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -735,7 +735,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s3_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -750,7 +750,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s4_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -765,7 +765,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s5_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -791,7 +791,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk_src", + .parent_data = gcc_parents_6, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_parents_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_floor_ops, + }, +@@ -816,7 +816,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc4_apps_clk_src", + .parent_data = gcc_parents_3, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parents_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_floor_ops, + }, +@@ -836,7 +836,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_ref_clk_src", + .parent_data = gcc_parents_7, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_parents_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -860,7 +860,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_axi_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -883,7 +883,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_ice_core_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_phy_aux_clk_src", + .parent_data = gcc_parents_4, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_parents_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -925,7 +925,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_unipro_core_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -949,7 +949,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -964,7 +964,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -979,7 +979,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", + .parent_data = gcc_parents_4, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_parents_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -994,7 +994,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -1018,7 +1018,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -1040,7 +1040,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -1055,7 +1055,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sec_master_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -1070,7 +1070,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sec_mock_utmi_clk_src", + .parent_data = gcc_parents_0, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parents_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -1085,7 +1085,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk_src", + .parent_data = gcc_parents_2, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parents_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +@@ -1100,7 +1100,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_sec_phy_aux_clk_src", + .parent_data = gcc_parents_2, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parents_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-mmcc-msm8998-add-hardware-clockgating-regis.patch b/queue-5.10/clk-qcom-mmcc-msm8998-add-hardware-clockgating-regis.patch new file mode 100644 index 00000000000..7ce8370117f --- /dev/null +++ b/queue-5.10/clk-qcom-mmcc-msm8998-add-hardware-clockgating-regis.patch @@ -0,0 +1,79 @@ +From 77a54f78ea9731133bc30fb485d02ff82027f4bd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Jan 2021 23:10:56 +0100 +Subject: clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some + clks + +From: AngeloGioacchino Del Regno + +[ Upstream commit fa92f3b093d6ca624f42d444d5a206f8724b6bb3 ] + +Hardware clock gating is supported on some of the clocks declared in +there: ignoring that it does exist may lead to unstabilities on some +firmwares. +Add the HWCG registers where applicable to stop potential crashes. + +This was verified on a smartphone shipped with a recent MSM8998 +firmware, which will experience random crashes without this change. + +Signed-off-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20210114221059.483390-9-angelogioacchino.delregno@somainline.org +Signed-off-by: Stephen Boyd +Stable-dep-of: 9906c4140897 ("clk: qcom: mmcc-msm8998: Don't check halt bit on some branch clks") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/mmcc-msm8998.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c +index dd68983fe22ef..0f7c2a48ef2e6 100644 +--- a/drivers/clk/qcom/mmcc-msm8998.c ++++ b/drivers/clk/qcom/mmcc-msm8998.c +@@ -1211,6 +1211,8 @@ static struct clk_rcg2 vfe1_clk_src = { + + static struct clk_branch misc_ahb_clk = { + .halt_reg = 0x328, ++ .hwcg_reg = 0x328, ++ .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x328, + .enable_mask = BIT(0), +@@ -1241,6 +1243,8 @@ static struct clk_branch video_core_clk = { + + static struct clk_branch video_ahb_clk = { + .halt_reg = 0x1030, ++ .hwcg_reg = 0x1030, ++ .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = BIT(0), +@@ -1315,6 +1319,8 @@ static struct clk_branch video_subcore1_clk = { + + static struct clk_branch mdss_ahb_clk = { + .halt_reg = 0x2308, ++ .hwcg_reg = 0x2308, ++ .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2308, + .enable_mask = BIT(0), +@@ -2496,6 +2502,8 @@ static struct clk_branch mnoc_ahb_clk = { + + static struct clk_branch bimc_smmu_ahb_clk = { + .halt_reg = 0xe004, ++ .hwcg_reg = 0xe004, ++ .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xe004, + .enable_mask = BIT(0), +@@ -2511,6 +2519,8 @@ static struct clk_branch bimc_smmu_ahb_clk = { + + static struct clk_branch bimc_smmu_axi_clk = { + .halt_reg = 0xe008, ++ .hwcg_reg = 0xe008, ++ .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xe008, + .enable_mask = BIT(0), +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-mmcc-msm8998-don-t-check-halt-bit-on-some-b.patch b/queue-5.10/clk-qcom-mmcc-msm8998-don-t-check-halt-bit-on-some-b.patch new file mode 100644 index 00000000000..74b3c870fd7 --- /dev/null +++ b/queue-5.10/clk-qcom-mmcc-msm8998-don-t-check-halt-bit-on-some-b.patch @@ -0,0 +1,55 @@ +From e8700efef2b00ec0265511f17d285b3953510a35 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 9 Aug 2023 21:20:27 +0200 +Subject: clk: qcom: mmcc-msm8998: Don't check halt bit on some branch clks + +From: Konrad Dybcio + +[ Upstream commit 9906c4140897bbdbff7bb71c6ae67903cb9954ce ] + +Some branch clocks are governed externally and we're only supposed to +send a request concerning their shutdown, not actually ensure it happens. + +Use the BRANCH_HALT_SKIP define to skip checking the halt bit. + +Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") +Reviewed-by: Jeffrey Hugo +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-4-ba1b1fd9ee75@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/mmcc-msm8998.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c +index 0f7c2a48ef2e6..c0bdefcbb2946 100644 +--- a/drivers/clk/qcom/mmcc-msm8998.c ++++ b/drivers/clk/qcom/mmcc-msm8998.c +@@ -2487,6 +2487,7 @@ static struct clk_branch fd_ahb_clk = { + + static struct clk_branch mnoc_ahb_clk = { + .halt_reg = 0x5024, ++ .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x5024, + .enable_mask = BIT(0), +@@ -2502,6 +2503,7 @@ static struct clk_branch mnoc_ahb_clk = { + + static struct clk_branch bimc_smmu_ahb_clk = { + .halt_reg = 0xe004, ++ .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0xe004, + .hwcg_bit = 1, + .clkr = { +@@ -2519,6 +2521,7 @@ static struct clk_branch bimc_smmu_ahb_clk = { + + static struct clk_branch bimc_smmu_axi_clk = { + .halt_reg = 0xe008, ++ .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0xe008, + .hwcg_bit = 1, + .clkr = { +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-mmcc-msm8998-fix-the-smmu-gdsc.patch b/queue-5.10/clk-qcom-mmcc-msm8998-fix-the-smmu-gdsc.patch new file mode 100644 index 00000000000..ef6efd0dc88 --- /dev/null +++ b/queue-5.10/clk-qcom-mmcc-msm8998-fix-the-smmu-gdsc.patch @@ -0,0 +1,48 @@ +From 406332a9cb7cf67a3ec39bd2c17be2d127acd4d3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 9 Aug 2023 21:20:28 +0200 +Subject: clk: qcom: mmcc-msm8998: Fix the SMMU GDSC + +From: Konrad Dybcio + +[ Upstream commit 1fc62c8347397faf4e18249e88ecd4470c0a5357 ] + +The SMMU GDSC doesn't have to be ALWAYS-ON and shouldn't feature the +HW_CTRL flag (it's separate from hw_ctrl_addr). In addition to that, +it should feature a cxc entry for bimc_smmu_axi_clk and be marked as +votable. + +Fix all of these issues. + +Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") +Signed-off-by: Konrad Dybcio +Reviewed-by: Jeffrey Hugo +Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-5-ba1b1fd9ee75@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/mmcc-msm8998.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c +index 8768cdcf0aa3c..a68764cfb7930 100644 +--- a/drivers/clk/qcom/mmcc-msm8998.c ++++ b/drivers/clk/qcom/mmcc-msm8998.c +@@ -2662,11 +2662,13 @@ static struct gdsc camss_cpp_gdsc = { + static struct gdsc bimc_smmu_gdsc = { + .gdscr = 0xe020, + .gds_hw_ctrl = 0xe024, ++ .cxcs = (unsigned int []){ 0xe008 }, ++ .cxc_count = 1, + .pd = { + .name = "bimc_smmu", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = HW_CTRL | ALWAYS_ON, ++ .flags = VOTABLE, + }; + + static struct clk_regmap *mmcc_msm8998_clocks[] = { +-- +2.42.0 + diff --git a/queue-5.10/clk-qcom-mmcc-msm8998-set-bimc_smmu_gdsc-always-on.patch b/queue-5.10/clk-qcom-mmcc-msm8998-set-bimc_smmu_gdsc-always-on.patch new file mode 100644 index 00000000000..787c1b61993 --- /dev/null +++ b/queue-5.10/clk-qcom-mmcc-msm8998-set-bimc_smmu_gdsc-always-on.patch @@ -0,0 +1,42 @@ +From 76be519bab5c6ca6a6ad9402401996fb6a0955b5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Jan 2021 23:10:57 +0100 +Subject: clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on + +From: AngeloGioacchino Del Regno + +[ Upstream commit 68e1d106eb4dceb61bc2818d829786b364fd502b ] + +This GDSC enables (or cuts!) power to the Multimedia Subsystem IOMMU +(mmss smmu), which has bootloader pre-set secure contexts. +In the event of a complete power loss, the secure contexts will be +reset and the hypervisor will crash the SoC. + +To prevent this, and get a working multimedia subsystem, set this +GDSC as always on. + +Signed-off-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20210114221059.483390-10-angelogioacchino.delregno@somainline.org +Signed-off-by: Stephen Boyd +Stable-dep-of: 1fc62c834739 ("clk: qcom: mmcc-msm8998: Fix the SMMU GDSC") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/mmcc-msm8998.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c +index c0bdefcbb2946..8768cdcf0aa3c 100644 +--- a/drivers/clk/qcom/mmcc-msm8998.c ++++ b/drivers/clk/qcom/mmcc-msm8998.c +@@ -2666,7 +2666,7 @@ static struct gdsc bimc_smmu_gdsc = { + .name = "bimc_smmu", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = HW_CTRL, ++ .flags = HW_CTRL | ALWAYS_ON, + }; + + static struct clk_regmap *mmcc_msm8998_clocks[] = { +-- +2.42.0 + diff --git a/queue-5.10/clk-scmi-free-scmi_clk-allocated-when-the-clocks-wit.patch b/queue-5.10/clk-scmi-free-scmi_clk-allocated-when-the-clocks-wit.patch new file mode 100644 index 00000000000..fbefd68460c --- /dev/null +++ b/queue-5.10/clk-scmi-free-scmi_clk-allocated-when-the-clocks-wit.patch @@ -0,0 +1,40 @@ +From 7fd6b2933aaa6444a9373a4102c76ac2426d8f27 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 4 Oct 2023 20:36:00 +0100 +Subject: clk: scmi: Free scmi_clk allocated when the clocks with invalid info + are skipped + +From: Sudeep Holla + +[ Upstream commit 3537a75e73f3420614a358d0c8b390ea483cc87d ] + +Add the missing devm_kfree() when we skip the clocks with invalid or +missing information from the firmware. + +Cc: Cristian Marussi +Cc: Michael Turquette +Cc: Stephen Boyd +Cc: linux-clk@vger.kernel.org +Fixes: 6d6a1d82eaef ("clk: add support for clocks provided by SCMI") +Link: https://lore.kernel.org/r/20231004193600.66232-1-sudeep.holla@arm.com +Signed-off-by: Sudeep Holla +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-scmi.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c +index c754dfbb73fd4..c62636fb4aca8 100644 +--- a/drivers/clk/clk-scmi.c ++++ b/drivers/clk/clk-scmi.c +@@ -170,6 +170,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev) + sclk->info = handle->clk_ops->info_get(handle, idx); + if (!sclk->info) { + dev_dbg(dev, "invalid clock info for idx %d\n", idx); ++ devm_kfree(dev, sclk); + continue; + } + +-- +2.42.0 + diff --git a/queue-5.10/clk-ti-add-ti_dt_clk_name-helper-to-use-clock-output.patch b/queue-5.10/clk-ti-add-ti_dt_clk_name-helper-to-use-clock-output.patch new file mode 100644 index 00000000000..4e7dc96a885 --- /dev/null +++ b/queue-5.10/clk-ti-add-ti_dt_clk_name-helper-to-use-clock-output.patch @@ -0,0 +1,76 @@ +From 823fbd79e5b4bd8d2347366c64541912b95a6ed9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 4 Feb 2022 09:14:47 +0200 +Subject: clk: ti: Add ti_dt_clk_name() helper to use clock-output-names + +From: Tony Lindgren + +[ Upstream commit 2c1593328d7f02fe49de5ad6b42c36296c9d6922 ] + +Let's create the clock alias based on the clock-output-names property if +available. Also the component clock drivers can use ti_dt_clk_name() in +the following patches. + +Signed-off-by: Tony Lindgren +Link: https://lore.kernel.org/r/20220204071449.16762-7-tony@atomide.com +Signed-off-by: Stephen Boyd +Stable-dep-of: 7af5b9eadd64 ("clk: ti: fix double free in of_ti_divider_clk_setup()") +Signed-off-by: Sasha Levin +--- + drivers/clk/ti/clk.c | 20 +++++++++++++++++++- + drivers/clk/ti/clock.h | 1 + + 2 files changed, 20 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c +index 29eafab4353ef..b941ce0f3c394 100644 +--- a/drivers/clk/ti/clk.c ++++ b/drivers/clk/ti/clk.c +@@ -402,6 +402,24 @@ static const struct of_device_id simple_clk_match_table[] __initconst = { + { } + }; + ++/** ++ * ti_dt_clk_name - init clock name from first output name or node name ++ * @np: device node ++ * ++ * Use the first clock-output-name for the clock name if found. Fall back ++ * to legacy naming based on node name. ++ */ ++const char *ti_dt_clk_name(struct device_node *np) ++{ ++ const char *name; ++ ++ if (!of_property_read_string_index(np, "clock-output-names", 0, ++ &name)) ++ return name; ++ ++ return np->name; ++} ++ + /** + * ti_clk_add_aliases - setup clock aliases + * +@@ -418,7 +436,7 @@ void __init ti_clk_add_aliases(void) + clkspec.np = np; + clk = of_clk_get_from_provider(&clkspec); + +- ti_clk_add_alias(NULL, clk, np->name); ++ ti_clk_add_alias(NULL, clk, ti_dt_clk_name(np)); + } + } + +diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h +index f1dd62de2bfcb..938f34e290ed2 100644 +--- a/drivers/clk/ti/clock.h ++++ b/drivers/clk/ti/clock.h +@@ -214,6 +214,7 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, + const char *con); + struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, + const char *con); ++const char *ti_dt_clk_name(struct device_node *np); + int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); + void ti_clk_add_aliases(void); + +-- +2.42.0 + diff --git a/queue-5.10/clk-ti-change-ti_clk_register-_omap_hw-api.patch b/queue-5.10/clk-ti-change-ti_clk_register-_omap_hw-api.patch new file mode 100644 index 00000000000..c395d87e085 --- /dev/null +++ b/queue-5.10/clk-ti-change-ti_clk_register-_omap_hw-api.patch @@ -0,0 +1,383 @@ +From da78772062159100362163dbdcd3da90c975ee97 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 13 Nov 2022 19:11:46 +0100 +Subject: clk: ti: change ti_clk_register[_omap_hw]() API + +From: Dario Binacchi + +[ Upstream commit 3400d546a741a2b2001d88e7fa29110d45a3930d ] + +The ti_clk_register() and ti_clk_register_omap_hw() functions are always +called with the parameter of type "struct device" set to NULL, since the +functions from which they are called always have a parameter of type +"struct device_node". Replacing "struct device" type parameter with +"struct device_node" will allow you to register a TI clock to the common +clock framework by taking advantage of the facilities provided by the +"struct device_node" type. Further, adding the "of_" prefix to the name +of these functions explicitly binds them to the "struct device_node" +type. + +The patch has been tested on a Beaglebone board. + +Signed-off-by: Dario Binacchi +Tested-by: Tony Lindgren +Reviewed-by: Tony Lindgren +Link: https://lore.kernel.org/r/20221113181147.1626585-1-dario.binacchi@amarulasolutions.com +Signed-off-by: Stephen Boyd +Stable-dep-of: 7af5b9eadd64 ("clk: ti: fix double free in of_ti_divider_clk_setup()") +Signed-off-by: Sasha Levin +--- + drivers/clk/ti/apll.c | 4 ++-- + drivers/clk/ti/clk-dra7-atl.c | 2 +- + drivers/clk/ti/clk.c | 34 ++++++++++++++++------------------ + drivers/clk/ti/clkctrl.c | 4 ++-- + drivers/clk/ti/clock.h | 10 +++++----- + drivers/clk/ti/composite.c | 2 +- + drivers/clk/ti/divider.c | 2 +- + drivers/clk/ti/dpll.c | 4 ++-- + drivers/clk/ti/fixed-factor.c | 2 +- + drivers/clk/ti/gate.c | 6 +++--- + drivers/clk/ti/interface.c | 7 ++++--- + drivers/clk/ti/mux.c | 6 +++--- + 12 files changed, 41 insertions(+), 42 deletions(-) + +diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c +index e4db6b9a55c61..f921c6812852f 100644 +--- a/drivers/clk/ti/apll.c ++++ b/drivers/clk/ti/apll.c +@@ -168,7 +168,7 @@ static void __init omap_clk_register_apll(void *user, + ad->clk_bypass = __clk_get_hw(clk); + + name = ti_dt_clk_name(node); +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); ++ clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + kfree(init->parent_names); +@@ -408,7 +408,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) + goto cleanup; + + name = ti_dt_clk_name(node); +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); ++ clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + kfree(init); +diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c +index 5c278d6c985e9..62508e74a47a7 100644 +--- a/drivers/clk/ti/clk-dra7-atl.c ++++ b/drivers/clk/ti/clk-dra7-atl.c +@@ -205,7 +205,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) + + init.parent_names = parent_names; + +- clk = ti_clk_register(NULL, &clk_hw->hw, name); ++ clk = of_ti_clk_register(node, &clk_hw->hw, name); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); +diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c +index b941ce0f3c394..6a39fb051b2ee 100644 +--- a/drivers/clk/ti/clk.c ++++ b/drivers/clk/ti/clk.c +@@ -436,7 +436,7 @@ void __init ti_clk_add_aliases(void) + clkspec.np = np; + clk = of_clk_get_from_provider(&clkspec); + +- ti_clk_add_alias(NULL, clk, ti_dt_clk_name(np)); ++ ti_clk_add_alias(clk, ti_dt_clk_name(np)); + } + } + +@@ -489,7 +489,6 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) + + /** + * ti_clk_add_alias - add a clock alias for a TI clock +- * @dev: device alias for this clock + * @clk: clock handle to create alias for + * @con: connection ID for this clock + * +@@ -497,7 +496,7 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) + * and assigns the data to it. Returns 0 if successful, negative error + * value otherwise. + */ +-int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) ++int ti_clk_add_alias(struct clk *clk, const char *con) + { + struct clk_lookup *cl; + +@@ -511,8 +510,6 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) + if (!cl) + return -ENOMEM; + +- if (dev) +- cl->dev_id = dev_name(dev); + cl->con_id = con; + cl->clk = clk; + +@@ -522,8 +519,8 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) + } + + /** +- * ti_clk_register - register a TI clock to the common clock framework +- * @dev: device for this clock ++ * of_ti_clk_register - register a TI clock to the common clock framework ++ * @node: device node for this clock + * @hw: hardware clock handle + * @con: connection ID for this clock + * +@@ -531,17 +528,18 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) + * alias for it. Returns a handle to the registered clock if successful, + * ERR_PTR value in failure. + */ +-struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, +- const char *con) ++struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw, ++ const char *con) + { + struct clk *clk; + int ret; + +- clk = clk_register(dev, hw); +- if (IS_ERR(clk)) +- return clk; ++ ret = of_clk_hw_register(node, hw); ++ if (ret) ++ return ERR_PTR(ret); + +- ret = ti_clk_add_alias(dev, clk, con); ++ clk = hw->clk; ++ ret = ti_clk_add_alias(clk, con); + if (ret) { + clk_unregister(clk); + return ERR_PTR(ret); +@@ -551,8 +549,8 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, + } + + /** +- * ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework +- * @dev: device for this clock ++ * of_ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework ++ * @node: device node for this clock + * @hw: hardware clock handle + * @con: connection ID for this clock + * +@@ -561,13 +559,13 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, + * Returns a handle to the registered clock if successful, ERR_PTR value + * in failure. + */ +-struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, +- const char *con) ++struct clk *of_ti_clk_register_omap_hw(struct device_node *node, ++ struct clk_hw *hw, const char *con) + { + struct clk *clk; + struct clk_hw_omap *oclk; + +- clk = ti_clk_register(dev, hw, con); ++ clk = of_ti_clk_register(node, hw, con); + if (IS_ERR(clk)) + return clk; + +diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c +index 157abc46dcf44..1424b615a4cc5 100644 +--- a/drivers/clk/ti/clkctrl.c ++++ b/drivers/clk/ti/clkctrl.c +@@ -317,7 +317,7 @@ _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider, + init.ops = ops; + init.flags = 0; + +- clk = ti_clk_register(NULL, clk_hw, init.name); ++ clk = of_ti_clk_register(node, clk_hw, init.name); + if (IS_ERR_OR_NULL(clk)) { + ret = -EINVAL; + goto cleanup; +@@ -701,7 +701,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) + init.ops = &omap4_clkctrl_clk_ops; + hw->hw.init = &init; + +- clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name); ++ clk = of_ti_clk_register_omap_hw(node, &hw->hw, init.name); + if (IS_ERR_OR_NULL(clk)) + goto cleanup; + +diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h +index 938f34e290ed2..821f33ee330e4 100644 +--- a/drivers/clk/ti/clock.h ++++ b/drivers/clk/ti/clock.h +@@ -210,12 +210,12 @@ extern const struct omap_clkctrl_data dm816_clkctrl_data[]; + + typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); + +-struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, +- const char *con); +-struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, +- const char *con); ++struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw, ++ const char *con); ++struct clk *of_ti_clk_register_omap_hw(struct device_node *node, ++ struct clk_hw *hw, const char *con); + const char *ti_dt_clk_name(struct device_node *np); +-int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); ++int ti_clk_add_alias(struct clk *clk, const char *con); + void ti_clk_add_aliases(void); + + void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); +diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c +index 8d60319be3683..78d44158fb7d9 100644 +--- a/drivers/clk/ti/composite.c ++++ b/drivers/clk/ti/composite.c +@@ -184,7 +184,7 @@ static void __init _register_composite(void *user, + &ti_composite_gate_ops, 0); + + if (!IS_ERR(clk)) { +- ret = ti_clk_add_alias(NULL, clk, name); ++ ret = ti_clk_add_alias(clk, name); + if (ret) { + clk_unregister(clk); + goto cleanup; +diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c +index 9fbea0997b432..83931cc299713 100644 +--- a/drivers/clk/ti/divider.c ++++ b/drivers/clk/ti/divider.c +@@ -334,7 +334,7 @@ static struct clk *_register_divider(struct device_node *node, + div->hw.init = &init; + + /* register the clock */ +- clk = ti_clk_register(NULL, &div->hw, name); ++ clk = of_ti_clk_register(node, &div->hw, name); + + if (IS_ERR(clk)) + kfree(div); +diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c +index 6013c1d30c266..13d01594516d1 100644 +--- a/drivers/clk/ti/dpll.c ++++ b/drivers/clk/ti/dpll.c +@@ -195,7 +195,7 @@ static void __init _register_dpll(void *user, + + /* register the clock */ + name = ti_dt_clk_name(node); +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); ++ clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); +@@ -267,7 +267,7 @@ static void _register_dpll_x2(struct device_node *node, + #endif + + /* register the clock */ +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); ++ clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); + + if (IS_ERR(clk)) + kfree(clk_hw); +diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c +index 8cb00d0af9662..a4f9c1c156137 100644 +--- a/drivers/clk/ti/fixed-factor.c ++++ b/drivers/clk/ti/fixed-factor.c +@@ -62,7 +62,7 @@ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + of_ti_clk_autoidle_setup(node); +- ti_clk_add_alias(NULL, clk, clk_name); ++ ti_clk_add_alias(clk, clk_name); + } + } + CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock", +diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c +index 2fee7d681a678..0cc1babad661d 100644 +--- a/drivers/clk/ti/gate.c ++++ b/drivers/clk/ti/gate.c +@@ -93,7 +93,7 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw) + return ret; + } + +-static struct clk *_register_gate(struct device *dev, const char *name, ++static struct clk *_register_gate(struct device_node *node, const char *name, + const char *parent_name, unsigned long flags, + struct clk_omap_reg *reg, u8 bit_idx, + u8 clk_gate_flags, const struct clk_ops *ops, +@@ -123,7 +123,7 @@ static struct clk *_register_gate(struct device *dev, const char *name, + + init.flags = flags; + +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); ++ clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); + + if (IS_ERR(clk)) + kfree(clk_hw); +@@ -166,7 +166,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, + clk_gate_flags |= INVERT_ENABLE; + + name = ti_dt_clk_name(node); +- clk = _register_gate(NULL, name, parent_name, flags, ®, ++ clk = _register_gate(node, name, parent_name, flags, ®, + enable_bit, clk_gate_flags, ops, hw_ops); + + if (!IS_ERR(clk)) +diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c +index dd2b455183a91..1ccd5dbf2bb48 100644 +--- a/drivers/clk/ti/interface.c ++++ b/drivers/clk/ti/interface.c +@@ -32,7 +32,8 @@ static const struct clk_ops ti_interface_clk_ops = { + .is_enabled = &omap2_dflt_clk_is_enabled, + }; + +-static struct clk *_register_interface(struct device *dev, const char *name, ++static struct clk *_register_interface(struct device_node *node, ++ const char *name, + const char *parent_name, + struct clk_omap_reg *reg, u8 bit_idx, + const struct clk_hw_omap_ops *ops) +@@ -57,7 +58,7 @@ static struct clk *_register_interface(struct device *dev, const char *name, + init.num_parents = 1; + init.parent_names = &parent_name; + +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); ++ clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); + + if (IS_ERR(clk)) + kfree(clk_hw); +@@ -88,7 +89,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node, + } + + name = ti_dt_clk_name(node); +- clk = _register_interface(NULL, name, parent_name, ®, ++ clk = _register_interface(node, name, parent_name, ®, + enable_bit, ops); + + if (!IS_ERR(clk)) +diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c +index 15de513d2d818..4205ff4bad217 100644 +--- a/drivers/clk/ti/mux.c ++++ b/drivers/clk/ti/mux.c +@@ -126,7 +126,7 @@ const struct clk_ops ti_clk_mux_ops = { + .restore_context = clk_mux_restore_context, + }; + +-static struct clk *_register_mux(struct device *dev, const char *name, ++static struct clk *_register_mux(struct device_node *node, const char *name, + const char * const *parent_names, + u8 num_parents, unsigned long flags, + struct clk_omap_reg *reg, u8 shift, u32 mask, +@@ -156,7 +156,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, + mux->table = table; + mux->hw.init = &init; + +- clk = ti_clk_register(dev, &mux->hw, name); ++ clk = of_ti_clk_register(node, &mux->hw, name); + + if (IS_ERR(clk)) + kfree(mux); +@@ -215,7 +215,7 @@ static void of_mux_clk_setup(struct device_node *node) + mask = (1 << fls(mask)) - 1; + + name = ti_dt_clk_name(node); +- clk = _register_mux(NULL, name, parent_names, num_parents, ++ clk = _register_mux(node, name, parent_names, num_parents, + flags, ®, shift, mask, latch, clk_mux_flags, + NULL); + +-- +2.42.0 + diff --git a/queue-5.10/clk-ti-fix-double-free-in-of_ti_divider_clk_setup.patch b/queue-5.10/clk-ti-fix-double-free-in-of_ti_divider_clk_setup.patch new file mode 100644 index 00000000000..0ed276c2b6c --- /dev/null +++ b/queue-5.10/clk-ti-fix-double-free-in-of_ti_divider_clk_setup.patch @@ -0,0 +1,51 @@ +From b353ce581fc5817cc71651467c3339ce56e7826f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 2 Oct 2023 10:04:36 +0300 +Subject: clk: ti: fix double free in of_ti_divider_clk_setup() + +From: Dan Carpenter + +[ Upstream commit 7af5b9eadd64c9e02a71f97c45bcdf3b64841f6b ] + +The "div" pointer is freed in _register_divider() and again in +of_ti_divider_clk_setup(). Delete the free in _register_divider() + +Fixes: fbbc18591585 ("clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table") +Signed-off-by: Dan Carpenter +Link: https://lore.kernel.org/r/6d36eeec-6c8a-4f11-a579-aa3cd7c38749@moroto.mountain +Reviewed-by: Tony Lindgren +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/ti/divider.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c +index 83931cc299713..4cc0aaa6cb139 100644 +--- a/drivers/clk/ti/divider.c ++++ b/drivers/clk/ti/divider.c +@@ -317,7 +317,6 @@ static struct clk *_register_divider(struct device_node *node, + u32 flags, + struct clk_omap_divider *div) + { +- struct clk *clk; + struct clk_init_data init; + const char *parent_name; + const char *name; +@@ -334,12 +333,7 @@ static struct clk *_register_divider(struct device_node *node, + div->hw.init = &init; + + /* register the clock */ +- clk = of_ti_clk_register(node, &div->hw, name); +- +- if (IS_ERR(clk)) +- kfree(div); +- +- return clk; ++ return of_ti_clk_register(node, &div->hw, name); + } + + int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, +-- +2.42.0 + diff --git a/queue-5.10/clk-ti-update-component-clocks-to-use-ti_dt_clk_name.patch b/queue-5.10/clk-ti-update-component-clocks-to-use-ti_dt_clk_name.patch new file mode 100644 index 00000000000..7a389af5d10 --- /dev/null +++ b/queue-5.10/clk-ti-update-component-clocks-to-use-ti_dt_clk_name.patch @@ -0,0 +1,212 @@ +From 4065ad934342b3ad11bab5dbed621629a48485f2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 4 Feb 2022 09:14:49 +0200 +Subject: clk: ti: Update component clocks to use ti_dt_clk_name() + +From: Tony Lindgren + +[ Upstream commit ed06099c5d0b329082cc19c58eace0b20bf7fe70 ] + +Let's update all the TI component clocks to use ti_dt_clk_name() instead +of devicetree node name if available. + +Signed-off-by: Tony Lindgren +Link: https://lore.kernel.org/r/20220204071449.16762-9-tony@atomide.com +Signed-off-by: Stephen Boyd +Stable-dep-of: 7af5b9eadd64 ("clk: ti: fix double free in of_ti_divider_clk_setup()") +Signed-off-by: Sasha Levin +--- + drivers/clk/ti/autoidle.c | 2 +- + drivers/clk/ti/clk-dra7-atl.c | 6 ++++-- + drivers/clk/ti/composite.c | 6 ++++-- + drivers/clk/ti/divider.c | 6 ++++-- + drivers/clk/ti/fixed-factor.c | 2 +- + drivers/clk/ti/gate.c | 4 +++- + drivers/clk/ti/interface.c | 4 +++- + drivers/clk/ti/mux.c | 4 +++- + 8 files changed, 23 insertions(+), 11 deletions(-) + +diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c +index f6f8a409f148f..d6e5f1511ace8 100644 +--- a/drivers/clk/ti/autoidle.c ++++ b/drivers/clk/ti/autoidle.c +@@ -205,7 +205,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node) + return -ENOMEM; + + clk->shift = shift; +- clk->name = node->name; ++ clk->name = ti_dt_clk_name(node); + ret = ti_clk_get_reg_addr(node, 0, &clk->reg); + if (ret) { + kfree(clk); +diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c +index e2e59d78c173f..5c278d6c985e9 100644 +--- a/drivers/clk/ti/clk-dra7-atl.c ++++ b/drivers/clk/ti/clk-dra7-atl.c +@@ -173,6 +173,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) + struct dra7_atl_desc *clk_hw = NULL; + struct clk_init_data init = { NULL }; + const char **parent_names = NULL; ++ const char *name; + struct clk *clk; + + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); +@@ -183,7 +184,8 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) + + clk_hw->hw.init = &init; + clk_hw->divider = 1; +- init.name = node->name; ++ name = ti_dt_clk_name(node); ++ init.name = name; + init.ops = &atl_clk_ops; + init.flags = CLK_IGNORE_UNUSED; + init.num_parents = of_clk_get_parent_count(node); +@@ -203,7 +205,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) + + init.parent_names = parent_names; + +- clk = ti_clk_register(NULL, &clk_hw->hw, node->name); ++ clk = ti_clk_register(NULL, &clk_hw->hw, name); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); +diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c +index eaa43575cfa5e..8d60319be3683 100644 +--- a/drivers/clk/ti/composite.c ++++ b/drivers/clk/ti/composite.c +@@ -125,6 +125,7 @@ static void __init _register_composite(void *user, + struct component_clk *comp; + int num_parents = 0; + const char **parent_names = NULL; ++ const char *name; + int i; + int ret; + +@@ -172,7 +173,8 @@ static void __init _register_composite(void *user, + goto cleanup; + } + +- clk = clk_register_composite(NULL, node->name, ++ name = ti_dt_clk_name(node); ++ clk = clk_register_composite(NULL, name, + parent_names, num_parents, + _get_hw(cclk, CLK_COMPONENT_TYPE_MUX), + &ti_clk_mux_ops, +@@ -182,7 +184,7 @@ static void __init _register_composite(void *user, + &ti_composite_gate_ops, 0); + + if (!IS_ERR(clk)) { +- ret = ti_clk_add_alias(NULL, clk, node->name); ++ ret = ti_clk_add_alias(NULL, clk, name); + if (ret) { + clk_unregister(clk); + goto cleanup; +diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c +index 28080df92f722..9fbea0997b432 100644 +--- a/drivers/clk/ti/divider.c ++++ b/drivers/clk/ti/divider.c +@@ -320,10 +320,12 @@ static struct clk *_register_divider(struct device_node *node, + struct clk *clk; + struct clk_init_data init; + const char *parent_name; ++ const char *name; + + parent_name = of_clk_get_parent_name(node, 0); + +- init.name = node->name; ++ name = ti_dt_clk_name(node); ++ init.name = name; + init.ops = &ti_clk_divider_ops; + init.flags = flags; + init.parent_names = (parent_name ? &parent_name : NULL); +@@ -332,7 +334,7 @@ static struct clk *_register_divider(struct device_node *node, + div->hw.init = &init; + + /* register the clock */ +- clk = ti_clk_register(NULL, &div->hw, node->name); ++ clk = ti_clk_register(NULL, &div->hw, name); + + if (IS_ERR(clk)) + kfree(div); +diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c +index 7cbe896db0716..8cb00d0af9662 100644 +--- a/drivers/clk/ti/fixed-factor.c ++++ b/drivers/clk/ti/fixed-factor.c +@@ -36,7 +36,7 @@ + static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) + { + struct clk *clk; +- const char *clk_name = node->name; ++ const char *clk_name = ti_dt_clk_name(node); + const char *parent_name; + u32 div, mult; + u32 flags = 0; +diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c +index 42389558418c5..2fee7d681a678 100644 +--- a/drivers/clk/ti/gate.c ++++ b/drivers/clk/ti/gate.c +@@ -138,6 +138,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, + struct clk *clk; + const char *parent_name; + struct clk_omap_reg reg; ++ const char *name; + u8 enable_bit = 0; + u32 val; + u32 flags = 0; +@@ -164,7 +165,8 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, + if (of_property_read_bool(node, "ti,set-bit-to-disable")) + clk_gate_flags |= INVERT_ENABLE; + +- clk = _register_gate(NULL, node->name, parent_name, flags, ®, ++ name = ti_dt_clk_name(node); ++ clk = _register_gate(NULL, name, parent_name, flags, ®, + enable_bit, clk_gate_flags, ops, hw_ops); + + if (!IS_ERR(clk)) +diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c +index 83e34429d3b10..dd2b455183a91 100644 +--- a/drivers/clk/ti/interface.c ++++ b/drivers/clk/ti/interface.c +@@ -72,6 +72,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node, + const char *parent_name; + struct clk_omap_reg reg; + u8 enable_bit = 0; ++ const char *name; + u32 val; + + if (ti_clk_get_reg_addr(node, 0, ®)) +@@ -86,7 +87,8 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node, + return; + } + +- clk = _register_interface(NULL, node->name, parent_name, ®, ++ name = ti_dt_clk_name(node); ++ clk = _register_interface(NULL, name, parent_name, ®, + enable_bit, ops); + + if (!IS_ERR(clk)) +diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c +index 0069e7cf3ebcc..15de513d2d818 100644 +--- a/drivers/clk/ti/mux.c ++++ b/drivers/clk/ti/mux.c +@@ -176,6 +176,7 @@ static void of_mux_clk_setup(struct device_node *node) + struct clk_omap_reg reg; + unsigned int num_parents; + const char **parent_names; ++ const char *name; + u8 clk_mux_flags = 0; + u32 mask = 0; + u32 shift = 0; +@@ -213,7 +214,8 @@ static void of_mux_clk_setup(struct device_node *node) + + mask = (1 << fls(mask)) - 1; + +- clk = _register_mux(NULL, node->name, parent_names, num_parents, ++ name = ti_dt_clk_name(node); ++ clk = _register_mux(NULL, name, parent_names, num_parents, + flags, ®, shift, mask, latch, clk_mux_flags, + NULL); + +-- +2.42.0 + diff --git a/queue-5.10/clk-ti-update-pll-and-clockdomain-clocks-to-use-ti_d.patch b/queue-5.10/clk-ti-update-pll-and-clockdomain-clocks-to-use-ti_d.patch new file mode 100644 index 00000000000..144c89fdedf --- /dev/null +++ b/queue-5.10/clk-ti-update-pll-and-clockdomain-clocks-to-use-ti_d.patch @@ -0,0 +1,189 @@ +From 6367224b8673917c59aab4e17ed1f13a25197fad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 4 Feb 2022 09:14:48 +0200 +Subject: clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name() + +From: Tony Lindgren + +[ Upstream commit 9e56a7d4263ca1c51d867e811cf2dd7e61b6469e ] + +Let's update the TI pll and clockdomain clocks to use ti_dt_clk_name() +instead of devicetree node name if available. + +Signed-off-by: Tony Lindgren +Link: https://lore.kernel.org/r/20220204071449.16762-8-tony@atomide.com +Signed-off-by: Stephen Boyd +Stable-dep-of: 7af5b9eadd64 ("clk: ti: fix double free in of_ti_divider_clk_setup()") +Signed-off-by: Sasha Levin +--- + drivers/clk/ti/apll.c | 13 +++++++++---- + drivers/clk/ti/clockdomain.c | 2 +- + drivers/clk/ti/dpll.c | 8 +++++--- + drivers/clk/ti/fapll.c | 11 +++++++---- + 4 files changed, 22 insertions(+), 12 deletions(-) + +diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c +index ac5bc8857a514..e4db6b9a55c61 100644 +--- a/drivers/clk/ti/apll.c ++++ b/drivers/clk/ti/apll.c +@@ -139,6 +139,7 @@ static void __init omap_clk_register_apll(void *user, + struct clk_hw *hw = user; + struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); + struct dpll_data *ad = clk_hw->dpll_data; ++ const char *name; + struct clk *clk; + const struct clk_init_data *init = clk_hw->hw.init; + +@@ -166,7 +167,8 @@ static void __init omap_clk_register_apll(void *user, + + ad->clk_bypass = __clk_get_hw(clk); + +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); ++ name = ti_dt_clk_name(node); ++ clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + kfree(init->parent_names); +@@ -198,7 +200,7 @@ static void __init of_dra7_apll_setup(struct device_node *node) + clk_hw->dpll_data = ad; + clk_hw->hw.init = init; + +- init->name = node->name; ++ init->name = ti_dt_clk_name(node); + init->ops = &apll_ck_ops; + + init->num_parents = of_clk_get_parent_count(node); +@@ -347,6 +349,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) + struct dpll_data *ad = NULL; + struct clk_hw_omap *clk_hw = NULL; + struct clk_init_data *init = NULL; ++ const char *name; + struct clk *clk; + const char *parent_name; + u32 val; +@@ -362,7 +365,8 @@ static void __init of_omap2_apll_setup(struct device_node *node) + clk_hw->dpll_data = ad; + clk_hw->hw.init = init; + init->ops = &omap2_apll_ops; +- init->name = node->name; ++ name = ti_dt_clk_name(node); ++ init->name = name; + clk_hw->ops = &omap2_apll_hwops; + + init->num_parents = of_clk_get_parent_count(node); +@@ -403,7 +407,8 @@ static void __init of_omap2_apll_setup(struct device_node *node) + if (ret) + goto cleanup; + +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); ++ name = ti_dt_clk_name(node); ++ clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + kfree(init); +diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c +index 700b7f44f6716..e5f447f4377b7 100644 +--- a/drivers/clk/ti/clockdomain.c ++++ b/drivers/clk/ti/clockdomain.c +@@ -131,7 +131,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) + { + struct clk *clk; + struct clk_hw *clk_hw; +- const char *clkdm_name = node->name; ++ const char *clkdm_name = ti_dt_clk_name(node); + int i; + unsigned int num_clks; + +diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c +index 247510e306e2a..6013c1d30c266 100644 +--- a/drivers/clk/ti/dpll.c ++++ b/drivers/clk/ti/dpll.c +@@ -164,6 +164,7 @@ static void __init _register_dpll(void *user, + struct clk_hw *hw = user; + struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); + struct dpll_data *dd = clk_hw->dpll_data; ++ const char *name; + struct clk *clk; + const struct clk_init_data *init = hw->init; + +@@ -193,7 +194,8 @@ static void __init _register_dpll(void *user, + dd->clk_bypass = __clk_get_hw(clk); + + /* register the clock */ +- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); ++ name = ti_dt_clk_name(node); ++ clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); +@@ -227,7 +229,7 @@ static void _register_dpll_x2(struct device_node *node, + struct clk *clk; + struct clk_init_data init = { NULL }; + struct clk_hw_omap *clk_hw; +- const char *name = node->name; ++ const char *name = ti_dt_clk_name(node); + const char *parent_name; + + parent_name = of_clk_get_parent_name(node, 0); +@@ -302,7 +304,7 @@ static void __init of_ti_dpll_setup(struct device_node *node, + clk_hw->ops = &clkhwops_omap3_dpll; + clk_hw->hw.init = init; + +- init->name = node->name; ++ init->name = ti_dt_clk_name(node); + init->ops = ops; + + init->num_parents = of_clk_get_parent_count(node); +diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c +index 8024c6d2b9e95..749c6b73abff3 100644 +--- a/drivers/clk/ti/fapll.c ++++ b/drivers/clk/ti/fapll.c +@@ -19,6 +19,8 @@ + #include + #include + ++#include "clock.h" ++ + /* FAPLL Control Register PLL_CTRL */ + #define FAPLL_MAIN_MULT_N_SHIFT 16 + #define FAPLL_MAIN_DIV_P_SHIFT 8 +@@ -542,6 +544,7 @@ static void __init ti_fapll_setup(struct device_node *node) + struct clk_init_data *init = NULL; + const char *parent_name[2]; + struct clk *pll_clk; ++ const char *name; + int i; + + fd = kzalloc(sizeof(*fd), GFP_KERNEL); +@@ -559,7 +562,8 @@ static void __init ti_fapll_setup(struct device_node *node) + goto free; + + init->ops = &ti_fapll_ops; +- init->name = node->name; ++ name = ti_dt_clk_name(node); ++ init->name = name; + + init->num_parents = of_clk_get_parent_count(node); + if (init->num_parents != 2) { +@@ -591,7 +595,7 @@ static void __init ti_fapll_setup(struct device_node *node) + if (fapll_is_ddr_pll(fd->base)) + fd->bypass_bit_inverted = true; + +- fd->name = node->name; ++ fd->name = name; + fd->hw.init = init; + + /* Register the parent PLL */ +@@ -638,8 +642,7 @@ static void __init ti_fapll_setup(struct device_node *node) + freq = NULL; + } + synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, +- output_name, node->name, +- pll_clk); ++ output_name, name, pll_clk); + if (IS_ERR(synth_clk)) + continue; + +-- +2.42.0 + diff --git a/queue-5.10/crypto-caam-jr-fix-chacha20-poly1305-self-test-failu.patch b/queue-5.10/crypto-caam-jr-fix-chacha20-poly1305-self-test-failu.patch new file mode 100644 index 00000000000..50a5e9e41ef --- /dev/null +++ b/queue-5.10/crypto-caam-jr-fix-chacha20-poly1305-self-test-failu.patch @@ -0,0 +1,39 @@ +From da8bc168f5017f1eebf59726ab40591f6dcd902d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Sep 2023 18:12:37 +0530 +Subject: crypto: caam/jr - fix Chacha20 + Poly1305 self test failure + +From: Gaurav Jain + +[ Upstream commit a8d3cdcc092fb2f2882acb6c20473a1be0ef4484 ] + +key buffer is not copied in chachapoly_setkey function, +results in wrong output for encryption/decryption operation. + +fix this by memcpy the key in caam_ctx key arrary + +Fixes: d6bbd4eea243 ("crypto: caam/jr - add support for Chacha20 + Poly1305") +Signed-off-by: Gaurav Jain +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/caam/caamalg.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c +index 8697ae53b0633..6b513555df348 100644 +--- a/drivers/crypto/caam/caamalg.c ++++ b/drivers/crypto/caam/caamalg.c +@@ -566,7 +566,8 @@ static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key, + if (keylen != CHACHA_KEY_SIZE + saltlen) + return -EINVAL; + +- ctx->cdata.key_virt = key; ++ memcpy(ctx->key, key, keylen); ++ ctx->cdata.key_virt = ctx->key; + ctx->cdata.keylen = keylen - saltlen; + + return chachapoly_set_sh_desc(aead); +-- +2.42.0 + diff --git a/queue-5.10/crypto-caam-qi2-fix-chacha20-poly1305-self-test-fail.patch b/queue-5.10/crypto-caam-qi2-fix-chacha20-poly1305-self-test-fail.patch new file mode 100644 index 00000000000..a88e86c3d35 --- /dev/null +++ b/queue-5.10/crypto-caam-qi2-fix-chacha20-poly1305-self-test-fail.patch @@ -0,0 +1,39 @@ +From abe333a47b2c4ffdca0d48b6373ca68247818647 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Sep 2023 15:14:44 +0530 +Subject: crypto: caam/qi2 - fix Chacha20 + Poly1305 self test failure + +From: Gaurav Jain + +[ Upstream commit 7b8c6aee0d5b864e70c0da82583f9862e374eaf3 ] + +key buffer is not copied in chachapoly_setkey function, +results in wrong output for encryption/decryption operation. + +fix this by memcpy the key in caam_ctx key arrary + +Fixes: c10a53367901 ("crypto: caam/qi2 - add support for Chacha20 + Poly1305") +Signed-off-by: Gaurav Jain +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/caam/caamalg_qi2.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c +index 5a40c7d10cc9a..43bed47ce59be 100644 +--- a/drivers/crypto/caam/caamalg_qi2.c ++++ b/drivers/crypto/caam/caamalg_qi2.c +@@ -636,7 +636,8 @@ static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key, + if (keylen != CHACHA_KEY_SIZE + saltlen) + return -EINVAL; + +- ctx->cdata.key_virt = key; ++ memcpy(ctx->key, key, keylen); ++ ctx->cdata.key_virt = ctx->key; + ctx->cdata.keylen = keylen - saltlen; + + return chachapoly_set_sh_desc(aead); +-- +2.42.0 + diff --git a/queue-5.10/crypto-hisilicon-hpre-fix-a-erroneous-check-after-sn.patch b/queue-5.10/crypto-hisilicon-hpre-fix-a-erroneous-check-after-sn.patch new file mode 100644 index 00000000000..fb6b6f5736d --- /dev/null +++ b/queue-5.10/crypto-hisilicon-hpre-fix-a-erroneous-check-after-sn.patch @@ -0,0 +1,36 @@ +From 1c90b66e89f092cfdb95213837e63623709b4136 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Sep 2023 22:17:29 +0200 +Subject: crypto: hisilicon/hpre - Fix a erroneous check after snprintf() + +From: Christophe JAILLET + +[ Upstream commit c977950146720abff14e46d8c53f5638b06a9182 ] + +This error handling looks really strange. +Check if the string has been truncated instead. + +Fixes: 02ab994635eb ("crypto: hisilicon - Fixed some tiny bugs of HPRE") +Signed-off-by: Christophe JAILLET +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/hpre/hpre_main.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c +index a33394d91bbf8..8da9d6dc6e87a 100644 +--- a/drivers/crypto/hisilicon/hpre/hpre_main.c ++++ b/drivers/crypto/hisilicon/hpre/hpre_main.c +@@ -637,7 +637,7 @@ static int hpre_cluster_debugfs_init(struct hisi_qm *qm) + + for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { + ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); +- if (ret < 0) ++ if (ret >= HPRE_DBGFS_VAL_MAX_LEN) + return -EINVAL; + tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); + +-- +2.42.0 + diff --git a/queue-5.10/crypto-qat-increase-size-of-buffers.patch b/queue-5.10/crypto-qat-increase-size-of-buffers.patch new file mode 100644 index 00000000000..fdd2de40a42 --- /dev/null +++ b/queue-5.10/crypto-qat-increase-size-of-buffers.patch @@ -0,0 +1,72 @@ +From e5467db0d32c97bc56c94581c1a3405118862116 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Sep 2023 10:03:47 +0100 +Subject: crypto: qat - increase size of buffers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Giovanni Cabiddu + +[ Upstream commit 4e4e2ed22d505c5bacf65c6a39bfb6d120d24785 ] + +Increase the size of the buffers used for composing the names used for +the transport debugfs entries and the vector name to avoid a potential +truncation. + +This resolves the following errors when compiling the driver with W=1 +and KCFLAGS=-Werror on GCC 12.3.1: + + drivers/crypto/intel/qat/qat_common/adf_transport_debug.c: In function ‘adf_ring_debugfs_add’: + drivers/crypto/intel/qat/qat_common/adf_transport_debug.c:100:60: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] + drivers/crypto/intel/qat/qat_common/adf_isr.c: In function ‘adf_isr_resource_alloc’: + drivers/crypto/intel/qat/qat_common/adf_isr.c:197:47: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size between 0 and 5 [-Werror=format-truncation=] + +Fixes: a672a9dc872e ("crypto: qat - Intel(R) QAT transport code") +Signed-off-by: Giovanni Cabiddu +Reviewed-by: Damian Muszynski +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/qat/qat_common/adf_accel_devices.h | 2 +- + drivers/crypto/qat/qat_common/adf_transport_debug.c | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h +index 411a505e1f59f..961a8b3650c73 100644 +--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h ++++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h +@@ -23,7 +23,7 @@ + #define ADF_PCI_MAX_BARS 3 + #define ADF_DEVICE_NAME_LENGTH 32 + #define ADF_ETR_MAX_RINGS_PER_BANK 16 +-#define ADF_MAX_MSIX_VECTOR_NAME 16 ++#define ADF_MAX_MSIX_VECTOR_NAME 48 + #define ADF_DEVICE_NAME_PREFIX "qat_" + + enum adf_accel_capabilities { +diff --git a/drivers/crypto/qat/qat_common/adf_transport_debug.c b/drivers/crypto/qat/qat_common/adf_transport_debug.c +index dac25ba47260b..e6bdbd3c9b1f2 100644 +--- a/drivers/crypto/qat/qat_common/adf_transport_debug.c ++++ b/drivers/crypto/qat/qat_common/adf_transport_debug.c +@@ -89,7 +89,7 @@ DEFINE_SEQ_ATTRIBUTE(adf_ring_debug); + int adf_ring_debugfs_add(struct adf_etr_ring_data *ring, const char *name) + { + struct adf_etr_ring_debug_entry *ring_debug; +- char entry_name[8]; ++ char entry_name[16]; + + ring_debug = kzalloc(sizeof(*ring_debug), GFP_KERNEL); + if (!ring_debug) +@@ -184,7 +184,7 @@ int adf_bank_debugfs_add(struct adf_etr_bank_data *bank) + { + struct adf_accel_dev *accel_dev = bank->accel_dev; + struct dentry *parent = accel_dev->transport->debug; +- char name[8]; ++ char name[16]; + + snprintf(name, sizeof(name), "bank_%02d", bank->bank_number); + bank->bank_debug_dir = debugfs_create_dir(name, parent); +-- +2.42.0 + diff --git a/queue-5.10/crypto-qat-mask-device-capabilities-with-soft-straps.patch b/queue-5.10/crypto-qat-mask-device-capabilities-with-soft-straps.patch new file mode 100644 index 00000000000..ce2e1dfc41a --- /dev/null +++ b/queue-5.10/crypto-qat-mask-device-capabilities-with-soft-straps.patch @@ -0,0 +1,555 @@ +From 7e26f3a7ff737a6250fc4f82bb8be3e9998fbe11 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Oct 2020 21:38:18 +0100 +Subject: crypto: qat - mask device capabilities with soft straps + +From: Giovanni Cabiddu + +[ Upstream commit 7b07ed5042c5d21467af5aa055f2b49b2e661a83 ] + +Enable acceleration engines (AEs) and accelerators based on soft straps +and fuses. When looping with a number of AEs or accelerators, ignore the +ones that are disabled. + +This patch is based on earlier work done by Conor McLoughlin. + +Signed-off-by: Giovanni Cabiddu +Reviewed-by: Fiona Trahe +Reviewed-by: Wojciech Ziemba +Reviewed-by: Andy Shevchenko +Signed-off-by: Herbert Xu +Stable-dep-of: 4e4e2ed22d50 ("crypto: qat - increase size of buffers") +Signed-off-by: Sasha Levin +--- + .../crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c | 34 +++++++++++++++---- + .../crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h | 1 + + drivers/crypto/qat/qat_c3xxx/adf_drv.c | 6 ++-- + .../qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c | 4 +-- + drivers/crypto/qat/qat_c3xxxvf/adf_drv.c | 4 +-- + .../crypto/qat/qat_c62x/adf_c62x_hw_data.c | 34 +++++++++++++++---- + .../crypto/qat/qat_c62x/adf_c62x_hw_data.h | 1 + + drivers/crypto/qat/qat_c62x/adf_drv.c | 6 ++-- + .../qat/qat_c62xvf/adf_c62xvf_hw_data.c | 4 +-- + drivers/crypto/qat/qat_c62xvf/adf_drv.c | 4 +-- + .../crypto/qat/qat_common/adf_accel_devices.h | 5 +-- + drivers/crypto/qat/qat_common/qat_hal.c | 27 ++++++++------- + .../qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 20 +++++++---- + drivers/crypto/qat/qat_dh895xcc/adf_drv.c | 4 +-- + .../qat_dh895xccvf/adf_dh895xccvf_hw_data.c | 4 +-- + drivers/crypto/qat/qat_dh895xccvf/adf_drv.c | 4 +-- + 16 files changed, 109 insertions(+), 53 deletions(-) + +diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c +index aee494d3da529..4b2f5aa833919 100644 +--- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c ++++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c +@@ -17,15 +17,33 @@ static struct adf_hw_device_class c3xxx_class = { + .instances = 0 + }; + +-static u32 get_accel_mask(u32 fuse) ++static u32 get_accel_mask(struct adf_hw_device_data *self) + { +- return (~fuse) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET & +- ADF_C3XXX_ACCELERATORS_MASK; ++ u32 straps = self->straps; ++ u32 fuses = self->fuses; ++ u32 accel; ++ ++ accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET; ++ accel &= ADF_C3XXX_ACCELERATORS_MASK; ++ ++ return accel; + } + +-static u32 get_ae_mask(u32 fuse) ++static u32 get_ae_mask(struct adf_hw_device_data *self) + { +- return (~fuse) & ADF_C3XXX_ACCELENGINES_MASK; ++ u32 straps = self->straps; ++ u32 fuses = self->fuses; ++ unsigned long disabled; ++ u32 ae_disable; ++ int accel; ++ ++ /* If an accel is disabled, then disable the corresponding two AEs */ ++ disabled = ~get_accel_mask(self) & ADF_C3XXX_ACCELERATORS_MASK; ++ ae_disable = BIT(1) | BIT(0); ++ for_each_set_bit(accel, &disabled, ADF_C3XXX_MAX_ACCELERATORS) ++ straps |= ae_disable << (accel << 1); ++ ++ return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK; + } + + static u32 get_num_accels(struct adf_hw_device_data *self) +@@ -109,11 +127,13 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev) + { + struct adf_hw_device_data *hw_device = accel_dev->hw_device; + struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C3XXX_PMISC_BAR]; ++ unsigned long accel_mask = hw_device->accel_mask; ++ unsigned long ae_mask = hw_device->ae_mask; + void __iomem *csr = misc_bar->virt_addr; + unsigned int val, i; + + /* Enable Accel Engine error detection & correction */ +- for (i = 0; i < hw_device->get_num_aes(hw_device); i++) { ++ for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { + val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); + val |= ADF_C3XXX_ENABLE_AE_ECC_ERR; + ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); +@@ -123,7 +143,7 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev) + } + + /* Enable shared memory error detection & correction */ +- for (i = 0; i < hw_device->get_num_accels(hw_device); i++) { ++ for_each_set_bit(i, &accel_mask, ADF_C3XXX_MAX_ACCELERATORS) { + val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); + val |= ADF_C3XXX_ERRSSMSH_EN; + ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); +diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h +index 8b5dd2c94ebfa..94097816f68ae 100644 +--- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h ++++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h +@@ -18,6 +18,7 @@ + #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) + #define ADF_C3XXX_SMIA0_MASK 0xFFFF + #define ADF_C3XXX_SMIA1_MASK 0x1 ++#define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC + /* Error detection and correction */ + #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) + #define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) +diff --git a/drivers/crypto/qat/qat_c3xxx/adf_drv.c b/drivers/crypto/qat/qat_c3xxx/adf_drv.c +index ed0e8e33fe4b3..da6e880269881 100644 +--- a/drivers/crypto/qat/qat_c3xxx/adf_drv.c ++++ b/drivers/crypto/qat/qat_c3xxx/adf_drv.c +@@ -126,10 +126,12 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid); + pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET, + &hw_data->fuses); ++ pci_read_config_dword(pdev, ADF_C3XXX_SOFTSTRAP_CSR_OFFSET, ++ &hw_data->straps); + + /* Get Accelerators and Accelerators Engines masks */ +- hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); +- hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); ++ hw_data->accel_mask = hw_data->get_accel_mask(hw_data); ++ hw_data->ae_mask = hw_data->get_ae_mask(hw_data); + accel_pci_dev->sku = hw_data->get_sku(hw_data); + /* If the device has no acceleration engines then ignore it. */ + if (!hw_data->accel_mask || !hw_data->ae_mask || +diff --git a/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c b/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c +index 9709f29b64540..26b13973f9ac9 100644 +--- a/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c ++++ b/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c +@@ -11,12 +11,12 @@ static struct adf_hw_device_class c3xxxiov_class = { + .instances = 0 + }; + +-static u32 get_accel_mask(u32 fuse) ++static u32 get_accel_mask(struct adf_hw_device_data *self) + { + return ADF_C3XXXIOV_ACCELERATORS_MASK; + } + +-static u32 get_ae_mask(u32 fuse) ++static u32 get_ae_mask(struct adf_hw_device_data *self) + { + return ADF_C3XXXIOV_ACCELENGINES_MASK; + } +diff --git a/drivers/crypto/qat/qat_c3xxxvf/adf_drv.c b/drivers/crypto/qat/qat_c3xxxvf/adf_drv.c +index ea932b6c4534f..067ca5e17d387 100644 +--- a/drivers/crypto/qat/qat_c3xxxvf/adf_drv.c ++++ b/drivers/crypto/qat/qat_c3xxxvf/adf_drv.c +@@ -119,8 +119,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + adf_init_hw_data_c3xxxiov(accel_dev->hw_device); + + /* Get Accelerators and Accelerators Engines masks */ +- hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); +- hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); ++ hw_data->accel_mask = hw_data->get_accel_mask(hw_data); ++ hw_data->ae_mask = hw_data->get_ae_mask(hw_data); + accel_pci_dev->sku = hw_data->get_sku(hw_data); + + /* Create dev top level debugfs entry */ +diff --git a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c +index 844ad5ed33fcd..c0b5751e96821 100644 +--- a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c ++++ b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c +@@ -22,15 +22,33 @@ static struct adf_hw_device_class c62x_class = { + .instances = 0 + }; + +-static u32 get_accel_mask(u32 fuse) ++static u32 get_accel_mask(struct adf_hw_device_data *self) + { +- return (~fuse) >> ADF_C62X_ACCELERATORS_REG_OFFSET & +- ADF_C62X_ACCELERATORS_MASK; ++ u32 straps = self->straps; ++ u32 fuses = self->fuses; ++ u32 accel; ++ ++ accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET; ++ accel &= ADF_C62X_ACCELERATORS_MASK; ++ ++ return accel; + } + +-static u32 get_ae_mask(u32 fuse) ++static u32 get_ae_mask(struct adf_hw_device_data *self) + { +- return (~fuse) & ADF_C62X_ACCELENGINES_MASK; ++ u32 straps = self->straps; ++ u32 fuses = self->fuses; ++ unsigned long disabled; ++ u32 ae_disable; ++ int accel; ++ ++ /* If an accel is disabled, then disable the corresponding two AEs */ ++ disabled = ~get_accel_mask(self) & ADF_C62X_ACCELERATORS_MASK; ++ ae_disable = BIT(1) | BIT(0); ++ for_each_set_bit(accel, &disabled, ADF_C62X_MAX_ACCELERATORS) ++ straps |= ae_disable << (accel << 1); ++ ++ return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK; + } + + static u32 get_num_accels(struct adf_hw_device_data *self) +@@ -119,11 +137,13 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev) + { + struct adf_hw_device_data *hw_device = accel_dev->hw_device; + struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C62X_PMISC_BAR]; ++ unsigned long accel_mask = hw_device->accel_mask; ++ unsigned long ae_mask = hw_device->ae_mask; + void __iomem *csr = misc_bar->virt_addr; + unsigned int val, i; + + /* Enable Accel Engine error detection & correction */ +- for (i = 0; i < hw_device->get_num_aes(hw_device); i++) { ++ for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { + val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); + val |= ADF_C62X_ENABLE_AE_ECC_ERR; + ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); +@@ -133,7 +153,7 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev) + } + + /* Enable shared memory error detection & correction */ +- for (i = 0; i < hw_device->get_num_accels(hw_device); i++) { ++ for_each_set_bit(i, &accel_mask, ADF_C62X_MAX_ACCELERATORS) { + val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); + val |= ADF_C62X_ERRSSMSH_EN; + ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); +diff --git a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h +index 88504d2bf30d5..a2e2961a21022 100644 +--- a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h ++++ b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h +@@ -19,6 +19,7 @@ + #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) + #define ADF_C62X_SMIA0_MASK 0xFFFF + #define ADF_C62X_SMIA1_MASK 0x1 ++#define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC + /* Error detection and correction */ + #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) + #define ADF_C62X_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) +diff --git a/drivers/crypto/qat/qat_c62x/adf_drv.c b/drivers/crypto/qat/qat_c62x/adf_drv.c +index d8e7c9c255903..3da697a566ad7 100644 +--- a/drivers/crypto/qat/qat_c62x/adf_drv.c ++++ b/drivers/crypto/qat/qat_c62x/adf_drv.c +@@ -126,10 +126,12 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid); + pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET, + &hw_data->fuses); ++ pci_read_config_dword(pdev, ADF_C62X_SOFTSTRAP_CSR_OFFSET, ++ &hw_data->straps); + + /* Get Accelerators and Accelerators Engines masks */ +- hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); +- hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); ++ hw_data->accel_mask = hw_data->get_accel_mask(hw_data); ++ hw_data->ae_mask = hw_data->get_ae_mask(hw_data); + accel_pci_dev->sku = hw_data->get_sku(hw_data); + /* If the device has no acceleration engines then ignore it. */ + if (!hw_data->accel_mask || !hw_data->ae_mask || +diff --git a/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c b/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c +index 5e6909d6cfc65..ff5a57824eca4 100644 +--- a/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c ++++ b/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c +@@ -11,12 +11,12 @@ static struct adf_hw_device_class c62xiov_class = { + .instances = 0 + }; + +-static u32 get_accel_mask(u32 fuse) ++static u32 get_accel_mask(struct adf_hw_device_data *self) + { + return ADF_C62XIOV_ACCELERATORS_MASK; + } + +-static u32 get_ae_mask(u32 fuse) ++static u32 get_ae_mask(struct adf_hw_device_data *self) + { + return ADF_C62XIOV_ACCELENGINES_MASK; + } +diff --git a/drivers/crypto/qat/qat_c62xvf/adf_drv.c b/drivers/crypto/qat/qat_c62xvf/adf_drv.c +index 6200ad448b119..51ea88c0b17d7 100644 +--- a/drivers/crypto/qat/qat_c62xvf/adf_drv.c ++++ b/drivers/crypto/qat/qat_c62xvf/adf_drv.c +@@ -119,8 +119,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + adf_init_hw_data_c62xiov(accel_dev->hw_device); + + /* Get Accelerators and Accelerators Engines masks */ +- hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); +- hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); ++ hw_data->accel_mask = hw_data->get_accel_mask(hw_data); ++ hw_data->ae_mask = hw_data->get_ae_mask(hw_data); + accel_pci_dev->sku = hw_data->get_sku(hw_data); + + /* Create dev top level debugfs entry */ +diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h +index 06952ece53d91..411a505e1f59f 100644 +--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h ++++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h +@@ -104,8 +104,8 @@ struct adf_etr_ring_data; + + struct adf_hw_device_data { + struct adf_hw_device_class *dev_class; +- u32 (*get_accel_mask)(u32 fuse); +- u32 (*get_ae_mask)(u32 fuse); ++ u32 (*get_accel_mask)(struct adf_hw_device_data *self); ++ u32 (*get_ae_mask)(struct adf_hw_device_data *self); + u32 (*get_sram_bar_id)(struct adf_hw_device_data *self); + u32 (*get_misc_bar_id)(struct adf_hw_device_data *self); + u32 (*get_etr_bar_id)(struct adf_hw_device_data *self); +@@ -131,6 +131,7 @@ struct adf_hw_device_data { + const char *fw_name; + const char *fw_mmp_name; + u32 fuses; ++ u32 straps; + u32 accel_capabilities_mask; + u32 instance_id; + u16 accel_mask; +diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c +index b40e81e0088f0..76d8470651b85 100644 +--- a/drivers/crypto/qat/qat_common/qat_hal.c ++++ b/drivers/crypto/qat/qat_common/qat_hal.c +@@ -346,11 +346,12 @@ static void qat_hal_put_wakeup_event(struct icp_qat_fw_loader_handle *handle, + + static int qat_hal_check_ae_alive(struct icp_qat_fw_loader_handle *handle) + { ++ unsigned long ae_mask = handle->hal_handle->ae_mask; + unsigned int base_cnt, cur_cnt; + unsigned char ae; + int times = MAX_RETRY_TIMES; + +- for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { ++ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { + base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); + base_cnt &= 0xffff; + +@@ -384,6 +385,7 @@ int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle, + + static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) + { ++ unsigned long ae_mask = handle->hal_handle->ae_mask; + unsigned int misc_ctl; + unsigned char ae; + +@@ -393,7 +395,7 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) + SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl & + (~MC_TIMESTAMP_ENABLE)); + +- for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { ++ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { + qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0); + qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0); + } +@@ -438,6 +440,7 @@ static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle) + #define SHRAM_INIT_CYCLES 2060 + int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) + { ++ unsigned long ae_mask = handle->hal_handle->ae_mask; + unsigned int ae_reset_csr; + unsigned char ae; + unsigned int clk_csr; +@@ -464,7 +467,7 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) + goto out_err; + + /* Set undefined power-up/reset states to reasonable default values */ +- for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { ++ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { + qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, + INIT_CTX_ENABLE_VALUE); + qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX, +@@ -570,10 +573,11 @@ static void qat_hal_enable_ctx(struct icp_qat_fw_loader_handle *handle, + + static void qat_hal_clear_xfer(struct icp_qat_fw_loader_handle *handle) + { ++ unsigned long ae_mask = handle->hal_handle->ae_mask; + unsigned char ae; + unsigned short reg; + +- for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { ++ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { + for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) { + qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS, + reg, 0); +@@ -585,6 +589,7 @@ static void qat_hal_clear_xfer(struct icp_qat_fw_loader_handle *handle) + + static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) + { ++ unsigned long ae_mask = handle->hal_handle->ae_mask; + unsigned char ae; + unsigned int ctx_mask = ICP_QAT_UCLO_AE_ALL_CTX; + int times = MAX_RETRY_TIMES; +@@ -592,7 +597,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) + unsigned int savctx = 0; + int ret = 0; + +- for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { ++ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { + csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); + csr_val &= ~(1 << MMC_SHARE_CS_BITPOS); + qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); +@@ -613,7 +618,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) + qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); + qat_hal_enable_ctx(handle, ae, ctx_mask); + } +- for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { ++ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { + /* wait for AE to finish */ + do { + ret = qat_hal_wait_cycles(handle, ae, 20, 1); +@@ -654,6 +659,8 @@ int qat_hal_init(struct adf_accel_dev *accel_dev) + struct adf_hw_device_data *hw_data = accel_dev->hw_device; + struct adf_bar *misc_bar = + &pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)]; ++ unsigned long ae_mask = hw_data->ae_mask; ++ unsigned int csr_val = 0; + struct adf_bar *sram_bar; + + handle = kzalloc(sizeof(*handle), GFP_KERNEL); +@@ -689,9 +696,7 @@ int qat_hal_init(struct adf_accel_dev *accel_dev) + /* create AE objects */ + handle->hal_handle->upc_mask = 0x1ffff; + handle->hal_handle->max_ustore = 0x4000; +- for (ae = 0; ae < ICP_QAT_UCLO_MAX_AE; ae++) { +- if (!(hw_data->ae_mask & (1 << ae))) +- continue; ++ for_each_set_bit(ae, &ae_mask, ICP_QAT_UCLO_MAX_AE) { + handle->hal_handle->aes[ae].free_addr = 0; + handle->hal_handle->aes[ae].free_size = + handle->hal_handle->max_ustore; +@@ -714,9 +719,7 @@ int qat_hal_init(struct adf_accel_dev *accel_dev) + } + + /* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */ +- for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { +- unsigned int csr_val = 0; +- ++ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { + csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE); + csr_val |= 0x1; + qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val); +diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c +index b975c263446db..6a0d01103136f 100644 +--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c ++++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c +@@ -24,15 +24,19 @@ static struct adf_hw_device_class dh895xcc_class = { + .instances = 0 + }; + +-static u32 get_accel_mask(u32 fuse) ++static u32 get_accel_mask(struct adf_hw_device_data *self) + { +- return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & +- ADF_DH895XCC_ACCELERATORS_MASK; ++ u32 fuses = self->fuses; ++ ++ return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & ++ ADF_DH895XCC_ACCELERATORS_MASK; + } + +-static u32 get_ae_mask(u32 fuse) ++static u32 get_ae_mask(struct adf_hw_device_data *self) + { +- return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK; ++ u32 fuses = self->fuses; ++ ++ return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK; + } + + static u32 get_num_accels(struct adf_hw_device_data *self) +@@ -131,11 +135,13 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev) + { + struct adf_hw_device_data *hw_device = accel_dev->hw_device; + struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR]; ++ unsigned long accel_mask = hw_device->accel_mask; ++ unsigned long ae_mask = hw_device->ae_mask; + void __iomem *csr = misc_bar->virt_addr; + unsigned int val, i; + + /* Enable Accel Engine error detection & correction */ +- for (i = 0; i < hw_device->get_num_aes(hw_device); i++) { ++ for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { + val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); + val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR; + ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); +@@ -145,7 +151,7 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev) + } + + /* Enable shared memory error detection & correction */ +- for (i = 0; i < hw_device->get_num_accels(hw_device); i++) { ++ for_each_set_bit(i, &accel_mask, ADF_DH895XCC_MAX_ACCELERATORS) { + val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); + val |= ADF_DH895XCC_ERRSSMSH_EN; + ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); +diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_drv.c b/drivers/crypto/qat/qat_dh895xcc/adf_drv.c +index ecb4f6f20e22b..d7941bc2bafd6 100644 +--- a/drivers/crypto/qat/qat_dh895xcc/adf_drv.c ++++ b/drivers/crypto/qat/qat_dh895xcc/adf_drv.c +@@ -128,8 +128,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + &hw_data->fuses); + + /* Get Accelerators and Accelerators Engines masks */ +- hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); +- hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); ++ hw_data->accel_mask = hw_data->get_accel_mask(hw_data); ++ hw_data->ae_mask = hw_data->get_ae_mask(hw_data); + accel_pci_dev->sku = hw_data->get_sku(hw_data); + /* If the device has no acceleration engines then ignore it. */ + if (!hw_data->accel_mask || !hw_data->ae_mask || +diff --git a/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c b/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c +index fc4cf141b1dea..7930e4c7883db 100644 +--- a/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c ++++ b/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c +@@ -11,12 +11,12 @@ static struct adf_hw_device_class dh895xcciov_class = { + .instances = 0 + }; + +-static u32 get_accel_mask(u32 fuse) ++static u32 get_accel_mask(struct adf_hw_device_data *self) + { + return ADF_DH895XCCIOV_ACCELERATORS_MASK; + } + +-static u32 get_ae_mask(u32 fuse) ++static u32 get_ae_mask(struct adf_hw_device_data *self) + { + return ADF_DH895XCCIOV_ACCELENGINES_MASK; + } +diff --git a/drivers/crypto/qat/qat_dh895xccvf/adf_drv.c b/drivers/crypto/qat/qat_dh895xccvf/adf_drv.c +index 737508ded37b4..29999da716cc9 100644 +--- a/drivers/crypto/qat/qat_dh895xccvf/adf_drv.c ++++ b/drivers/crypto/qat/qat_dh895xccvf/adf_drv.c +@@ -119,8 +119,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + adf_init_hw_data_dh895xcciov(accel_dev->hw_device); + + /* Get Accelerators and Accelerators Engines masks */ +- hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); +- hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); ++ hw_data->accel_mask = hw_data->get_accel_mask(hw_data); ++ hw_data->ae_mask = hw_data->get_ae_mask(hw_data); + accel_pci_dev->sku = hw_data->get_sku(hw_data); + + /* Create dev top level debugfs entry */ +-- +2.42.0 + diff --git a/queue-5.10/dmaengine-pxa_dma-remove-an-erroneous-bug_on-in-pxad.patch b/queue-5.10/dmaengine-pxa_dma-remove-an-erroneous-bug_on-in-pxad.patch new file mode 100644 index 00000000000..fcc6d9a4c36 --- /dev/null +++ b/queue-5.10/dmaengine-pxa_dma-remove-an-erroneous-bug_on-in-pxad.patch @@ -0,0 +1,43 @@ +From 9a3ee44021a0b5151cfb37e5ca6ba753cd83bf8f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 7 Oct 2023 13:13:09 +0200 +Subject: dmaengine: pxa_dma: Remove an erroneous BUG_ON() in pxad_free_desc() + +From: Christophe JAILLET + +[ Upstream commit 83c761f568733277ce1f7eb9dc9e890649c29a8c ] + +If pxad_alloc_desc() fails on the first dma_pool_alloc() call, then +sw_desc->nb_desc is zero. +In such a case pxad_free_desc() is called and it will BUG_ON(). + +Remove this erroneous BUG_ON(). + +It is also useless, because if "sw_desc->nb_desc == 0", then, on the first +iteration of the for loop, i is -1 and the loop will not be executed. +(both i and sw_desc->nb_desc are 'int') + +Fixes: a57e16cf0333 ("dmaengine: pxa: add pxa dmaengine driver") +Signed-off-by: Christophe JAILLET +Link: https://lore.kernel.org/r/c8fc5563c9593c914fde41f0f7d1489a21b45a9a.1696676782.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/dma/pxa_dma.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/dma/pxa_dma.c b/drivers/dma/pxa_dma.c +index 68d9d60c051d9..9ce75ff9fa1cc 100644 +--- a/drivers/dma/pxa_dma.c ++++ b/drivers/dma/pxa_dma.c +@@ -723,7 +723,6 @@ static void pxad_free_desc(struct virt_dma_desc *vd) + dma_addr_t dma; + struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); + +- BUG_ON(sw_desc->nb_desc == 0); + for (i = sw_desc->nb_desc - 1; i >= 0; i--) { + if (i > 0) + dma = sw_desc->hw_desc[i - 1]->ddadr; +-- +2.42.0 + diff --git a/queue-5.10/dmaengine-ti-edma-handle-irq_of_parse_and_map-errors.patch b/queue-5.10/dmaengine-ti-edma-handle-irq_of_parse_and_map-errors.patch new file mode 100644 index 00000000000..b5aa2014467 --- /dev/null +++ b/queue-5.10/dmaengine-ti-edma-handle-irq_of_parse_and_map-errors.patch @@ -0,0 +1,48 @@ +From 9d8b3f831ee2525eebda98fae75b45d93b0e6f7d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Sep 2023 15:59:59 +0300 +Subject: dmaengine: ti: edma: handle irq_of_parse_and_map() errors + +From: Dan Carpenter + +[ Upstream commit 14f6d317913f634920a640e9047aa2e66f5bdcb7 ] + +Zero is not a valid IRQ for in-kernel code and the irq_of_parse_and_map() +function returns zero on error. So this check for valid IRQs should only +accept values > 0. + +Fixes: 2b6b3b742019 ("ARM/dmaengine: edma: Merge the two drivers under drivers/dma/") +Signed-off-by: Dan Carpenter +Acked-by: Peter Ujfalusi +Link: https://lore.kernel.org/r/f15cb6a7-8449-4f79-98b6-34072f04edbc@moroto.mountain +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/dma/ti/edma.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c +index 35d81bd857f11..a1adc8d91fd8d 100644 +--- a/drivers/dma/ti/edma.c ++++ b/drivers/dma/ti/edma.c +@@ -2459,7 +2459,7 @@ static int edma_probe(struct platform_device *pdev) + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 0); + +- if (irq >= 0) { ++ if (irq > 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, +@@ -2475,7 +2475,7 @@ static int edma_probe(struct platform_device *pdev) + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 2); + +- if (irq >= 0) { ++ if (irq > 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, +-- +2.42.0 + diff --git a/queue-5.10/drm-bridge-tc358768-disable-non-continuous-clock-mod.patch b/queue-5.10/drm-bridge-tc358768-disable-non-continuous-clock-mod.patch new file mode 100644 index 00000000000..7b55b7c5cdf --- /dev/null +++ b/queue-5.10/drm-bridge-tc358768-disable-non-continuous-clock-mod.patch @@ -0,0 +1,78 @@ +From 9a167a960d2ead0be11668ad385fe37bf2c52a95 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Oct 2021 02:34:46 +0300 +Subject: drm/bridge: tc358768: Disable non-continuous clock mode + +From: Dmitry Osipenko + +[ Upstream commit fbc5a90e82c1131869e76ce5b082693b8a75c121 ] + +Non-continuous clock mode doesn't work because driver doesn't support it +properly. The bridge driver programs wrong bitfields that are required by +the non-continuous mode (BTACNTRL1 register bitfields are swapped in the +code), but fixing them doesn't help. + +Display panel of ASUS Transformer TF700T tablet supports non-continuous +mode and display doesn't work at all using that mode. There are no +device-trees that are actively using this DSI bridge in upstream yet, +so clearly the broken mode wasn't ever tested properly. It's a bit too +difficult to get LP mode working, hence let's disable the offending mode +for now and fall back to continuous mode. + +Tested-by: Andreas Westman Dorcsak # Asus TF700T +Tested-by: Maxim Schwalm #TF700T +Signed-off-by: Dmitry Osipenko +Reviewed-by: Robert Foss +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20211002233447.1105-5-digetx@gmail.com +Stable-dep-of: 66962d5c3c51 ("drm/bridge: tc358768: Fix bit updates") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/tc358768.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c +index a5e7afa5e6275..8f7460f011aea 100644 +--- a/drivers/gpu/drm/bridge/tc358768.c ++++ b/drivers/gpu/drm/bridge/tc358768.c +@@ -637,6 +637,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) + { + struct tc358768_priv *priv = bridge_to_tc358768(bridge); + struct mipi_dsi_device *dsi_dev = priv->output.dev; ++ unsigned long mode_flags = dsi_dev->mode_flags; + u32 val, val2, lptxcnt, hact, data_type; + s32 raw_val; + const struct drm_display_mode *mode; +@@ -644,6 +645,11 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) + u32 dsiclk, dsibclk; + int ret, i; + ++ if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { ++ dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n"); ++ mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; ++ } ++ + tc358768_hw_enable(priv); + + ret = tc358768_sw_reset(priv); +@@ -779,7 +785,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) + val |= BIT(i + 1); + tc358768_write(priv, TC358768_HSTXVREGEN, val); + +- if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) ++ if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); + + /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ +@@ -836,7 +842,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) + + val |= TC358768_DSI_CONTROL_TXMD; + +- if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) ++ if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + val |= TC358768_DSI_CONTROL_HSCKMD; + + if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET) +-- +2.42.0 + diff --git a/queue-5.10/drm-bridge-tc358768-fix-bit-updates.patch b/queue-5.10/drm-bridge-tc358768-fix-bit-updates.patch new file mode 100644 index 00000000000..87e7f0351a7 --- /dev/null +++ b/queue-5.10/drm-bridge-tc358768-fix-bit-updates.patch @@ -0,0 +1,66 @@ +From 9e04a8ba9601eda9f74e0a20118b36fb716c0cfc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Sep 2023 09:50:51 +0300 +Subject: drm/bridge: tc358768: Fix bit updates + +From: Tomi Valkeinen + +[ Upstream commit 66962d5c3c51377b9b90cae35b7e038950438e02 ] + +The driver has a few places where it does: + +if (thing_is_enabled_in_config) + update_thing_bit_in_hw() + +This means that if the thing is _not_ enabled, the bit never gets +cleared. This affects the h/vsyncs and continuous DSI clock bits. + +Fix the driver to always update the bit. + +Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") +Reviewed-by: Peter Ujfalusi +Tested-by: Maxim Schwalm # Asus TF700T +Tested-by: Marcel Ziswiler +Signed-off-by: Tomi Valkeinen +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20230906-tc358768-v4-4-31725f008a50@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/tc358768.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c +index 8f7460f011aea..48dab19f3e236 100644 +--- a/drivers/gpu/drm/bridge/tc358768.c ++++ b/drivers/gpu/drm/bridge/tc358768.c +@@ -785,8 +785,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) + val |= BIT(i + 1); + tc358768_write(priv, TC358768_HSTXVREGEN, val); + +- if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) +- tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); ++ tc358768_write(priv, TC358768_TXOPTIONCNTRL, ++ (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); + + /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ + val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); +@@ -822,11 +822,12 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) + tc358768_write(priv, TC358768_DSI_HACT, hact); + + /* VSYNC polarity */ +- if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) +- tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); ++ tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), ++ (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); ++ + /* HSYNC polarity */ +- if (mode->flags & DRM_MODE_FLAG_PHSYNC) +- tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); ++ tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), ++ (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); + + /* Start DSI Tx */ + tc358768_write(priv, TC358768_DSI_START, 0x1); +-- +2.42.0 + diff --git a/queue-5.10/drm-bridge-tc358768-fix-use-of-uninitialized-variabl.patch b/queue-5.10/drm-bridge-tc358768-fix-use-of-uninitialized-variabl.patch new file mode 100644 index 00000000000..09da6d583b6 --- /dev/null +++ b/queue-5.10/drm-bridge-tc358768-fix-use-of-uninitialized-variabl.patch @@ -0,0 +1,46 @@ +From c653ddac39da4bbad38d47fcb1436072079d4740 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Sep 2023 09:50:49 +0300 +Subject: drm/bridge: tc358768: Fix use of uninitialized variable + +From: Tomi Valkeinen + +[ Upstream commit a2d9036615f0adfa5b0a46bb2ce42ef1d9a04fbe ] + +smatch reports: + +drivers/gpu/drm/bridge/tc358768.c:223 tc358768_update_bits() error: uninitialized symbol 'orig'. + +Fix this by bailing out from tc358768_update_bits() if the +tc358768_read() produces an error. + +Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") +Reviewed-by: Peter Ujfalusi +Tested-by: Maxim Schwalm # Asus TF700T +Tested-by: Marcel Ziswiler +Signed-off-by: Tomi Valkeinen +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20230906-tc358768-v4-2-31725f008a50@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/tc358768.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c +index b4a69b2104514..a5e7afa5e6275 100644 +--- a/drivers/gpu/drm/bridge/tc358768.c ++++ b/drivers/gpu/drm/bridge/tc358768.c +@@ -217,6 +217,10 @@ static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, + u32 tmp, orig; + + tc358768_read(priv, reg, &orig); ++ ++ if (priv->error) ++ return; ++ + tmp = orig & ~mask; + tmp |= val & mask; + if (tmp != orig) +-- +2.42.0 + diff --git a/queue-5.10/drm-mediatek-fix-iommu-fault-during-crtc-enabling.patch b/queue-5.10/drm-mediatek-fix-iommu-fault-during-crtc-enabling.patch new file mode 100644 index 00000000000..a6644f7d61e --- /dev/null +++ b/queue-5.10/drm-mediatek-fix-iommu-fault-during-crtc-enabling.patch @@ -0,0 +1,55 @@ +From f6df6d99e696725410c9b34f1522deec2fbafb35 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 9 Aug 2023 20:57:22 +0800 +Subject: drm/mediatek: Fix iommu fault during crtc enabling + +From: Jason-JH.Lin + +[ Upstream commit 53412dc2905401207f264dc30890f6b9e41524a6 ] + +The difference between drm_atomic_helper_commit_tail() and +drm_atomic_helper_commit_tail_rpm() is +drm_atomic_helper_commit_tail() will commit plane first and +then enable crtc, drm_atomic_helper_commit_tail_rpm() will +enable crtc first and then commit plane. + +Before mediatek-drm enables crtc, the power and clk required +by OVL have not been turned on, so the commit plane cannot be +committed before crtc is enabled. That means OVL layer should +not be enabled before crtc is enabled. +Therefore, the atomic_commit_tail of mediatek-drm is hooked with +drm_atomic_helper_commit_tail_rpm(). + +Another reason is that the plane_state of drm_atomic_state is not +synchronized with the plane_state stored in mtk_crtc during crtc enablng, +so just set all planes to disabled. + +Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.") +Signed-off-by: Jason-JH.Lin +Reviewed-by: Alexandre Mergnat +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: CK Hu +Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20230809125722.24112-3-jason-jh.lin@mediatek.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +index e83b1c406b96a..cc3cb5b63d444 100644 +--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c ++++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +@@ -320,6 +320,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) + unsigned int local_layer; + + plane_state = to_mtk_plane_state(plane->state); ++ ++ /* should not enable layer before crtc enabled */ ++ plane_state->pending.enable = false; + comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); + if (comp) + mtk_ddp_comp_layer_config(comp, local_layer, +-- +2.42.0 + diff --git a/queue-5.10/drm-radeon-possible-buffer-overflow.patch b/queue-5.10/drm-radeon-possible-buffer-overflow.patch new file mode 100644 index 00000000000..cfa7c0702d7 --- /dev/null +++ b/queue-5.10/drm-radeon-possible-buffer-overflow.patch @@ -0,0 +1,47 @@ +From 2065197d5cc9dca5f71c8815b565264eb1b8c990 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 17 Aug 2023 19:33:49 +0800 +Subject: drm/radeon: possible buffer overflow + +From: Konstantin Meskhidze + +[ Upstream commit dd05484f99d16715a88eedfca363828ef9a4c2d4 ] + +Buffer 'afmt_status' of size 6 could overflow, since index 'afmt_idx' is +checked after access. + +Fixes: 5cc4e5fc293b ("drm/radeon: Cleanup HDMI audio interrupt handling for evergreen") +Co-developed-by: Ivanov Mikhail +Signed-off-by: Konstantin Meskhidze +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/evergreen.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c +index 14d90dc376e71..061ef6c008592 100644 +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -4819,14 +4819,15 @@ int evergreen_irq_process(struct radeon_device *rdev) + break; + case 44: /* hdmi */ + afmt_idx = src_data; +- if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG)) +- DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); +- + if (afmt_idx > 5) { + DRM_ERROR("Unhandled interrupt: %d %d\n", + src_id, src_data); + break; + } ++ ++ if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG)) ++ DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); ++ + afmt_status[afmt_idx] &= ~AFMT_AZ_FORMAT_WTRIG; + queue_hdmi = true; + DRM_DEBUG("IH: HDMI%d\n", afmt_idx + 1); +-- +2.42.0 + diff --git a/queue-5.10/drm-rockchip-cdn-dp-fix-some-error-handling-paths-in.patch b/queue-5.10/drm-rockchip-cdn-dp-fix-some-error-handling-paths-in.patch new file mode 100644 index 00000000000..22ca7f99f9d --- /dev/null +++ b/queue-5.10/drm-rockchip-cdn-dp-fix-some-error-handling-paths-in.patch @@ -0,0 +1,60 @@ +From 61a9d3fc2b33c83cd2560c181934dd64b9e95c8c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Sep 2023 19:34:31 +0200 +Subject: drm/rockchip: cdn-dp: Fix some error handling paths in cdn_dp_probe() + +From: Christophe JAILLET + +[ Upstream commit 44b968d0d0868b7a9b7a5c64464ada464ff4d532 ] + +cdn_dp_audio_codec_init() can fail. So add some error handling. + +If component_add() fails, the previous cdn_dp_audio_codec_init() call +should be undone, as already done in the remove function. + +Fixes: 88582f564692 ("drm/rockchip: cdn-dp: Don't unregister audio dev when unbinding") +Signed-off-by: Christophe JAILLET +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/8494a41602fadb7439630921a9779640698f2f9f.1693676045.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/rockchip/cdn-dp-core.c | 15 +++++++++++++-- + 1 file changed, 13 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c +index adeaa0140f0f7..53cad1003ad77 100644 +--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c ++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c +@@ -1145,6 +1145,7 @@ static int cdn_dp_probe(struct platform_device *pdev) + struct cdn_dp_device *dp; + struct extcon_dev *extcon; + struct phy *phy; ++ int ret; + int i; + + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); +@@ -1185,9 +1186,19 @@ static int cdn_dp_probe(struct platform_device *pdev) + mutex_init(&dp->lock); + dev_set_drvdata(dev, dp); + +- cdn_dp_audio_codec_init(dp, dev); ++ ret = cdn_dp_audio_codec_init(dp, dev); ++ if (ret) ++ return ret; ++ ++ ret = component_add(dev, &cdn_dp_component_ops); ++ if (ret) ++ goto err_audio_deinit; + +- return component_add(dev, &cdn_dp_component_ops); ++ return 0; ++ ++err_audio_deinit: ++ platform_device_unregister(dp->audio_pdev); ++ return ret; + } + + static int cdn_dp_remove(struct platform_device *pdev) +-- +2.42.0 + diff --git a/queue-5.10/drm-rockchip-fix-type-promotion-bug-in-rockchip_gem_.patch b/queue-5.10/drm-rockchip-fix-type-promotion-bug-in-rockchip_gem_.patch new file mode 100644 index 00000000000..bde6cb9e0c3 --- /dev/null +++ b/queue-5.10/drm-rockchip-fix-type-promotion-bug-in-rockchip_gem_.patch @@ -0,0 +1,40 @@ +From f8b2ec56fc69a54317e3ef2c7c162951fd95eb74 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 11 Oct 2023 11:01:48 +0300 +Subject: drm/rockchip: Fix type promotion bug in rockchip_gem_iommu_map() + +From: Dan Carpenter + +[ Upstream commit 6471da5ee311d53ef46eebcb7725bc94266cc0cf ] + +The "ret" variable is declared as ssize_t and it can hold negative error +codes but the "rk_obj->base.size" variable is type size_t. This means +that when we compare them, they are both type promoted to size_t and the +negative error code becomes a high unsigned value and is treated as +success. Add a cast to fix this. + +Fixes: 38f993b7c59e ("drm/rockchip: Do not use DMA mapping API if attached to IOMMU domain") +Signed-off-by: Dan Carpenter +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/2bfa28b5-145d-4b9e-a18a-98819dd686ce@moroto.mountain +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +index 22ff4a5929768..6038aafa29c68 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +@@ -38,7 +38,7 @@ static int rockchip_gem_iommu_map(struct rockchip_gem_object *rk_obj) + + ret = iommu_map_sgtable(private->domain, rk_obj->dma_addr, rk_obj->sgt, + prot); +- if (ret < rk_obj->base.size) { ++ if (ret < (ssize_t)rk_obj->base.size) { + DRM_ERROR("failed to map buffer: size=%zd request_size=%zd\n", + ret, rk_obj->base.size); + ret = -ENOMEM; +-- +2.42.0 + diff --git a/queue-5.10/drm-rockchip-vop-fix-call-to-crtc-reset-helper.patch b/queue-5.10/drm-rockchip-vop-fix-call-to-crtc-reset-helper.patch new file mode 100644 index 00000000000..a206024aeb6 --- /dev/null +++ b/queue-5.10/drm-rockchip-vop-fix-call-to-crtc-reset-helper.patch @@ -0,0 +1,43 @@ +From 5a9904fad7561338e8545aa004b00111822ead81 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Jun 2023 22:33:20 +0000 +Subject: drm/rockchip: vop: Fix call to crtc reset helper + +From: Jonas Karlman + +[ Upstream commit 5aacd290837828c089a83ac9795c74c4c9e2c923 ] + +Allocation of crtc_state may fail in vop_crtc_reset, causing an invalid +pointer to be passed to __drm_atomic_helper_crtc_reset. + +Fix this by adding a NULL check of crtc_state, similar to other drivers. + +Fixes: 01e2eaf40c9d ("drm/rockchip: Convert to using __drm_atomic_helper_crtc_reset() for reset.") +Signed-off-by: Jonas Karlman +Reviewed-by: Sascha Hauer +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20230621223311.2239547-4-jonas@kwiboo.se +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 2f1e55a905d42..05fcc9e078d6d 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1559,7 +1559,10 @@ static void vop_crtc_reset(struct drm_crtc *crtc) + if (crtc->state) + vop_crtc_destroy_state(crtc, crtc->state); + +- __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); ++ if (crtc_state) ++ __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); ++ else ++ __drm_atomic_helper_crtc_reset(crtc, NULL); + } + + #ifdef CONFIG_DRM_ANALOGIX_DP +-- +2.42.0 + diff --git a/queue-5.10/drm-rockchip-vop-fix-reset-of-state-in-duplicate-sta.patch b/queue-5.10/drm-rockchip-vop-fix-reset-of-state-in-duplicate-sta.patch new file mode 100644 index 00000000000..a1fc9ae5810 --- /dev/null +++ b/queue-5.10/drm-rockchip-vop-fix-reset-of-state-in-duplicate-sta.patch @@ -0,0 +1,42 @@ +From 7ab33da220b3050fbfb03cc1f7166fde88c537c6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Jun 2023 22:33:17 +0000 +Subject: drm/rockchip: vop: Fix reset of state in duplicate state crtc funcs + +From: Jonas Karlman + +[ Upstream commit 13fc28804bf10ca0b7bce3efbba95c534836d7ca ] + +struct rockchip_crtc_state members such as output_type, output_bpc and +enable_afbc is always reset to zero in the atomic_duplicate_state crtc +funcs. + +Fix this by using kmemdup on the subclass rockchip_crtc_state struct. + +Fixes: 4e257d9eee23 ("drm/rockchip: get rid of rockchip_drm_crtc_mode_config") +Signed-off-by: Jonas Karlman +Reviewed-by: Sascha Hauer +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20230621223311.2239547-2-jonas@kwiboo.se +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 65dde9df9793e..2f1e55a905d42 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1533,7 +1533,8 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) + if (WARN_ON(!crtc->state)) + return NULL; + +- rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); ++ rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state), ++ sizeof(*rockchip_state), GFP_KERNEL); + if (!rockchip_state) + return NULL; + +-- +2.42.0 + diff --git a/queue-5.10/ext4-move-ix-sanity-check-to-corrent-position.patch b/queue-5.10/ext4-move-ix-sanity-check-to-corrent-position.patch new file mode 100644 index 00000000000..7c041dbe658 --- /dev/null +++ b/queue-5.10/ext4-move-ix-sanity-check-to-corrent-position.patch @@ -0,0 +1,51 @@ +From 4e9b78c5971921ae621636d14da38d05dfe7eacc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Sep 2023 09:33:41 +0800 +Subject: ext4: move 'ix' sanity check to corrent position + +From: Gou Hao + +[ Upstream commit af90a8f4a09ec4a3de20142e37f37205d4687f28 ] + +Check 'ix' before it is used. + +Fixes: 80e675f906db ("ext4: optimize memmmove lengths in extent/index insertions") +Signed-off-by: Gou Hao +Link: https://lore.kernel.org/r/20230906013341.7199-1-gouhao@uniontech.com +Signed-off-by: Theodore Ts'o +Signed-off-by: Sasha Levin +--- + fs/ext4/extents.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c +index 2c2e1cc43e0e8..193b13630ac1e 100644 +--- a/fs/ext4/extents.c ++++ b/fs/ext4/extents.c +@@ -1003,6 +1003,11 @@ static int ext4_ext_insert_index(handle_t *handle, struct inode *inode, + ix = curp->p_idx; + } + ++ if (unlikely(ix > EXT_MAX_INDEX(curp->p_hdr))) { ++ EXT4_ERROR_INODE(inode, "ix > EXT_MAX_INDEX!"); ++ return -EFSCORRUPTED; ++ } ++ + len = EXT_LAST_INDEX(curp->p_hdr) - ix + 1; + BUG_ON(len < 0); + if (len > 0) { +@@ -1012,11 +1017,6 @@ static int ext4_ext_insert_index(handle_t *handle, struct inode *inode, + memmove(ix + 1, ix, len * sizeof(struct ext4_extent_idx)); + } + +- if (unlikely(ix > EXT_MAX_INDEX(curp->p_hdr))) { +- EXT4_ERROR_INODE(inode, "ix > EXT_MAX_INDEX!"); +- return -EFSCORRUPTED; +- } +- + ix->ei_block = cpu_to_le32(logical); + ext4_idx_store_pblock(ix, ptr); + le16_add_cpu(&curp->p_hdr->eh_entries, 1); +-- +2.42.0 + diff --git a/queue-5.10/f2fs-add-compress_mode-mount-option.patch b/queue-5.10/f2fs-add-compress_mode-mount-option.patch new file mode 100644 index 00000000000..70ec6f33e70 --- /dev/null +++ b/queue-5.10/f2fs-add-compress_mode-mount-option.patch @@ -0,0 +1,255 @@ +From 9aafb2b095b5ccb863934bc226baf5b74a63f109 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Dec 2020 13:08:02 +0900 +Subject: f2fs: add compress_mode mount option + +From: Daeho Jeong + +[ Upstream commit 602a16d58e9aab3c423bcf051033ea6c9e8a6d37 ] + +We will add a new "compress_mode" mount option to control file +compression mode. This supports "fs" and "user". In "fs" mode (default), +f2fs does automatic compression on the compression enabled files. +In "user" mode, f2fs disables the automaic compression and gives the +user discretion of choosing the target file and the timing. It means +the user can do manual compression/decompression on the compression +enabled files using ioctls. + +Signed-off-by: Daeho Jeong +Reviewed-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Stable-dep-of: 7e1b150fece0 ("f2fs: compress: fix to avoid redundant compress extension") +Signed-off-by: Sasha Levin +--- + Documentation/filesystems/f2fs.rst | 35 ++++++++++++++++++++++++++++++ + fs/f2fs/compress.c | 2 +- + fs/f2fs/data.c | 2 +- + fs/f2fs/f2fs.h | 30 +++++++++++++++++++++++++ + fs/f2fs/segment.c | 2 +- + fs/f2fs/super.c | 23 ++++++++++++++++++++ + 6 files changed, 91 insertions(+), 3 deletions(-) + +diff --git a/Documentation/filesystems/f2fs.rst b/Documentation/filesystems/f2fs.rst +index 3d21a9e86995f..de2bacc418fee 100644 +--- a/Documentation/filesystems/f2fs.rst ++++ b/Documentation/filesystems/f2fs.rst +@@ -261,6 +261,13 @@ compress_extension=%s Support adding specified extension, so that f2fs can enab + Note that, there is one reserved special extension '*', it + can be set to enable compression for all files. + compress_chksum Support verifying chksum of raw data in compressed cluster. ++compress_mode=%s Control file compression mode. This supports "fs" and "user" ++ modes. In "fs" mode (default), f2fs does automatic compression ++ on the compression enabled files. In "user" mode, f2fs disables ++ the automaic compression and gives the user discretion of ++ choosing the target file and the timing. The user can do manual ++ compression/decompression on the compression enabled files using ++ ioctls. + inlinecrypt When possible, encrypt/decrypt the contents of encrypted + files using the blk-crypto framework rather than + filesystem-layer encryption. This allows the use of +@@ -811,6 +818,34 @@ Compress metadata layout:: + | data length | data chksum | reserved | compressed data | + +-------------+-------------+----------+----------------------------+ + ++Compression mode ++-------------------------- ++ ++f2fs supports "fs" and "user" compression modes with "compression_mode" mount option. ++With this option, f2fs provides a choice to select the way how to compress the ++compression enabled files (refer to "Compression implementation" section for how to ++enable compression on a regular inode). ++ ++1) compress_mode=fs ++This is the default option. f2fs does automatic compression in the writeback of the ++compression enabled files. ++ ++2) compress_mode=user ++This disables the automaic compression and gives the user discretion of choosing the ++target file and the timing. The user can do manual compression/decompression on the ++compression enabled files using F2FS_IOC_DECOMPRESS_FILE and F2FS_IOC_COMPRESS_FILE ++ioctls like the below. ++ ++To decompress a file, ++ ++fd = open(filename, O_WRONLY, 0); ++ret = ioctl(fd, F2FS_IOC_DECOMPRESS_FILE); ++ ++To compress a file, ++ ++fd = open(filename, O_WRONLY, 0); ++ret = ioctl(fd, F2FS_IOC_COMPRESS_FILE); ++ + NVMe Zoned Namespace devices + ---------------------------- + +diff --git a/fs/f2fs/compress.c b/fs/f2fs/compress.c +index db8360ae96caf..8da6df3bfb03f 100644 +--- a/fs/f2fs/compress.c ++++ b/fs/f2fs/compress.c +@@ -929,7 +929,7 @@ int f2fs_is_compressed_cluster(struct inode *inode, pgoff_t index) + + static bool cluster_may_compress(struct compress_ctx *cc) + { +- if (!f2fs_compressed_file(cc->inode)) ++ if (!f2fs_need_compress_data(cc->inode)) + return false; + if (f2fs_is_atomic_file(cc->inode)) + return false; +diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c +index e0533cffbb076..fc6c88e80cf4f 100644 +--- a/fs/f2fs/data.c ++++ b/fs/f2fs/data.c +@@ -3222,7 +3222,7 @@ static inline bool __should_serialize_io(struct inode *inode, + if (IS_NOQUOTA(inode)) + return false; + +- if (f2fs_compressed_file(inode)) ++ if (f2fs_need_compress_data(inode)) + return true; + if (wbc->sync_mode != WB_SYNC_ALL) + return true; +diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h +index 6dfefbf54917d..6a9f4dcea06d6 100644 +--- a/fs/f2fs/f2fs.h ++++ b/fs/f2fs/f2fs.h +@@ -150,6 +150,7 @@ struct f2fs_mount_info { + unsigned char compress_log_size; /* cluster log size */ + bool compress_chksum; /* compressed data chksum */ + unsigned char compress_ext_cnt; /* extension count */ ++ int compress_mode; /* compression mode */ + unsigned char extensions[COMPRESS_EXT_NUM][F2FS_EXTENSION_LEN]; /* extensions */ + }; + +@@ -681,6 +682,7 @@ enum { + FI_COMPRESSED_FILE, /* indicate file's data can be compressed */ + FI_COMPRESS_CORRUPT, /* indicate compressed cluster is corrupted */ + FI_MMAP_FILE, /* indicate file was mmapped */ ++ FI_ENABLE_COMPRESS, /* enable compression in "user" compression mode */ + FI_MAX, /* max flag, never be used */ + }; + +@@ -1255,6 +1257,18 @@ enum fsync_mode { + FSYNC_MODE_NOBARRIER, /* fsync behaves nobarrier based on posix */ + }; + ++enum { ++ COMPR_MODE_FS, /* ++ * automatically compress compression ++ * enabled files ++ */ ++ COMPR_MODE_USER, /* ++ * automatical compression is disabled. ++ * user can control the file compression ++ * using ioctls ++ */ ++}; ++ + /* + * this value is set in page as a private data which indicate that + * the page is atomically written, and it is in inmem_pages list. +@@ -2795,6 +2809,22 @@ static inline int f2fs_compressed_file(struct inode *inode) + is_inode_flag_set(inode, FI_COMPRESSED_FILE); + } + ++static inline bool f2fs_need_compress_data(struct inode *inode) ++{ ++ int compress_mode = F2FS_OPTION(F2FS_I_SB(inode)).compress_mode; ++ ++ if (!f2fs_compressed_file(inode)) ++ return false; ++ ++ if (compress_mode == COMPR_MODE_FS) ++ return true; ++ else if (compress_mode == COMPR_MODE_USER && ++ is_inode_flag_set(inode, FI_ENABLE_COMPRESS)) ++ return true; ++ ++ return false; ++} ++ + static inline unsigned int addrs_per_inode(struct inode *inode) + { + unsigned int addrs = CUR_ADDRS_PER_INODE(inode) - +diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c +index a27a934292715..ad30908ac99f3 100644 +--- a/fs/f2fs/segment.c ++++ b/fs/f2fs/segment.c +@@ -3296,7 +3296,7 @@ static int __get_segment_type_6(struct f2fs_io_info *fio) + else + return CURSEG_COLD_DATA; + } +- if (file_is_cold(inode) || f2fs_compressed_file(inode)) ++ if (file_is_cold(inode) || f2fs_need_compress_data(inode)) + return CURSEG_COLD_DATA; + if (file_is_hot(inode) || + is_inode_flag_set(inode, FI_HOT_DATA) || +diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c +index 065aa01958e95..1281b59da6a2a 100644 +--- a/fs/f2fs/super.c ++++ b/fs/f2fs/super.c +@@ -147,6 +147,7 @@ enum { + Opt_compress_log_size, + Opt_compress_extension, + Opt_compress_chksum, ++ Opt_compress_mode, + Opt_atgc, + Opt_err, + }; +@@ -216,6 +217,7 @@ static match_table_t f2fs_tokens = { + {Opt_compress_log_size, "compress_log_size=%u"}, + {Opt_compress_extension, "compress_extension=%s"}, + {Opt_compress_chksum, "compress_chksum"}, ++ {Opt_compress_mode, "compress_mode=%s"}, + {Opt_atgc, "atgc"}, + {Opt_err, NULL}, + }; +@@ -979,11 +981,26 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + case Opt_compress_chksum: + F2FS_OPTION(sbi).compress_chksum = true; + break; ++ case Opt_compress_mode: ++ name = match_strdup(&args[0]); ++ if (!name) ++ return -ENOMEM; ++ if (!strcmp(name, "fs")) { ++ F2FS_OPTION(sbi).compress_mode = COMPR_MODE_FS; ++ } else if (!strcmp(name, "user")) { ++ F2FS_OPTION(sbi).compress_mode = COMPR_MODE_USER; ++ } else { ++ kfree(name); ++ return -EINVAL; ++ } ++ kfree(name); ++ break; + #else + case Opt_compress_algorithm: + case Opt_compress_log_size: + case Opt_compress_extension: + case Opt_compress_chksum: ++ case Opt_compress_mode: + f2fs_info(sbi, "compression options not supported"); + break; + #endif +@@ -1571,6 +1588,11 @@ static inline void f2fs_show_compress_options(struct seq_file *seq, + + if (F2FS_OPTION(sbi).compress_chksum) + seq_puts(seq, ",compress_chksum"); ++ ++ if (F2FS_OPTION(sbi).compress_mode == COMPR_MODE_FS) ++ seq_printf(seq, ",compress_mode=%s", "fs"); ++ else if (F2FS_OPTION(sbi).compress_mode == COMPR_MODE_USER) ++ seq_printf(seq, ",compress_mode=%s", "user"); + } + + static int f2fs_show_options(struct seq_file *seq, struct dentry *root) +@@ -1720,6 +1742,7 @@ static void default_options(struct f2fs_sb_info *sbi) + F2FS_OPTION(sbi).compress_algorithm = COMPRESS_LZ4; + F2FS_OPTION(sbi).compress_log_size = MIN_COMPRESS_LOG_SIZE; + F2FS_OPTION(sbi).compress_ext_cnt = 0; ++ F2FS_OPTION(sbi).compress_mode = COMPR_MODE_FS; + F2FS_OPTION(sbi).bggc_mode = BGGC_MODE_ON; + + sbi->sb->s_flags &= ~SB_INLINECRYPT; +-- +2.42.0 + diff --git a/queue-5.10/f2fs-compress-add-nocompress-extensions-support.patch b/queue-5.10/f2fs-compress-add-nocompress-extensions-support.patch new file mode 100644 index 00000000000..4c64bc5a626 --- /dev/null +++ b/queue-5.10/f2fs-compress-add-nocompress-extensions-support.patch @@ -0,0 +1,296 @@ +From 107a40f56eb74851697bb37513bc058300424cb8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Jun 2021 19:15:08 +0800 +Subject: f2fs: compress: add nocompress extensions support + +From: Fengnan Chang + +[ Upstream commit 151b1982be5d9f4ca641687ee1a4bb4fba5d26cf ] + +When we create a directory with enable compression, all file write into +directory will try to compress.But sometimes we may know, new file +cannot meet compression ratio requirements. +We need a nocompress extension to skip those files to avoid unnecessary +compress page test. + +After add nocompress_extension, the priority should be: +dir_flag < comp_extention,nocompress_extension < comp_file_flag, +no_comp_file_flag. + +Priority in between FS_COMPR_FL, FS_NOCOMP_FS, extensions: + * compress_extension=so; nocompress_extension=zip; chattr +c dir; + touch dir/foo.so; touch dir/bar.zip; touch dir/baz.txt; then foo.so + and baz.txt should be compresse, bar.zip should be non-compressed. + chattr +c dir/bar.zip can enable compress on bar.zip. + * compress_extension=so; nocompress_extension=zip; chattr -c dir; + touch dir/foo.so; touch dir/bar.zip; touch dir/baz.txt; then foo.so + should be compresse, bar.zip and baz.txt should be non-compressed. + chattr+c dir/bar.zip; chattr+c dir/baz.txt; can enable compress on + bar.zip and baz.txt. + +Signed-off-by: Fengnan Chang +Reviewed-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Stable-dep-of: 7e1b150fece0 ("f2fs: compress: fix to avoid redundant compress extension") +Signed-off-by: Sasha Levin +--- + Documentation/filesystems/f2fs.rst | 31 +++++++++++- + fs/f2fs/f2fs.h | 2 + + fs/f2fs/namei.c | 20 ++++++-- + fs/f2fs/super.c | 79 +++++++++++++++++++++++++++++- + 4 files changed, 125 insertions(+), 7 deletions(-) + +diff --git a/Documentation/filesystems/f2fs.rst b/Documentation/filesystems/f2fs.rst +index 9e302d3dd85a6..ae7b9fe07d5c8 100644 +--- a/Documentation/filesystems/f2fs.rst ++++ b/Documentation/filesystems/f2fs.rst +@@ -265,6 +265,18 @@ compress_extension=%s Support adding specified extension, so that f2fs can enab + For other files, we can still enable compression via ioctl. + Note that, there is one reserved special extension '*', it + can be set to enable compression for all files. ++nocompress_extension=%s Support adding specified extension, so that f2fs can disable ++ compression on those corresponding files, just contrary to compression extension. ++ If you know exactly which files cannot be compressed, you can use this. ++ The same extension name can't appear in both compress and nocompress ++ extension at the same time. ++ If the compress extension specifies all files, the types specified by the ++ nocompress extension will be treated as special cases and will not be compressed. ++ Don't allow use '*' to specifie all file in nocompress extension. ++ After add nocompress_extension, the priority should be: ++ dir_flag < comp_extention,nocompress_extension < comp_file_flag,no_comp_file_flag. ++ See more in compression sections. ++ + compress_chksum Support verifying chksum of raw data in compressed cluster. + compress_mode=%s Control file compression mode. This supports "fs" and "user" + modes. In "fs" mode (default), f2fs does automatic compression +@@ -798,13 +810,30 @@ Compression implementation + all logical blocks in cluster contain valid data and compress ratio of + cluster data is lower than specified threshold. + +-- To enable compression on regular inode, there are three ways: ++- To enable compression on regular inode, there are four ways: + + * chattr +c file + * chattr +c dir; touch dir/file + * mount w/ -o compress_extension=ext; touch file.ext + * mount w/ -o compress_extension=*; touch any_file + ++- To disable compression on regular inode, there are two ways: ++ ++ * chattr -c file ++ * mount w/ -o nocompress_extension=ext; touch file.ext ++ ++- Priority in between FS_COMPR_FL, FS_NOCOMP_FS, extensions: ++ ++ * compress_extension=so; nocompress_extension=zip; chattr +c dir; touch ++ dir/foo.so; touch dir/bar.zip; touch dir/baz.txt; then foo.so and baz.txt ++ should be compresse, bar.zip should be non-compressed. chattr +c dir/bar.zip ++ can enable compress on bar.zip. ++ * compress_extension=so; nocompress_extension=zip; chattr -c dir; touch ++ dir/foo.so; touch dir/bar.zip; touch dir/baz.txt; then foo.so should be ++ compresse, bar.zip and baz.txt should be non-compressed. ++ chattr+c dir/bar.zip; chattr+c dir/baz.txt; can enable compress on bar.zip ++ and baz.txt. ++ + - At this point, compression feature doesn't expose compressed space to user + directly in order to guarantee potential data updates later to the space. + Instead, the main goal is to reduce data writes to flash disk as much as +diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h +index 01e365aefbc97..cda5dbda7f86d 100644 +--- a/fs/f2fs/f2fs.h ++++ b/fs/f2fs/f2fs.h +@@ -151,8 +151,10 @@ struct f2fs_mount_info { + unsigned char compress_level; /* compress level */ + bool compress_chksum; /* compressed data chksum */ + unsigned char compress_ext_cnt; /* extension count */ ++ unsigned char nocompress_ext_cnt; /* nocompress extension count */ + int compress_mode; /* compression mode */ + unsigned char extensions[COMPRESS_EXT_NUM][F2FS_EXTENSION_LEN]; /* extensions */ ++ unsigned char noextensions[COMPRESS_EXT_NUM][F2FS_EXTENSION_LEN]; /* extensions */ + }; + + #define F2FS_FEATURE_ENCRYPT 0x0001 +diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c +index 72b109685db47..516b7d27336ec 100644 +--- a/fs/f2fs/namei.c ++++ b/fs/f2fs/namei.c +@@ -289,14 +289,16 @@ static void set_compress_inode(struct f2fs_sb_info *sbi, struct inode *inode, + const unsigned char *name) + { + __u8 (*extlist)[F2FS_EXTENSION_LEN] = sbi->raw_super->extension_list; +- unsigned char (*ext)[F2FS_EXTENSION_LEN]; +- unsigned int ext_cnt = F2FS_OPTION(sbi).compress_ext_cnt; ++ unsigned char (*noext)[F2FS_EXTENSION_LEN] = F2FS_OPTION(sbi).noextensions; ++ unsigned char (*ext)[F2FS_EXTENSION_LEN] = F2FS_OPTION(sbi).extensions; ++ unsigned char ext_cnt = F2FS_OPTION(sbi).compress_ext_cnt; ++ unsigned char noext_cnt = F2FS_OPTION(sbi).nocompress_ext_cnt; + int i, cold_count, hot_count; + + if (!f2fs_sb_has_compression(sbi) || +- is_inode_flag_set(inode, FI_COMPRESSED_FILE) || + F2FS_I(inode)->i_flags & F2FS_NOCOMP_FL || +- !f2fs_may_compress(inode)) ++ !f2fs_may_compress(inode) || ++ (!ext_cnt && !noext_cnt)) + return; + + down_read(&sbi->sb_lock); +@@ -313,7 +315,15 @@ static void set_compress_inode(struct f2fs_sb_info *sbi, struct inode *inode, + + up_read(&sbi->sb_lock); + +- ext = F2FS_OPTION(sbi).extensions; ++ for (i = 0; i < noext_cnt; i++) { ++ if (is_extension_exist(name, noext[i], false)) { ++ f2fs_disable_compressed_file(inode); ++ return; ++ } ++ } ++ ++ if (is_inode_flag_set(inode, FI_COMPRESSED_FILE)) ++ return; + + for (i = 0; i < ext_cnt; i++) { + if (!is_extension_exist(name, ext[i], false)) +diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c +index d49160328d53b..daae61df66ffa 100644 +--- a/fs/f2fs/super.c ++++ b/fs/f2fs/super.c +@@ -148,6 +148,7 @@ enum { + Opt_compress_algorithm, + Opt_compress_log_size, + Opt_compress_extension, ++ Opt_nocompress_extension, + Opt_compress_chksum, + Opt_compress_mode, + Opt_atgc, +@@ -218,6 +219,7 @@ static match_table_t f2fs_tokens = { + {Opt_compress_algorithm, "compress_algorithm=%s"}, + {Opt_compress_log_size, "compress_log_size=%u"}, + {Opt_compress_extension, "compress_extension=%s"}, ++ {Opt_nocompress_extension, "nocompress_extension=%s"}, + {Opt_compress_chksum, "compress_chksum"}, + {Opt_compress_mode, "compress_mode=%s"}, + {Opt_atgc, "atgc"}, +@@ -507,6 +509,43 @@ static int f2fs_set_test_dummy_encryption(struct super_block *sb, + } + + #ifdef CONFIG_F2FS_FS_COMPRESSION ++/* ++ * 1. The same extension name cannot not appear in both compress and non-compress extension ++ * at the same time. ++ * 2. If the compress extension specifies all files, the types specified by the non-compress ++ * extension will be treated as special cases and will not be compressed. ++ * 3. Don't allow the non-compress extension specifies all files. ++ */ ++static int f2fs_test_compress_extension(struct f2fs_sb_info *sbi) ++{ ++ unsigned char (*ext)[F2FS_EXTENSION_LEN]; ++ unsigned char (*noext)[F2FS_EXTENSION_LEN]; ++ int ext_cnt, noext_cnt, index = 0, no_index = 0; ++ ++ ext = F2FS_OPTION(sbi).extensions; ++ ext_cnt = F2FS_OPTION(sbi).compress_ext_cnt; ++ noext = F2FS_OPTION(sbi).noextensions; ++ noext_cnt = F2FS_OPTION(sbi).nocompress_ext_cnt; ++ ++ if (!noext_cnt) ++ return 0; ++ ++ for (no_index = 0; no_index < noext_cnt; no_index++) { ++ if (!strcasecmp("*", noext[no_index])) { ++ f2fs_info(sbi, "Don't allow the nocompress extension specifies all files"); ++ return -EINVAL; ++ } ++ for (index = 0; index < ext_cnt; index++) { ++ if (!strcasecmp(ext[index], noext[no_index])) { ++ f2fs_info(sbi, "Don't allow the same extension %s appear in both compress and nocompress extension", ++ ext[index]); ++ return -EINVAL; ++ } ++ } ++ } ++ return 0; ++} ++ + #ifdef CONFIG_F2FS_FS_LZ4 + static int f2fs_set_lz4hc_level(struct f2fs_sb_info *sbi, const char *str) + { +@@ -580,7 +619,8 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + substring_t args[MAX_OPT_ARGS]; + #ifdef CONFIG_F2FS_FS_COMPRESSION + unsigned char (*ext)[F2FS_EXTENSION_LEN]; +- int ext_cnt; ++ unsigned char (*noext)[F2FS_EXTENSION_LEN]; ++ int ext_cnt, noext_cnt; + #endif + char *p, *name; + int arg = 0; +@@ -1076,6 +1116,30 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + F2FS_OPTION(sbi).compress_ext_cnt++; + kfree(name); + break; ++ case Opt_nocompress_extension: ++ if (!f2fs_sb_has_compression(sbi)) { ++ f2fs_info(sbi, "Image doesn't support compression"); ++ break; ++ } ++ name = match_strdup(&args[0]); ++ if (!name) ++ return -ENOMEM; ++ ++ noext = F2FS_OPTION(sbi).noextensions; ++ noext_cnt = F2FS_OPTION(sbi).nocompress_ext_cnt; ++ ++ if (strlen(name) >= F2FS_EXTENSION_LEN || ++ noext_cnt >= COMPRESS_EXT_NUM) { ++ f2fs_err(sbi, ++ "invalid extension length/number"); ++ kfree(name); ++ return -EINVAL; ++ } ++ ++ strcpy(noext[noext_cnt], name); ++ F2FS_OPTION(sbi).nocompress_ext_cnt++; ++ kfree(name); ++ break; + case Opt_compress_chksum: + F2FS_OPTION(sbi).compress_chksum = true; + break; +@@ -1097,6 +1161,7 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + case Opt_compress_algorithm: + case Opt_compress_log_size: + case Opt_compress_extension: ++ case Opt_nocompress_extension: + case Opt_compress_chksum: + case Opt_compress_mode: + f2fs_info(sbi, "compression options not supported"); +@@ -1143,6 +1208,13 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + } + #endif + ++#ifdef CONFIG_F2FS_FS_COMPRESSION ++ if (f2fs_test_compress_extension(sbi)) { ++ f2fs_err(sbi, "invalid compress or nocompress extension"); ++ return -EINVAL; ++ } ++#endif ++ + if (F2FS_IO_SIZE_BITS(sbi) && !f2fs_lfs_mode(sbi)) { + f2fs_err(sbi, "Should set mode=lfs with %uKB-sized IO", + F2FS_IO_SIZE_KB(sbi)); +@@ -1687,6 +1759,11 @@ static inline void f2fs_show_compress_options(struct seq_file *seq, + F2FS_OPTION(sbi).extensions[i]); + } + ++ for (i = 0; i < F2FS_OPTION(sbi).nocompress_ext_cnt; i++) { ++ seq_printf(seq, ",nocompress_extension=%s", ++ F2FS_OPTION(sbi).noextensions[i]); ++ } ++ + if (F2FS_OPTION(sbi).compress_chksum) + seq_puts(seq, ",compress_chksum"); + +-- +2.42.0 + diff --git a/queue-5.10/f2fs-compress-deny-setting-unsupported-compress-algo.patch b/queue-5.10/f2fs-compress-deny-setting-unsupported-compress-algo.patch new file mode 100644 index 00000000000..024c5286a32 --- /dev/null +++ b/queue-5.10/f2fs-compress-deny-setting-unsupported-compress-algo.patch @@ -0,0 +1,61 @@ +From 3686432492655f3f63be1a9f4ace7100a2b01264 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Jan 2021 17:40:13 +0800 +Subject: f2fs: compress: deny setting unsupported compress algorithm + +From: Chao Yu + +[ Upstream commit 32be0e97c71366a19d11d1965e3f0957ea0be609 ] + +If kernel doesn't support certain kinds of compress algorithm, deny to set +them as compress algorithm of f2fs via 'compress_algorithm=%s' mount option. + +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Stable-dep-of: 7e1b150fece0 ("f2fs: compress: fix to avoid redundant compress extension") +Signed-off-by: Sasha Levin +--- + fs/f2fs/super.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c +index 1281b59da6a2a..e66c2de29eebc 100644 +--- a/fs/f2fs/super.c ++++ b/fs/f2fs/super.c +@@ -922,17 +922,33 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + if (!name) + return -ENOMEM; + if (!strcmp(name, "lzo")) { ++#ifdef CONFIG_F2FS_FS_LZO + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_LZO; ++#else ++ f2fs_info(sbi, "kernel doesn't support lzo compression"); ++#endif + } else if (!strcmp(name, "lz4")) { ++#ifdef CONFIG_F2FS_FS_LZ4 + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_LZ4; ++#else ++ f2fs_info(sbi, "kernel doesn't support lz4 compression"); ++#endif + } else if (!strcmp(name, "zstd")) { ++#ifdef CONFIG_F2FS_FS_ZSTD + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_ZSTD; ++#else ++ f2fs_info(sbi, "kernel doesn't support zstd compression"); ++#endif + } else if (!strcmp(name, "lzo-rle")) { ++#ifdef CONFIG_F2FS_FS_LZORLE + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_LZORLE; ++#else ++ f2fs_info(sbi, "kernel doesn't support lzorle compression"); ++#endif + } else { + kfree(name); + return -EINVAL; +-- +2.42.0 + diff --git a/queue-5.10/f2fs-compress-fix-to-avoid-redundant-compress-extens.patch b/queue-5.10/f2fs-compress-fix-to-avoid-redundant-compress-extens.patch new file mode 100644 index 00000000000..436933807f6 --- /dev/null +++ b/queue-5.10/f2fs-compress-fix-to-avoid-redundant-compress-extens.patch @@ -0,0 +1,89 @@ +From 5c3751456274b97529ba7ac9604c690797d021ae Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 28 Aug 2023 22:04:17 +0800 +Subject: f2fs: compress: fix to avoid redundant compress extension + +From: Chao Yu + +[ Upstream commit 7e1b150fece033703a824df1bbc03df091ea53cc ] + +With below script, redundant compress extension will be parsed and added +by parse_options(), because parse_options() doesn't check whether the +extension is existed or not, fix it. + +1. mount -t f2fs -o compress_extension=so /dev/vdb /mnt/f2fs +2. mount -t f2fs -o remount,compress_extension=so /mnt/f2fs +3. mount|grep f2fs + +/dev/vdb on /mnt/f2fs type f2fs (...,compress_extension=so,compress_extension=so,...) + +Fixes: 4c8ff7095bef ("f2fs: support data compression") +Fixes: 151b1982be5d ("f2fs: compress: add nocompress extensions support") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/super.c | 33 +++++++++++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c +index daae61df66ffa..e40bc0aeb7fb5 100644 +--- a/fs/f2fs/super.c ++++ b/fs/f2fs/super.c +@@ -509,6 +509,29 @@ static int f2fs_set_test_dummy_encryption(struct super_block *sb, + } + + #ifdef CONFIG_F2FS_FS_COMPRESSION ++static bool is_compress_extension_exist(struct f2fs_sb_info *sbi, ++ const char *new_ext, bool is_ext) ++{ ++ unsigned char (*ext)[F2FS_EXTENSION_LEN]; ++ int ext_cnt; ++ int i; ++ ++ if (is_ext) { ++ ext = F2FS_OPTION(sbi).extensions; ++ ext_cnt = F2FS_OPTION(sbi).compress_ext_cnt; ++ } else { ++ ext = F2FS_OPTION(sbi).noextensions; ++ ext_cnt = F2FS_OPTION(sbi).nocompress_ext_cnt; ++ } ++ ++ for (i = 0; i < ext_cnt; i++) { ++ if (!strcasecmp(new_ext, ext[i])) ++ return true; ++ } ++ ++ return false; ++} ++ + /* + * 1. The same extension name cannot not appear in both compress and non-compress extension + * at the same time. +@@ -1112,6 +1135,11 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + return -EINVAL; + } + ++ if (is_compress_extension_exist(sbi, name, true)) { ++ kfree(name); ++ break; ++ } ++ + strcpy(ext[ext_cnt], name); + F2FS_OPTION(sbi).compress_ext_cnt++; + kfree(name); +@@ -1136,6 +1164,11 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + return -EINVAL; + } + ++ if (is_compress_extension_exist(sbi, name, false)) { ++ kfree(name); ++ break; ++ } ++ + strcpy(noext[noext_cnt], name); + F2FS_OPTION(sbi).nocompress_ext_cnt++; + kfree(name); +-- +2.42.0 + diff --git a/queue-5.10/f2fs-compress-support-chksum.patch b/queue-5.10/f2fs-compress-support-chksum.patch new file mode 100644 index 00000000000..c66e62fa62e --- /dev/null +++ b/queue-5.10/f2fs-compress-support-chksum.patch @@ -0,0 +1,228 @@ +From 0e566ca04faea90c08bd9b41a63f414ce7b65480 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 26 Nov 2020 18:32:09 +0800 +Subject: f2fs: compress: support chksum + +From: Chao Yu + +[ Upstream commit b28f047b28c51d0b9864c34b097bb0b221ea7247 ] + +This patch supports to store chksum value with compressed +data, and verify the integrality of compressed data while +reading the data. + +The feature can be enabled through specifying mount option +'compress_chksum'. + +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Stable-dep-of: 7e1b150fece0 ("f2fs: compress: fix to avoid redundant compress extension") +Signed-off-by: Sasha Levin +--- + Documentation/filesystems/f2fs.rst | 1 + + fs/f2fs/compress.c | 23 +++++++++++++++++++++++ + fs/f2fs/f2fs.h | 16 ++++++++++++++-- + fs/f2fs/inode.c | 3 +++ + fs/f2fs/super.c | 9 +++++++++ + include/linux/f2fs_fs.h | 2 +- + 6 files changed, 51 insertions(+), 3 deletions(-) + +diff --git a/Documentation/filesystems/f2fs.rst b/Documentation/filesystems/f2fs.rst +index 8c0fbdd8ce6fb..3d21a9e86995f 100644 +--- a/Documentation/filesystems/f2fs.rst ++++ b/Documentation/filesystems/f2fs.rst +@@ -260,6 +260,7 @@ compress_extension=%s Support adding specified extension, so that f2fs can enab + For other files, we can still enable compression via ioctl. + Note that, there is one reserved special extension '*', it + can be set to enable compression for all files. ++compress_chksum Support verifying chksum of raw data in compressed cluster. + inlinecrypt When possible, encrypt/decrypt the contents of encrypted + files using the blk-crypto framework rather than + filesystem-layer encryption. This allows the use of +diff --git a/fs/f2fs/compress.c b/fs/f2fs/compress.c +index 1be9de40f0b5a..db8360ae96caf 100644 +--- a/fs/f2fs/compress.c ++++ b/fs/f2fs/compress.c +@@ -589,6 +589,7 @@ static int f2fs_compress_pages(struct compress_ctx *cc) + f2fs_cops[fi->i_compress_algorithm]; + unsigned int max_len, new_nr_cpages; + struct page **new_cpages; ++ u32 chksum = 0; + int i, ret; + + trace_f2fs_compress_pages_start(cc->inode, cc->cluster_idx, +@@ -642,6 +643,11 @@ static int f2fs_compress_pages(struct compress_ctx *cc) + + cc->cbuf->clen = cpu_to_le32(cc->clen); + ++ if (fi->i_compress_flag & 1 << COMPRESS_CHKSUM) ++ chksum = f2fs_crc32(F2FS_I_SB(cc->inode), ++ cc->cbuf->cdata, cc->clen); ++ cc->cbuf->chksum = cpu_to_le32(chksum); ++ + for (i = 0; i < COMPRESS_DATA_RESERVED_SIZE; i++) + cc->cbuf->reserved[i] = cpu_to_le32(0); + +@@ -777,6 +783,23 @@ void f2fs_decompress_pages(struct bio *bio, struct page *page, bool verity) + + ret = cops->decompress_pages(dic); + ++ if (!ret && fi->i_compress_flag & 1 << COMPRESS_CHKSUM) { ++ u32 provided = le32_to_cpu(dic->cbuf->chksum); ++ u32 calculated = f2fs_crc32(sbi, dic->cbuf->cdata, dic->clen); ++ ++ if (provided != calculated) { ++ if (!is_inode_flag_set(dic->inode, FI_COMPRESS_CORRUPT)) { ++ set_inode_flag(dic->inode, FI_COMPRESS_CORRUPT); ++ printk_ratelimited( ++ "%sF2FS-fs (%s): checksum invalid, nid = %lu, %x vs %x", ++ KERN_INFO, sbi->sb->s_id, dic->inode->i_ino, ++ provided, calculated); ++ } ++ set_sbi_flag(sbi, SBI_NEED_FSCK); ++ WARN_ON_ONCE(1); ++ } ++ } ++ + out_vunmap_cbuf: + vm_unmap_ram(dic->cbuf, dic->nr_cpages); + out_vunmap_rbuf: +diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h +index 83ebc860508b0..6dfefbf54917d 100644 +--- a/fs/f2fs/f2fs.h ++++ b/fs/f2fs/f2fs.h +@@ -147,7 +147,8 @@ struct f2fs_mount_info { + + /* For compression */ + unsigned char compress_algorithm; /* algorithm type */ +- unsigned compress_log_size; /* cluster log size */ ++ unsigned char compress_log_size; /* cluster log size */ ++ bool compress_chksum; /* compressed data chksum */ + unsigned char compress_ext_cnt; /* extension count */ + unsigned char extensions[COMPRESS_EXT_NUM][F2FS_EXTENSION_LEN]; /* extensions */ + }; +@@ -678,6 +679,7 @@ enum { + FI_ATOMIC_REVOKE_REQUEST, /* request to drop atomic data */ + FI_VERITY_IN_PROGRESS, /* building fs-verity Merkle tree */ + FI_COMPRESSED_FILE, /* indicate file's data can be compressed */ ++ FI_COMPRESS_CORRUPT, /* indicate compressed cluster is corrupted */ + FI_MMAP_FILE, /* indicate file was mmapped */ + FI_MAX, /* max flag, never be used */ + }; +@@ -736,6 +738,7 @@ struct f2fs_inode_info { + atomic_t i_compr_blocks; /* # of compressed blocks */ + unsigned char i_compress_algorithm; /* algorithm type */ + unsigned char i_log_cluster_size; /* log of cluster size */ ++ unsigned short i_compress_flag; /* compress flag */ + unsigned int i_cluster_size; /* cluster size */ + }; + +@@ -1281,9 +1284,15 @@ enum compress_algorithm_type { + COMPRESS_MAX, + }; + +-#define COMPRESS_DATA_RESERVED_SIZE 5 ++enum compress_flag { ++ COMPRESS_CHKSUM, ++ COMPRESS_MAX_FLAG, ++}; ++ ++#define COMPRESS_DATA_RESERVED_SIZE 4 + struct compress_data { + __le32 clen; /* compressed data size */ ++ __le32 chksum; /* compressed data chksum */ + __le32 reserved[COMPRESS_DATA_RESERVED_SIZE]; /* reserved */ + u8 cdata[]; /* compressed data */ + }; +@@ -3925,6 +3934,9 @@ static inline void set_compress_context(struct inode *inode) + F2FS_OPTION(sbi).compress_algorithm; + F2FS_I(inode)->i_log_cluster_size = + F2FS_OPTION(sbi).compress_log_size; ++ F2FS_I(inode)->i_compress_flag = ++ F2FS_OPTION(sbi).compress_chksum ? ++ 1 << COMPRESS_CHKSUM : 0; + F2FS_I(inode)->i_cluster_size = + 1 << F2FS_I(inode)->i_log_cluster_size; + F2FS_I(inode)->i_flags |= F2FS_COMPR_FL; +diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c +index 87752550f78c8..3e98551f4186d 100644 +--- a/fs/f2fs/inode.c ++++ b/fs/f2fs/inode.c +@@ -455,6 +455,7 @@ static int do_read_inode(struct inode *inode) + le64_to_cpu(ri->i_compr_blocks)); + fi->i_compress_algorithm = ri->i_compress_algorithm; + fi->i_log_cluster_size = ri->i_log_cluster_size; ++ fi->i_compress_flag = le16_to_cpu(ri->i_compress_flag); + fi->i_cluster_size = 1 << fi->i_log_cluster_size; + set_inode_flag(inode, FI_COMPRESSED_FILE); + } +@@ -633,6 +634,8 @@ void f2fs_update_inode(struct inode *inode, struct page *node_page) + &F2FS_I(inode)->i_compr_blocks)); + ri->i_compress_algorithm = + F2FS_I(inode)->i_compress_algorithm; ++ ri->i_compress_flag = ++ cpu_to_le16(F2FS_I(inode)->i_compress_flag); + ri->i_log_cluster_size = + F2FS_I(inode)->i_log_cluster_size; + } +diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c +index 9a74d60f61dba..065aa01958e95 100644 +--- a/fs/f2fs/super.c ++++ b/fs/f2fs/super.c +@@ -146,6 +146,7 @@ enum { + Opt_compress_algorithm, + Opt_compress_log_size, + Opt_compress_extension, ++ Opt_compress_chksum, + Opt_atgc, + Opt_err, + }; +@@ -214,6 +215,7 @@ static match_table_t f2fs_tokens = { + {Opt_compress_algorithm, "compress_algorithm=%s"}, + {Opt_compress_log_size, "compress_log_size=%u"}, + {Opt_compress_extension, "compress_extension=%s"}, ++ {Opt_compress_chksum, "compress_chksum"}, + {Opt_atgc, "atgc"}, + {Opt_err, NULL}, + }; +@@ -974,10 +976,14 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + F2FS_OPTION(sbi).compress_ext_cnt++; + kfree(name); + break; ++ case Opt_compress_chksum: ++ F2FS_OPTION(sbi).compress_chksum = true; ++ break; + #else + case Opt_compress_algorithm: + case Opt_compress_log_size: + case Opt_compress_extension: ++ case Opt_compress_chksum: + f2fs_info(sbi, "compression options not supported"); + break; + #endif +@@ -1562,6 +1568,9 @@ static inline void f2fs_show_compress_options(struct seq_file *seq, + seq_printf(seq, ",compress_extension=%s", + F2FS_OPTION(sbi).extensions[i]); + } ++ ++ if (F2FS_OPTION(sbi).compress_chksum) ++ seq_puts(seq, ",compress_chksum"); + } + + static int f2fs_show_options(struct seq_file *seq, struct dentry *root) +diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h +index a5dbb57a687fb..7dc2a06cf19a1 100644 +--- a/include/linux/f2fs_fs.h ++++ b/include/linux/f2fs_fs.h +@@ -273,7 +273,7 @@ struct f2fs_inode { + __le64 i_compr_blocks; /* # of compressed blocks */ + __u8 i_compress_algorithm; /* compress algorithm */ + __u8 i_log_cluster_size; /* log of cluster size */ +- __le16 i_padding; /* padding */ ++ __le16 i_compress_flag; /* compress flag */ + __le32 i_extra_end[0]; /* for attribute size calculation */ + } __packed; + __le32 i_addr[DEF_ADDRS_PER_INODE]; /* Pointers to data blocks */ +-- +2.42.0 + diff --git a/queue-5.10/f2fs-compress-support-compress-level.patch b/queue-5.10/f2fs-compress-support-compress-level.patch new file mode 100644 index 00000000000..a9e871a8c46 --- /dev/null +++ b/queue-5.10/f2fs-compress-support-compress-level.patch @@ -0,0 +1,350 @@ +From c8c1c276f06b50c27eab63cd2b78ce81236b8d1e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Jan 2021 17:46:43 +0800 +Subject: f2fs: compress: support compress level + +From: Chao Yu + +[ Upstream commit 3fde13f817e23f05ce407d136325df4cbc913e67 ] + +Expand 'compress_algorithm' mount option to accept parameter as format of +:, by this way, it gives a way to allow user to do more +specified config on lz4 and zstd compression level, then f2fs compression +can provide higher compress ratio. + +In order to set compress level for lz4 algorithm, it needs to set +CONFIG_LZ4HC_COMPRESS and CONFIG_F2FS_FS_LZ4HC config to enable lz4hc +compress algorithm. + +CR and performance number on lz4/lz4hc algorithm: + +dd if=enwik9 of=compressed_file conv=fsync + +Original blocks: 244382 + + lz4 lz4hc-9 +compressed blocks 170647 163270 +compress ratio 69.8% 66.8% +speed 16.4207 s, 60.9 MB/s 26.7299 s, 37.4 MB/s + +compress ratio = after / before + +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Stable-dep-of: 7e1b150fece0 ("f2fs: compress: fix to avoid redundant compress extension") +Signed-off-by: Sasha Levin +--- + Documentation/filesystems/f2fs.rst | 5 ++ + fs/f2fs/Kconfig | 10 ++++ + fs/f2fs/compress.c | 41 +++++++++++++- + fs/f2fs/f2fs.h | 9 +++ + fs/f2fs/super.c | 89 +++++++++++++++++++++++++++++- + include/linux/f2fs_fs.h | 3 + + 6 files changed, 152 insertions(+), 5 deletions(-) + +diff --git a/Documentation/filesystems/f2fs.rst b/Documentation/filesystems/f2fs.rst +index de2bacc418fee..4f51c0be22c45 100644 +--- a/Documentation/filesystems/f2fs.rst ++++ b/Documentation/filesystems/f2fs.rst +@@ -249,6 +249,11 @@ checkpoint=%s[:%u[%]] Set to "disable" to turn off checkpointing. Set to "enabl + This space is reclaimed once checkpoint=enable. + compress_algorithm=%s Control compress algorithm, currently f2fs supports "lzo", + "lz4", "zstd" and "lzo-rle" algorithm. ++compress_algorithm=%s:%d Control compress algorithm and its compress level, now, only ++ "lz4" and "zstd" support compress level config. ++ algorithm level range ++ lz4 3 - 16 ++ zstd 1 - 22 + compress_log_size=%u Support configuring compress cluster size, the size will + be 4KB * (1 << %u), 16KB is minimum size, also it's + default size. +diff --git a/fs/f2fs/Kconfig b/fs/f2fs/Kconfig +index d13c5c6a97876..63c1fc1a0e3b2 100644 +--- a/fs/f2fs/Kconfig ++++ b/fs/f2fs/Kconfig +@@ -119,6 +119,16 @@ config F2FS_FS_LZ4 + help + Support LZ4 compress algorithm, if unsure, say Y. + ++config F2FS_FS_LZ4HC ++ bool "LZ4HC compression support" ++ depends on F2FS_FS_COMPRESSION ++ depends on F2FS_FS_LZ4 ++ select LZ4HC_COMPRESS ++ default y ++ help ++ Support LZ4HC compress algorithm, LZ4HC has compatible on-disk ++ layout with LZ4, if unsure, say Y. ++ + config F2FS_FS_ZSTD + bool "ZSTD compression support" + depends on F2FS_FS_COMPRESSION +diff --git a/fs/f2fs/compress.c b/fs/f2fs/compress.c +index 8da6df3bfb03f..579d3b32db178 100644 +--- a/fs/f2fs/compress.c ++++ b/fs/f2fs/compress.c +@@ -240,8 +240,14 @@ static const struct f2fs_compress_ops f2fs_lzo_ops = { + #ifdef CONFIG_F2FS_FS_LZ4 + static int lz4_init_compress_ctx(struct compress_ctx *cc) + { +- cc->private = f2fs_kvmalloc(F2FS_I_SB(cc->inode), +- LZ4_MEM_COMPRESS, GFP_NOFS); ++ unsigned int size = LZ4_MEM_COMPRESS; ++ ++#ifdef CONFIG_F2FS_FS_LZ4HC ++ if (F2FS_I(cc->inode)->i_compress_flag >> COMPRESS_LEVEL_OFFSET) ++ size = LZ4HC_MEM_COMPRESS; ++#endif ++ ++ cc->private = f2fs_kvmalloc(F2FS_I_SB(cc->inode), size, GFP_NOFS); + if (!cc->private) + return -ENOMEM; + +@@ -260,10 +266,34 @@ static void lz4_destroy_compress_ctx(struct compress_ctx *cc) + cc->private = NULL; + } + ++#ifdef CONFIG_F2FS_FS_LZ4HC ++static int lz4hc_compress_pages(struct compress_ctx *cc) ++{ ++ unsigned char level = F2FS_I(cc->inode)->i_compress_flag >> ++ COMPRESS_LEVEL_OFFSET; ++ int len; ++ ++ if (level) ++ len = LZ4_compress_HC(cc->rbuf, cc->cbuf->cdata, cc->rlen, ++ cc->clen, level, cc->private); ++ else ++ len = LZ4_compress_default(cc->rbuf, cc->cbuf->cdata, cc->rlen, ++ cc->clen, cc->private); ++ if (!len) ++ return -EAGAIN; ++ ++ cc->clen = len; ++ return 0; ++} ++#endif ++ + static int lz4_compress_pages(struct compress_ctx *cc) + { + int len; + ++#ifdef CONFIG_F2FS_FS_LZ4HC ++ return lz4hc_compress_pages(cc); ++#endif + len = LZ4_compress_default(cc->rbuf, cc->cbuf->cdata, cc->rlen, + cc->clen, cc->private); + if (!len) +@@ -312,8 +342,13 @@ static int zstd_init_compress_ctx(struct compress_ctx *cc) + ZSTD_CStream *stream; + void *workspace; + unsigned int workspace_size; ++ unsigned char level = F2FS_I(cc->inode)->i_compress_flag >> ++ COMPRESS_LEVEL_OFFSET; ++ ++ if (!level) ++ level = F2FS_ZSTD_DEFAULT_CLEVEL; + +- params = ZSTD_getParams(F2FS_ZSTD_DEFAULT_CLEVEL, cc->rlen, 0); ++ params = ZSTD_getParams(level, cc->rlen, 0); + workspace_size = ZSTD_CStreamWorkspaceBound(params.cParams); + + workspace = f2fs_kvmalloc(F2FS_I_SB(cc->inode), +diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h +index 6a9f4dcea06d6..01e365aefbc97 100644 +--- a/fs/f2fs/f2fs.h ++++ b/fs/f2fs/f2fs.h +@@ -148,6 +148,7 @@ struct f2fs_mount_info { + /* For compression */ + unsigned char compress_algorithm; /* algorithm type */ + unsigned char compress_log_size; /* cluster log size */ ++ unsigned char compress_level; /* compress level */ + bool compress_chksum; /* compressed data chksum */ + unsigned char compress_ext_cnt; /* extension count */ + int compress_mode; /* compression mode */ +@@ -740,6 +741,7 @@ struct f2fs_inode_info { + atomic_t i_compr_blocks; /* # of compressed blocks */ + unsigned char i_compress_algorithm; /* algorithm type */ + unsigned char i_log_cluster_size; /* log of cluster size */ ++ unsigned char i_compress_level; /* compress level (lz4hc,zstd) */ + unsigned short i_compress_flag; /* compress flag */ + unsigned int i_cluster_size; /* cluster size */ + }; +@@ -1315,6 +1317,8 @@ struct compress_data { + + #define F2FS_COMPRESSED_PAGE_MAGIC 0xF5F2C000 + ++#define COMPRESS_LEVEL_OFFSET 8 ++ + /* compress context */ + struct compress_ctx { + struct inode *inode; /* inode the context belong to */ +@@ -3969,6 +3973,11 @@ static inline void set_compress_context(struct inode *inode) + 1 << COMPRESS_CHKSUM : 0; + F2FS_I(inode)->i_cluster_size = + 1 << F2FS_I(inode)->i_log_cluster_size; ++ if (F2FS_I(inode)->i_compress_algorithm == COMPRESS_LZ4 && ++ F2FS_OPTION(sbi).compress_level) ++ F2FS_I(inode)->i_compress_flag |= ++ F2FS_OPTION(sbi).compress_level << ++ COMPRESS_LEVEL_OFFSET; + F2FS_I(inode)->i_flags |= F2FS_COMPR_FL; + set_inode_flag(inode, FI_COMPRESSED_FILE); + stat_inc_compr_inode(inode); +diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c +index e66c2de29eebc..d49160328d53b 100644 +--- a/fs/f2fs/super.c ++++ b/fs/f2fs/super.c +@@ -25,6 +25,8 @@ + #include + #include + #include ++#include ++#include + + #include "f2fs.h" + #include "node.h" +@@ -504,6 +506,74 @@ static int f2fs_set_test_dummy_encryption(struct super_block *sb, + return 0; + } + ++#ifdef CONFIG_F2FS_FS_COMPRESSION ++#ifdef CONFIG_F2FS_FS_LZ4 ++static int f2fs_set_lz4hc_level(struct f2fs_sb_info *sbi, const char *str) ++{ ++#ifdef CONFIG_F2FS_FS_LZ4HC ++ unsigned int level; ++#endif ++ ++ if (strlen(str) == 3) { ++ F2FS_OPTION(sbi).compress_level = 0; ++ return 0; ++ } ++ ++#ifdef CONFIG_F2FS_FS_LZ4HC ++ str += 3; ++ ++ if (str[0] != ':') { ++ f2fs_info(sbi, "wrong format, e.g. :"); ++ return -EINVAL; ++ } ++ if (kstrtouint(str + 1, 10, &level)) ++ return -EINVAL; ++ ++ if (level < LZ4HC_MIN_CLEVEL || level > LZ4HC_MAX_CLEVEL) { ++ f2fs_info(sbi, "invalid lz4hc compress level: %d", level); ++ return -EINVAL; ++ } ++ ++ F2FS_OPTION(sbi).compress_level = level; ++ return 0; ++#else ++ f2fs_info(sbi, "kernel doesn't support lz4hc compression"); ++ return -EINVAL; ++#endif ++} ++#endif ++ ++#ifdef CONFIG_F2FS_FS_ZSTD ++static int f2fs_set_zstd_level(struct f2fs_sb_info *sbi, const char *str) ++{ ++ unsigned int level; ++ int len = 4; ++ ++ if (strlen(str) == len) { ++ F2FS_OPTION(sbi).compress_level = 0; ++ return 0; ++ } ++ ++ str += len; ++ ++ if (str[0] != ':') { ++ f2fs_info(sbi, "wrong format, e.g. :"); ++ return -EINVAL; ++ } ++ if (kstrtouint(str + 1, 10, &level)) ++ return -EINVAL; ++ ++ if (!level || level > ZSTD_maxCLevel()) { ++ f2fs_info(sbi, "invalid zstd compress level: %d", level); ++ return -EINVAL; ++ } ++ ++ F2FS_OPTION(sbi).compress_level = level; ++ return 0; ++} ++#endif ++#endif ++ + static int parse_options(struct super_block *sb, char *options, bool is_remount) + { + struct f2fs_sb_info *sbi = F2FS_SB(sb); +@@ -923,20 +993,31 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + return -ENOMEM; + if (!strcmp(name, "lzo")) { + #ifdef CONFIG_F2FS_FS_LZO ++ F2FS_OPTION(sbi).compress_level = 0; + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_LZO; + #else + f2fs_info(sbi, "kernel doesn't support lzo compression"); + #endif +- } else if (!strcmp(name, "lz4")) { ++ } else if (!strncmp(name, "lz4", 3)) { + #ifdef CONFIG_F2FS_FS_LZ4 ++ ret = f2fs_set_lz4hc_level(sbi, name); ++ if (ret) { ++ kfree(name); ++ return -EINVAL; ++ } + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_LZ4; + #else + f2fs_info(sbi, "kernel doesn't support lz4 compression"); + #endif +- } else if (!strcmp(name, "zstd")) { ++ } else if (!strncmp(name, "zstd", 4)) { + #ifdef CONFIG_F2FS_FS_ZSTD ++ ret = f2fs_set_zstd_level(sbi, name); ++ if (ret) { ++ kfree(name); ++ return -EINVAL; ++ } + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_ZSTD; + #else +@@ -944,6 +1025,7 @@ static int parse_options(struct super_block *sb, char *options, bool is_remount) + #endif + } else if (!strcmp(name, "lzo-rle")) { + #ifdef CONFIG_F2FS_FS_LZORLE ++ F2FS_OPTION(sbi).compress_level = 0; + F2FS_OPTION(sbi).compress_algorithm = + COMPRESS_LZORLE; + #else +@@ -1594,6 +1676,9 @@ static inline void f2fs_show_compress_options(struct seq_file *seq, + } + seq_printf(seq, ",compress_algorithm=%s", algtype); + ++ if (F2FS_OPTION(sbi).compress_level) ++ seq_printf(seq, ":%d", F2FS_OPTION(sbi).compress_level); ++ + seq_printf(seq, ",compress_log_size=%u", + F2FS_OPTION(sbi).compress_log_size); + +diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h +index 7dc2a06cf19a1..c6cc0a566ef5c 100644 +--- a/include/linux/f2fs_fs.h ++++ b/include/linux/f2fs_fs.h +@@ -274,6 +274,9 @@ struct f2fs_inode { + __u8 i_compress_algorithm; /* compress algorithm */ + __u8 i_log_cluster_size; /* log of cluster size */ + __le16 i_compress_flag; /* compress flag */ ++ /* 0 bit: chksum flag ++ * [10,15] bits: compress level ++ */ + __le32 i_extra_end[0]; /* for attribute size calculation */ + } __packed; + __le32 i_addr[DEF_ADDRS_PER_INODE]; /* Pointers to data blocks */ +-- +2.42.0 + diff --git a/queue-5.10/f2fs-document-add-description-about-compressed-space.patch b/queue-5.10/f2fs-document-add-description-about-compressed-space.patch new file mode 100644 index 00000000000..442474989ca --- /dev/null +++ b/queue-5.10/f2fs-document-add-description-about-compressed-space.patch @@ -0,0 +1,43 @@ +From 8a86857d41240a18f01b22fa83f2ee6d8bc5777a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Apr 2021 17:56:53 +0800 +Subject: f2fs: document: add description about compressed space handling + +From: Chao Yu + +[ Upstream commit 38740707c5bc1253069eb932bc6d244f80ec21f0 ] + +User or developer may still be confused about why f2fs doesn't expose +compressed space to userspace, add description about compressed space +handling policy into f2fs documentation. + +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Stable-dep-of: 7e1b150fece0 ("f2fs: compress: fix to avoid redundant compress extension") +Signed-off-by: Sasha Levin +--- + Documentation/filesystems/f2fs.rst | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/Documentation/filesystems/f2fs.rst b/Documentation/filesystems/f2fs.rst +index 4f51c0be22c45..9e302d3dd85a6 100644 +--- a/Documentation/filesystems/f2fs.rst ++++ b/Documentation/filesystems/f2fs.rst +@@ -803,6 +803,14 @@ Compression implementation + * chattr +c file + * chattr +c dir; touch dir/file + * mount w/ -o compress_extension=ext; touch file.ext ++ * mount w/ -o compress_extension=*; touch any_file ++ ++- At this point, compression feature doesn't expose compressed space to user ++ directly in order to guarantee potential data updates later to the space. ++ Instead, the main goal is to reduce data writes to flash disk as much as ++ possible, resulting in extending disk life time as well as relaxing IO ++ congestion. Alternatively, we've added ioctl interface to reclaim compressed ++ space and show it to user after putting the immutable bit. + + Compress metadata layout:: + +-- +2.42.0 + diff --git a/queue-5.10/f2fs-fix-to-initialize-map.m_pblk-in-f2fs_precache_e.patch b/queue-5.10/f2fs-fix-to-initialize-map.m_pblk-in-f2fs_precache_e.patch new file mode 100644 index 00000000000..5575ae1c4d1 --- /dev/null +++ b/queue-5.10/f2fs-fix-to-initialize-map.m_pblk-in-f2fs_precache_e.patch @@ -0,0 +1,37 @@ +From 40a851657c22c81f6fbf3a88001b0b4510fad850 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 7 Oct 2023 15:45:52 +0800 +Subject: f2fs: fix to initialize map.m_pblk in f2fs_precache_extents() + +From: Chao Yu + +[ Upstream commit 8b07c1fb0f1ad139373c8253f2fad8bc43fab07d ] + +Otherwise, it may print random physical block address in tracepoint +of f2fs_map_blocks() as below: + +f2fs_map_blocks: dev = (253,16), ino = 2297, file offset = 0, start blkaddr = 0xa356c421, len = 0x0, flags = 0 + +Fixes: c4020b2da4c9 ("f2fs: support F2FS_IOC_PRECACHE_EXTENTS") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/file.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c +index 6e91be5b8c30f..4e6b93f167589 100644 +--- a/fs/f2fs/file.c ++++ b/fs/f2fs/file.c +@@ -3315,6 +3315,7 @@ int f2fs_precache_extents(struct inode *inode) + return -EOPNOTSUPP; + + map.m_lblk = 0; ++ map.m_pblk = 0; + map.m_next_pgofs = NULL; + map.m_next_extent = &m_next_extent; + map.m_seg_type = NO_CHECK_TYPE; +-- +2.42.0 + diff --git a/queue-5.10/firmware-ti_sci-mark-driver-as-non-removable.patch b/queue-5.10/firmware-ti_sci-mark-driver-as-non-removable.patch new file mode 100644 index 00000000000..2f6bb4d473f --- /dev/null +++ b/queue-5.10/firmware-ti_sci-mark-driver-as-non-removable.patch @@ -0,0 +1,113 @@ +From bd2b98feddc8df97125f5e2c95fd189db7a30a82 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Sep 2023 14:40:26 +0530 +Subject: firmware: ti_sci: Mark driver as non removable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Dhruva Gole + +[ Upstream commit 7b7a224b1ba1703583b25a3641ad9798f34d832a ] + +The TI-SCI message protocol provides a way to communicate between +various compute processors with a central system controller entity. It +provides the fundamental device management capability and clock control +in the SOCs that it's used in. + +The remove function failed to do all the necessary cleanup if +there are registered users. Some things are freed however which +likely results in an oops later on. + +Ensure that the driver isn't unbound by suppressing its bind and unbind +sysfs attributes. As the driver is built-in there is no way to remove +device once bound. + +We can also remove the ti_sci_remove call along with the +ti_sci_debugfs_destroy as there are no callers for it any longer. + +Fixes: aa276781a64a ("firmware: Add basic support for TI System Control Interface (TI-SCI) protocol") +Reported-by: Uwe Kleine-König +Closes: https://lore.kernel.org/linux-arm-kernel/20230216083908.mvmydic5lpi3ogo7@pengutronix.de/ +Suggested-by: Uwe Kleine-König +Acked-by: Uwe Kleine-König +Signed-off-by: Dhruva Gole +Link: https://lore.kernel.org/r/20230921091025.133130-1-d-gole@ti.com +Signed-off-by: Nishanth Menon +Signed-off-by: Sasha Levin +--- + drivers/firmware/ti_sci.c | 46 +-------------------------------------- + 1 file changed, 1 insertion(+), 45 deletions(-) + +diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c +index 896f53ec78571..fe6be0771a076 100644 +--- a/drivers/firmware/ti_sci.c ++++ b/drivers/firmware/ti_sci.c +@@ -190,19 +190,6 @@ static int ti_sci_debugfs_create(struct platform_device *pdev, + return 0; + } + +-/** +- * ti_sci_debugfs_destroy() - clean up log debug file +- * @pdev: platform device pointer +- * @info: Pointer to SCI entity information +- */ +-static void ti_sci_debugfs_destroy(struct platform_device *pdev, +- struct ti_sci_info *info) +-{ +- if (IS_ERR(info->debug_region)) +- return; +- +- debugfs_remove(info->d); +-} + #else /* CONFIG_DEBUG_FS */ + static inline int ti_sci_debugfs_create(struct platform_device *dev, + struct ti_sci_info *info) +@@ -3510,43 +3497,12 @@ static int ti_sci_probe(struct platform_device *pdev) + return ret; + } + +-static int ti_sci_remove(struct platform_device *pdev) +-{ +- struct ti_sci_info *info; +- struct device *dev = &pdev->dev; +- int ret = 0; +- +- of_platform_depopulate(dev); +- +- info = platform_get_drvdata(pdev); +- +- if (info->nb.notifier_call) +- unregister_restart_handler(&info->nb); +- +- mutex_lock(&ti_sci_list_mutex); +- if (info->users) +- ret = -EBUSY; +- else +- list_del(&info->node); +- mutex_unlock(&ti_sci_list_mutex); +- +- if (!ret) { +- ti_sci_debugfs_destroy(pdev, info); +- +- /* Safe to free channels since no more users */ +- mbox_free_channel(info->chan_tx); +- mbox_free_channel(info->chan_rx); +- } +- +- return ret; +-} +- + static struct platform_driver ti_sci_driver = { + .probe = ti_sci_probe, +- .remove = ti_sci_remove, + .driver = { + .name = "ti-sci", + .of_match_table = of_match_ptr(ti_sci_of_match), ++ .suppress_bind_attrs = true, + }, + }; + module_platform_driver(ti_sci_driver); +-- +2.42.0 + diff --git a/queue-5.10/futex-don-t-include-process-mm-in-futex-key-on-no-mm.patch b/queue-5.10/futex-don-t-include-process-mm-in-futex-key-on-no-mm.patch new file mode 100644 index 00000000000..8d9e2efce2c --- /dev/null +++ b/queue-5.10/futex-don-t-include-process-mm-in-futex-key-on-no-mm.patch @@ -0,0 +1,62 @@ +From 8c0ce4be92fd570c8babd8f3dffb5278eeee0efa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 19 Oct 2023 16:45:49 -0400 +Subject: futex: Don't include process MM in futex key on no-MMU +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ben Wolsieffer + +[ Upstream commit c73801ae4f22b390228ebf471d55668e824198b6 ] + +On no-MMU, all futexes are treated as private because there is no need +to map a virtual address to physical to match the futex across +processes. This doesn't quite work though, because private futexes +include the current process's mm_struct as part of their key. This makes +it impossible for one process to wake up a shared futex being waited on +in another process. + +Fix this bug by excluding the mm_struct from the key. With +a single address space, the futex address is already a unique key. + +Fixes: 784bdf3bb694 ("futex: Assume all mappings are private on !MMU systems") +Signed-off-by: Ben Wolsieffer +Signed-off-by: Ingo Molnar +Acked-by: Peter Zijlstra +Cc: Thomas Gleixner +Cc: Darren Hart +Cc: Davidlohr Bueso +Cc: André Almeida +Link: https://lore.kernel.org/r/20231019204548.1236437-2-ben.wolsieffer@hefring.com +Signed-off-by: Sasha Levin +--- + kernel/futex/core.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/kernel/futex/core.c b/kernel/futex/core.c +index 8dd0bc50ac36d..cde0ca876b935 100644 +--- a/kernel/futex/core.c ++++ b/kernel/futex/core.c +@@ -514,7 +514,17 @@ static int get_futex_key(u32 __user *uaddr, bool fshared, union futex_key *key, + * but access_ok() should be faster than find_vma() + */ + if (!fshared) { +- key->private.mm = mm; ++ /* ++ * On no-MMU, shared futexes are treated as private, therefore ++ * we must not include the current process in the key. Since ++ * there is only one address space, the address is a unique key ++ * on its own. ++ */ ++ if (IS_ENABLED(CONFIG_MMU)) ++ key->private.mm = mm; ++ else ++ key->private.mm = NULL; ++ + key->private.address = address; + return 0; + } +-- +2.42.0 + diff --git a/queue-5.10/genirq-matrix-exclude-managed-interrupts-in-irq_matr.patch b/queue-5.10/genirq-matrix-exclude-managed-interrupts-in-irq_matr.patch new file mode 100644 index 00000000000..f273d989c52 --- /dev/null +++ b/queue-5.10/genirq-matrix-exclude-managed-interrupts-in-irq_matr.patch @@ -0,0 +1,73 @@ +From c63568c760e8c157dd3b3f215756e4a523e6411b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 Oct 2023 15:25:22 +0800 +Subject: genirq/matrix: Exclude managed interrupts in irq_matrix_allocated() + +From: Chen Yu + +[ Upstream commit a0b0bad10587ae2948a7c36ca4ffc206007fbcf3 ] + +When a CPU is about to be offlined, x86 validates that all active +interrupts which are targeted to this CPU can be migrated to the remaining +online CPUs. If not, the offline operation is aborted. + +The validation uses irq_matrix_allocated() to retrieve the number of +vectors which are allocated on the outgoing CPU. The returned number of +allocated vectors includes also vectors which are associated to managed +interrupts. + +That's overaccounting because managed interrupts are: + + - not migrated when the affinity mask of the interrupt targets only + the outgoing CPU + + - migrated to another CPU, but in that case the vector is already + pre-allocated on the potential target CPUs and must not be taken into + account. + +As a consequence the check whether the remaining online CPUs have enough +capacity for migrating the allocated vectors from the outgoing CPU might +fail incorrectly. + +Let irq_matrix_allocated() return only the number of allocated non-managed +interrupts to make this validation check correct. + +[ tglx: Amend changelog and fixup kernel-doc comment ] + +Fixes: 2f75d9e1c905 ("genirq: Implement bitmap matrix allocator") +Reported-by: Wendy Wang +Signed-off-by: Chen Yu +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/r/20231020072522.557846-1-yu.c.chen@intel.com +Signed-off-by: Sasha Levin +--- + kernel/irq/matrix.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/kernel/irq/matrix.c b/kernel/irq/matrix.c +index 8e586858bcf41..d25edbb87119f 100644 +--- a/kernel/irq/matrix.c ++++ b/kernel/irq/matrix.c +@@ -466,16 +466,16 @@ unsigned int irq_matrix_reserved(struct irq_matrix *m) + } + + /** +- * irq_matrix_allocated - Get the number of allocated irqs on the local cpu ++ * irq_matrix_allocated - Get the number of allocated non-managed irqs on the local CPU + * @m: Pointer to the matrix to search + * +- * This returns number of allocated irqs ++ * This returns number of allocated non-managed interrupts. + */ + unsigned int irq_matrix_allocated(struct irq_matrix *m) + { + struct cpumap *cm = this_cpu_ptr(m->maps); + +- return cm->allocated; ++ return cm->allocated - cm->managed_allocated; + } + + #ifdef CONFIG_GENERIC_IRQ_DEBUGFS +-- +2.42.0 + diff --git a/queue-5.10/gpio-add-helpers-to-ease-the-transition-towards-immu.patch b/queue-5.10/gpio-add-helpers-to-ease-the-transition-towards-immu.patch new file mode 100644 index 00000000000..eb55cd859e3 --- /dev/null +++ b/queue-5.10/gpio-add-helpers-to-ease-the-transition-towards-immu.patch @@ -0,0 +1,54 @@ +From df4b1e899b420b2ee4661e9a42e9455f46c39c4e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Apr 2022 15:18:39 +0100 +Subject: gpio: Add helpers to ease the transition towards immutable irq_chip + +From: Marc Zyngier + +[ Upstream commit 36b78aae4bfee749bbde73be570796bfd0f56bec ] + +Add a couple of new helpers to make it slightly simpler to convert +drivers to immutable irq_chip structures: + +- GPIOCHIP_IRQ_RESOURCE_HELPERS populates the irq_chip structure + with the resource management callbacks + +- gpio_irq_chip_set_chip() populates the gpio_irq_chip.chip + structure, avoiding the proliferation of ugly casts + +Reviewed-by: Andy Shevchenko +Reviewed-by: Bartosz Golaszewski +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220419141846.598305-4-maz@kernel.org +Stable-dep-of: dc3115e6c5d9 ("hid: cp2112: Fix IRQ shutdown stopping polling for all IRQs on chip") +Signed-off-by: Sasha Levin +--- + include/linux/gpio/driver.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h +index 38df53b541d53..897fc150552a2 100644 +--- a/include/linux/gpio/driver.h ++++ b/include/linux/gpio/driver.h +@@ -595,6 +595,18 @@ void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); + int gpiochip_irq_reqres(struct irq_data *data); + void gpiochip_irq_relres(struct irq_data *data); + ++/* Paste this in your irq_chip structure */ ++#define GPIOCHIP_IRQ_RESOURCE_HELPERS \ ++ .irq_request_resources = gpiochip_irq_reqres, \ ++ .irq_release_resources = gpiochip_irq_relres ++ ++static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq, ++ const struct irq_chip *chip) ++{ ++ /* Yes, dropping const is ugly, but it isn't like we have a choice */ ++ girq->chip = (struct irq_chip *)chip; ++} ++ + /* Line status inquiry for drivers */ + bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); + bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); +-- +2.42.0 + diff --git a/queue-5.10/gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch b/queue-5.10/gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch new file mode 100644 index 00000000000..415b3589a88 --- /dev/null +++ b/queue-5.10/gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch @@ -0,0 +1,89 @@ +From 7d68361f77afb1ca0865bca7d160f730b71dd16e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Apr 2022 15:18:37 +0100 +Subject: gpio: Don't fiddle with irqchips marked as immutable + +From: Marc Zyngier + +[ Upstream commit 6c846d026d490b2383d395bc8e7b06336219667b ] + +In order to move away from gpiolib messing with the internals of +unsuspecting irqchips, add a flag by which irqchips advertise +that they are not to be messed with, and do solemnly swear that +they correctly call into the gpiolib helpers when required. + +Also nudge the users into converting their drivers to the +new model. + +Reviewed-by: Andy Shevchenko +Reviewed-by: Bartosz Golaszewski +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220419141846.598305-2-maz@kernel.org +Stable-dep-of: dc3115e6c5d9 ("hid: cp2112: Fix IRQ shutdown stopping polling for all IRQs on chip") +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpiolib.c | 7 ++++++- + include/linux/irq.h | 2 ++ + kernel/irq/debugfs.c | 1 + + 3 files changed, 9 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index d10f621085e2e..8a6510d0fe5fc 100644 +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -1491,6 +1491,11 @@ static void gpiochip_set_irq_hooks(struct gpio_chip *gc) + { + struct irq_chip *irqchip = gc->irq.chip; + ++ if (irqchip->flags & IRQCHIP_IMMUTABLE) ++ return; ++ ++ chip_warn(gc, "not an immutable chip, please consider fixing it!\n"); ++ + if (!irqchip->irq_request_resources && + !irqchip->irq_release_resources) { + irqchip->irq_request_resources = gpiochip_irq_reqres; +@@ -1667,7 +1672,7 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gc) + irq_domain_remove(gc->irq.domain); + } + +- if (irqchip) { ++ if (irqchip && !(irqchip->flags & IRQCHIP_IMMUTABLE)) { + if (irqchip->irq_request_resources == gpiochip_irq_reqres) { + irqchip->irq_request_resources = NULL; + irqchip->irq_release_resources = NULL; +diff --git a/include/linux/irq.h b/include/linux/irq.h +index b89a8ac83d1bc..da4cd9fb3e5f3 100644 +--- a/include/linux/irq.h ++++ b/include/linux/irq.h +@@ -568,6 +568,7 @@ struct irq_chip { + * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs + * in the suspend path if they are in disabled state + * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup ++ * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip + */ + enum { + IRQCHIP_SET_TYPE_MASKED = (1 << 0), +@@ -581,6 +582,7 @@ enum { + IRQCHIP_SUPPORTS_NMI = (1 << 8), + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), + IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), ++ IRQCHIP_IMMUTABLE = (1 << 11), + }; + + #include +diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c +index e4cff358b437e..7ff52d94b42c0 100644 +--- a/kernel/irq/debugfs.c ++++ b/kernel/irq/debugfs.c +@@ -58,6 +58,7 @@ static const struct irq_bit_descr irqchip_flags[] = { + BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI), + BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI), + BIT_MASK_DESCR(IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND), ++ BIT_MASK_DESCR(IRQCHIP_IMMUTABLE), + }; + + static void +-- +2.42.0 + diff --git a/queue-5.10/gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch b/queue-5.10/gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch new file mode 100644 index 00000000000..2696b2b435d --- /dev/null +++ b/queue-5.10/gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch @@ -0,0 +1,70 @@ +From 9ab3c9635641c836c2b9ae874d945c10f978b0e6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Apr 2022 15:18:38 +0100 +Subject: gpio: Expose the gpiochip_irq_re[ql]res helpers + +From: Marc Zyngier + +[ Upstream commit 704f08753b6dcd0e08c1953af0b2c7f3fac87111 ] + +The GPIO subsystem has a couple of internal helpers to manage +resources on behalf of the irqchip. Expose them so that GPIO +drivers can use them directly. + +Reviewed-by: Andy Shevchenko +Reviewed-by: Bartosz Golaszewski +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220419141846.598305-3-maz@kernel.org +Stable-dep-of: dc3115e6c5d9 ("hid: cp2112: Fix IRQ shutdown stopping polling for all IRQs on chip") +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpiolib.c | 6 ++++-- + include/linux/gpio/driver.h | 4 ++++ + 2 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index 8a6510d0fe5fc..69ef51a05709a 100644 +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -1439,19 +1439,21 @@ static int gpiochip_to_irq(struct gpio_chip *gc, unsigned offset) + return irq_create_mapping(domain, offset); + } + +-static int gpiochip_irq_reqres(struct irq_data *d) ++int gpiochip_irq_reqres(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + return gpiochip_reqres_irq(gc, d->hwirq); + } ++EXPORT_SYMBOL(gpiochip_irq_reqres); + +-static void gpiochip_irq_relres(struct irq_data *d) ++void gpiochip_irq_relres(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_relres_irq(gc, d->hwirq); + } ++EXPORT_SYMBOL(gpiochip_irq_relres); + + static void gpiochip_irq_mask(struct irq_data *d) + { +diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h +index 64c93a36a3a92..38df53b541d53 100644 +--- a/include/linux/gpio/driver.h ++++ b/include/linux/gpio/driver.h +@@ -591,6 +591,10 @@ void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); + void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); + void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); + ++/* irq_data versions of the above */ ++int gpiochip_irq_reqres(struct irq_data *data); ++void gpiochip_irq_relres(struct irq_data *data); ++ + /* Line status inquiry for drivers */ + bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); + bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); +-- +2.42.0 + diff --git a/queue-5.10/gve-use-size_add-in-call-to-struct_size.patch b/queue-5.10/gve-use-size_add-in-call-to-struct_size.patch new file mode 100644 index 00000000000..75d7f81e48e --- /dev/null +++ b/queue-5.10/gve-use-size_add-in-call-to-struct_size.patch @@ -0,0 +1,38 @@ +From f8acf67cb89923d708c639d7d68882539dc8d39e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Sep 2023 12:17:49 -0600 +Subject: gve: Use size_add() in call to struct_size() + +From: Gustavo A. R. Silva + +[ Upstream commit d692873cbe861a870cdc9cbfb120eefd113c3dfd ] + +If, for any reason, `tx_stats_num + rx_stats_num` wraps around, the +protection that struct_size() adds against potential integer overflows +is defeated. Fix this by hardening call to struct_size() with size_add(). + +Fixes: 691f4077d560 ("gve: Replace zero-length array with flexible-array member") +Signed-off-by: Gustavo A. R. Silva +Reviewed-by: Kees Cook +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/google/gve/gve_main.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/google/gve/gve_main.c b/drivers/net/ethernet/google/gve/gve_main.c +index f0c1e6c80b61c..b76d1d019a81d 100644 +--- a/drivers/net/ethernet/google/gve/gve_main.c ++++ b/drivers/net/ethernet/google/gve/gve_main.c +@@ -128,7 +128,7 @@ static int gve_alloc_stats_report(struct gve_priv *priv) + rx_stats_num = (GVE_RX_STATS_REPORT_NUM + NIC_RX_STATS_REPORT_NUM) * + priv->rx_cfg.num_queues; + priv->stats_report_len = struct_size(priv->stats_report, stats, +- tx_stats_num + rx_stats_num); ++ size_add(tx_stats_num, rx_stats_num)); + priv->stats_report = + dma_alloc_coherent(&priv->pdev->dev, priv->stats_report_len, + &priv->stats_report_bus, GFP_KERNEL); +-- +2.42.0 + diff --git a/queue-5.10/hid-cp2112-fix-duplicate-workqueue-initialization.patch b/queue-5.10/hid-cp2112-fix-duplicate-workqueue-initialization.patch new file mode 100644 index 00000000000..84aa7ce55a2 --- /dev/null +++ b/queue-5.10/hid-cp2112-fix-duplicate-workqueue-initialization.patch @@ -0,0 +1,50 @@ +From 876546ea3e087b11172e019759f2a05961e5ff60 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Sep 2023 16:22:45 -0500 +Subject: hid: cp2112: Fix duplicate workqueue initialization + +From: Danny Kaehn + +[ Upstream commit e3c2d2d144c082dd71596953193adf9891491f42 ] + +Previously the cp2112 driver called INIT_DELAYED_WORK within +cp2112_gpio_irq_startup, resulting in duplicate initilizations of the +workqueue on subsequent IRQ startups following an initial request. This +resulted in a warning in set_work_data in workqueue.c, as well as a rare +NULL dereference within process_one_work in workqueue.c. + +Initialize the workqueue within _probe instead. + +Fixes: 13de9cca514e ("HID: cp2112: add IRQ chip handling") +Signed-off-by: Danny Kaehn +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-cp2112.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c +index d902fe43cb818..a683d38200267 100644 +--- a/drivers/hid/hid-cp2112.c ++++ b/drivers/hid/hid-cp2112.c +@@ -1157,8 +1157,6 @@ static unsigned int cp2112_gpio_irq_startup(struct irq_data *d) + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cp2112_device *dev = gpiochip_get_data(gc); + +- INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback); +- + if (!dev->gpio_poll) { + dev->gpio_poll = true; + schedule_delayed_work(&dev->gpio_poll_worker, 0); +@@ -1354,6 +1352,8 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) + girq->handler = handle_simple_irq; + girq->threaded = true; + ++ INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback); ++ + ret = gpiochip_add_data(&dev->gc, dev); + if (ret < 0) { + hid_err(hdev, "error registering gpio chip\n"); +-- +2.42.0 + diff --git a/queue-5.10/hid-cp2112-fix-irq-shutdown-stopping-polling-for-all.patch b/queue-5.10/hid-cp2112-fix-irq-shutdown-stopping-polling-for-all.patch new file mode 100644 index 00000000000..e3061fdecdc --- /dev/null +++ b/queue-5.10/hid-cp2112-fix-irq-shutdown-stopping-polling-for-all.patch @@ -0,0 +1,48 @@ +From 15ec08258775e23372c5894b2b69d0b702129f97 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 11 Oct 2023 13:23:17 -0500 +Subject: hid: cp2112: Fix IRQ shutdown stopping polling for all IRQs on chip + +From: Danny Kaehn + +[ Upstream commit dc3115e6c5d9863ec1a9ff1acf004ede93c34361 ] + +Previously cp2112_gpio_irq_shutdown() always cancelled the +gpio_poll_worker, even if other IRQs were still active, and did not set +the gpio_poll flag to false. This resulted in any call to _shutdown() +resulting in interrupts no longer functioning on the chip until a +_remove() occurred (a.e. the cp2112 is unplugged or system rebooted). + +Only cancel polling if all IRQs are disabled/masked, and correctly set +the gpio_poll flag, allowing polling to restart when an interrupt is +next enabled. + +Signed-off-by: Danny Kaehn +Fixes: 13de9cca514e ("HID: cp2112: add IRQ chip handling") +Link: https://lore.kernel.org/r/20231011182317.1053344-1-danny.kaehn@plexus.com +Signed-off-by: Benjamin Tissoires +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-cp2112.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c +index 704aebb1a588f..ee983ddc7fd03 100644 +--- a/drivers/hid/hid-cp2112.c ++++ b/drivers/hid/hid-cp2112.c +@@ -1175,7 +1175,11 @@ static void cp2112_gpio_irq_shutdown(struct irq_data *d) + struct cp2112_device *dev = gpiochip_get_data(gc); + + cp2112_gpio_irq_mask(d); +- cancel_delayed_work_sync(&dev->gpio_poll_worker); ++ ++ if (!dev->irq_mask) { ++ dev->gpio_poll = false; ++ cancel_delayed_work_sync(&dev->gpio_poll_worker); ++ } + } + + static int cp2112_gpio_irq_type(struct irq_data *d, unsigned int type) +-- +2.42.0 + diff --git a/queue-5.10/hid-cp2112-make-irq_chip-immutable.patch b/queue-5.10/hid-cp2112-make-irq_chip-immutable.patch new file mode 100644 index 00000000000..165bd4109dd --- /dev/null +++ b/queue-5.10/hid-cp2112-make-irq_chip-immutable.patch @@ -0,0 +1,109 @@ +From 16bfa9251b2616c98ccaa9ded3d79e74e6bfb935 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 3 Jul 2023 21:52:13 +0300 +Subject: HID: cp2112: Make irq_chip immutable + +From: Andy Shevchenko + +[ Upstream commit 3e2977c425ad2789ca18084fff913cceacae75a2 ] + +Since recently, the kernel is nagging about mutable irq_chips: + + "not an immutable chip, please consider fixing it!" + +Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new +helper functions and call the appropriate gpiolib functions. + +Signed-off-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20230703185222.50554-4-andriy.shevchenko@linux.intel.com +Signed-off-by: Benjamin Tissoires +Stable-dep-of: dc3115e6c5d9 ("hid: cp2112: Fix IRQ shutdown stopping polling for all IRQs on chip") +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-cp2112.c | 33 ++++++++++++++++++++------------- + 1 file changed, 20 insertions(+), 13 deletions(-) + +diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c +index a683d38200267..704aebb1a588f 100644 +--- a/drivers/hid/hid-cp2112.c ++++ b/drivers/hid/hid-cp2112.c +@@ -161,7 +161,6 @@ struct cp2112_device { + atomic_t read_avail; + atomic_t xfer_avail; + struct gpio_chip gc; +- struct irq_chip irq; + u8 *in_out_buffer; + struct mutex lock; + +@@ -1078,16 +1077,20 @@ static void cp2112_gpio_irq_mask(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cp2112_device *dev = gpiochip_get_data(gc); ++ irq_hw_number_t hwirq = irqd_to_hwirq(d); + +- __clear_bit(d->hwirq, &dev->irq_mask); ++ __clear_bit(hwirq, &dev->irq_mask); ++ gpiochip_disable_irq(gc, hwirq); + } + + static void cp2112_gpio_irq_unmask(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cp2112_device *dev = gpiochip_get_data(gc); ++ irq_hw_number_t hwirq = irqd_to_hwirq(d); + +- __set_bit(d->hwirq, &dev->irq_mask); ++ gpiochip_enable_irq(gc, hwirq); ++ __set_bit(hwirq, &dev->irq_mask); + } + + static void cp2112_gpio_poll_callback(struct work_struct *work) +@@ -1171,6 +1174,7 @@ static void cp2112_gpio_irq_shutdown(struct irq_data *d) + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cp2112_device *dev = gpiochip_get_data(gc); + ++ cp2112_gpio_irq_mask(d); + cancel_delayed_work_sync(&dev->gpio_poll_worker); + } + +@@ -1224,6 +1228,18 @@ static int __maybe_unused cp2112_allocate_irq(struct cp2112_device *dev, + return ret; + } + ++static const struct irq_chip cp2112_gpio_irqchip = { ++ .name = "cp2112-gpio", ++ .irq_startup = cp2112_gpio_irq_startup, ++ .irq_shutdown = cp2112_gpio_irq_shutdown, ++ .irq_ack = cp2112_gpio_irq_ack, ++ .irq_mask = cp2112_gpio_irq_mask, ++ .irq_unmask = cp2112_gpio_irq_unmask, ++ .irq_set_type = cp2112_gpio_irq_type, ++ .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, ++ GPIOCHIP_IRQ_RESOURCE_HELPERS, ++}; ++ + static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) + { + struct cp2112_device *dev; +@@ -1333,17 +1349,8 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) + dev->gc.can_sleep = 1; + dev->gc.parent = &hdev->dev; + +- dev->irq.name = "cp2112-gpio"; +- dev->irq.irq_startup = cp2112_gpio_irq_startup; +- dev->irq.irq_shutdown = cp2112_gpio_irq_shutdown; +- dev->irq.irq_ack = cp2112_gpio_irq_ack; +- dev->irq.irq_mask = cp2112_gpio_irq_mask; +- dev->irq.irq_unmask = cp2112_gpio_irq_unmask; +- dev->irq.irq_set_type = cp2112_gpio_irq_type; +- dev->irq.flags = IRQCHIP_MASK_ON_SUSPEND; +- + girq = &dev->gc.irq; +- girq->chip = &dev->irq; ++ gpio_irq_chip_set_chip(girq, &cp2112_gpio_irqchip); + /* The event comes from the outside so no parent handler */ + girq->parent_handler = NULL; + girq->num_parents = 0; +-- +2.42.0 + diff --git a/queue-5.10/hid-logitech-hidpp-don-t-restart-io-instead-defer-hi.patch b/queue-5.10/hid-logitech-hidpp-don-t-restart-io-instead-defer-hi.patch new file mode 100644 index 00000000000..15f32007c68 --- /dev/null +++ b/queue-5.10/hid-logitech-hidpp-don-t-restart-io-instead-defer-hi.patch @@ -0,0 +1,119 @@ +From f24bbf0ca82813db0828949d2cce131afb1f305a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 10 Oct 2023 12:20:18 +0200 +Subject: HID: logitech-hidpp: Don't restart IO, instead defer hid_connect() + only + +From: Hans de Goede + +[ Upstream commit 11ca0322a41920df2b462d2e45b0731e47ff475b ] + +Restarting IO causes 2 problems: + +1. Some devices do not like IO being restarted this was addressed in + commit 498ba2069035 ("HID: logitech-hidpp: Don't restart communication + if not necessary"), but that change has issues of its own and needs to + be reverted. + +2. Restarting IO and specifically calling hid_device_io_stop() causes + received packets to be missed, which may cause connect-events to + get missed. + +Restarting IO was introduced in commit 91cf9a98ae41 ("HID: logitech-hidpp: +make .probe usbhid capable") to allow to retrieve the device's name and +serial number and store these in hdev->name and hdev->uniq before +connecting any hid subdrivers (hid-input, hidraw) exporting this info +to userspace. + +But this does not require restarting IO, this merely requires deferring +calling hid_connect(). Calling hid_hw_start() with a connect-mask of +0 makes it skip calling hid_connect(), so hidpp_probe() can simply call +hid_connect() later without needing to restart IO. + +Remove the stop + restart of IO and instead just call hid_connect() later +to avoid the issues caused by restarting IO. + +Now that IO is no longer stopped, hid_hw_close() must be called at the end +of probe() to balance the hid_hw_open() done at the beginning probe(). + +This series has been tested on the following devices: +Logitech Bluetooth Laser Travel Mouse (bluetooth, HID++ 1.0) +Logitech M720 Triathlon (bluetooth, HID++ 4.5) +Logitech M720 Triathlon (unifying, HID++ 4.5) +Logitech K400 Pro (unifying, HID++ 4.1) +Logitech K270 (eQUAD nano Lite, HID++ 2.0) +Logitech M185 (eQUAD nano Lite, HID++ 4.5) +Logitech LX501 keyboard (27 Mhz, HID++ builtin scroll-wheel, HID++ 1.0) +Logitech M-RAZ105 mouse (27 Mhz, HID++ extra mouse buttons, HID++ 1.0) + +And by bentiss: +Logitech Touchpad T650 (unifying) +Logitech Touchpad T651 (bluetooth) +Logitech MX Master 3B (BLE) +Logitech G403 (plain USB / Gaming receiver) + +Fixes: 498ba2069035 ("HID: logitech-hidpp: Don't restart communication if not necessary") +Suggested-by: Benjamin Tissoires +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20231010102029.111003-2-hdegoede@redhat.com +Signed-off-by: Benjamin Tissoires +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-logitech-hidpp.c | 22 ++++++++++++---------- + 1 file changed, 12 insertions(+), 10 deletions(-) + +diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c +index e012d2d1a644f..5755b3e63c338 100644 +--- a/drivers/hid/hid-logitech-hidpp.c ++++ b/drivers/hid/hid-logitech-hidpp.c +@@ -3869,8 +3869,10 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + hdev->name); + + /* +- * Plain USB connections need to actually call start and open +- * on the transport driver to allow incoming data. ++ * First call hid_hw_start(hdev, 0) to allow IO without connecting any ++ * hid subdrivers (hid-input, hidraw). This allows retrieving the dev's ++ * name and serial number and store these in hdev->name and hdev->uniq, ++ * before the hid-input and hidraw drivers expose these to userspace. + */ + ret = hid_hw_start(hdev, will_restart ? 0 : connect_mask); + if (ret) { +@@ -3928,19 +3930,14 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + flush_work(&hidpp->work); + + if (will_restart) { +- /* Reset the HID node state */ +- hid_device_io_stop(hdev); +- hid_hw_close(hdev); +- hid_hw_stop(hdev); +- + if (hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT) + connect_mask &= ~HID_CONNECT_HIDINPUT; + + /* Now export the actual inputs and hidraw nodes to the world */ +- ret = hid_hw_start(hdev, connect_mask); ++ ret = hid_connect(hdev, connect_mask); + if (ret) { +- hid_err(hdev, "%s:hid_hw_start returned error\n", __func__); +- goto hid_hw_start_fail; ++ hid_err(hdev, "%s:hid_connect returned error %d\n", __func__, ret); ++ goto hid_hw_init_fail; + } + } + +@@ -3952,6 +3949,11 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + ret); + } + ++ /* ++ * This relies on logi_dj_ll_close() being a no-op so that DJ connection ++ * events will still be received. ++ */ ++ hid_hw_close(hdev); + return ret; + + hid_hw_init_fail: +-- +2.42.0 + diff --git a/queue-5.10/hid-logitech-hidpp-move-get_wireless_feature_index-c.patch b/queue-5.10/hid-logitech-hidpp-move-get_wireless_feature_index-c.patch new file mode 100644 index 00000000000..08057e1af69 --- /dev/null +++ b/queue-5.10/hid-logitech-hidpp-move-get_wireless_feature_index-c.patch @@ -0,0 +1,98 @@ +From 3489204e6f1330858f9b5499bc7a56bdc5825f7d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 10 Oct 2023 12:20:20 +0200 +Subject: HID: logitech-hidpp: Move get_wireless_feature_index() check to + hidpp_connect_event() + +From: Hans de Goede + +[ Upstream commit ba9de350509504fb748837b71e23d7e84c83d93c ] + +Calling get_wireless_feature_index() from probe() causes +the wireless_feature_index to only get set for unifying devices which +are already connected at probe() time. It does not get set for devices +which connect later. + +Fix this by moving get_wireless_feature_index() to hidpp_connect_event(), +this does not make a difference for devices connected at probe() since +probe() will queue the hidpp_connect_event() for those at probe time. + +This series has been tested on the following devices: +Logitech Bluetooth Laser Travel Mouse (bluetooth, HID++ 1.0) +Logitech M720 Triathlon (bluetooth, HID++ 4.5) +Logitech M720 Triathlon (unifying, HID++ 4.5) +Logitech K400 Pro (unifying, HID++ 4.1) +Logitech K270 (eQUAD nano Lite, HID++ 2.0) +Logitech M185 (eQUAD nano Lite, HID++ 4.5) +Logitech LX501 keyboard (27 Mhz, HID++ builtin scroll-wheel, HID++ 1.0) +Logitech M-RAZ105 mouse (27 Mhz, HID++ extra mouse buttons, HID++ 1.0) + +And by bentiss: +Logitech Touchpad T650 (unifying) +Logitech Touchpad T651 (bluetooth) +Logitech MX Master 3B (BLE) +Logitech G403 (plain USB / Gaming receiver) + +Fixes: 0da0a63b7cba ("HID: logitech-hidpp: Support WirelessDeviceStatus connect events") +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20231010102029.111003-4-hdegoede@redhat.com +Signed-off-by: Benjamin Tissoires +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-logitech-hidpp.c | 20 +++++++++----------- + 1 file changed, 9 insertions(+), 11 deletions(-) + +diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c +index 6342363248cc1..8bdcd4027416f 100644 +--- a/drivers/hid/hid-logitech-hidpp.c ++++ b/drivers/hid/hid-logitech-hidpp.c +@@ -1488,15 +1488,14 @@ static int hidpp_battery_get_property(struct power_supply *psy, + /* -------------------------------------------------------------------------- */ + #define HIDPP_PAGE_WIRELESS_DEVICE_STATUS 0x1d4b + +-static int hidpp_set_wireless_feature_index(struct hidpp_device *hidpp) ++static int hidpp_get_wireless_feature_index(struct hidpp_device *hidpp, u8 *feature_index) + { + u8 feature_type; + int ret; + + ret = hidpp_root_get_feature(hidpp, + HIDPP_PAGE_WIRELESS_DEVICE_STATUS, +- &hidpp->wireless_feature_index, +- &feature_type); ++ feature_index, &feature_type); + + return ret; + } +@@ -3666,6 +3665,13 @@ static void hidpp_connect_event(struct hidpp_device *hidpp) + } + } + ++ if (hidpp->protocol_major >= 2) { ++ u8 feature_index; ++ ++ if (!hidpp_get_wireless_feature_index(hidpp, &feature_index)) ++ hidpp->wireless_feature_index = feature_index; ++ } ++ + if (hidpp->name == hdev->name && hidpp->protocol_major >= 2) { + name = hidpp_get_device_name(hidpp); + if (name) { +@@ -3902,14 +3908,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + hidpp_overwrite_name(hdev); + } + +- if (connected && hidpp->protocol_major >= 2) { +- ret = hidpp_set_wireless_feature_index(hidpp); +- if (ret == -ENOENT) +- hidpp->wireless_feature_index = 0; +- else if (ret) +- goto hid_hw_init_fail; +- } +- + if (connected && (hidpp->quirks & HIDPP_QUIRK_CLASS_WTP)) { + ret = wtp_get_config(hidpp); + if (ret) +-- +2.42.0 + diff --git a/queue-5.10/hid-logitech-hidpp-remove-hidpp_quirk_no_hidinput-qu.patch b/queue-5.10/hid-logitech-hidpp-remove-hidpp_quirk_no_hidinput-qu.patch new file mode 100644 index 00000000000..f1c8312ac71 --- /dev/null +++ b/queue-5.10/hid-logitech-hidpp-remove-hidpp_quirk_no_hidinput-qu.patch @@ -0,0 +1,69 @@ +From 93fd0c06bae492b147a639e8776d8385fed4c70c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 Jan 2023 13:17:23 +0100 +Subject: HID: logitech-hidpp: Remove HIDPP_QUIRK_NO_HIDINPUT quirk + +From: Bastien Nocera + +[ Upstream commit d83956c8855c6c2ed4bd16cec4a5083d63df17e4 ] + +HIDPP_QUIRK_NO_HIDINPUT isn't used by any devices but still happens to +work as HIDPP_QUIRK_DELAYED_INIT is defined to the same value. Remove +HIDPP_QUIRK_NO_HIDINPUT and use HIDPP_QUIRK_DELAYED_INIT everywhere +instead. + +Tested on a T650 which requires that quirk, and a number of unifying and +Bluetooth devices that don't. + +Signed-off-by: Bastien Nocera +Link: https://lore.kernel.org/r/20230125121723.3122-2-hadess@hadess.net +Signed-off-by: Benjamin Tissoires +Stable-dep-of: 11ca0322a419 ("HID: logitech-hidpp: Don't restart IO, instead defer hid_connect() only") +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-logitech-hidpp.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c +index 8d81a700886fc..e012d2d1a644f 100644 +--- a/drivers/hid/hid-logitech-hidpp.c ++++ b/drivers/hid/hid-logitech-hidpp.c +@@ -61,7 +61,7 @@ MODULE_PARM_DESC(disable_tap_to_click, + /* bits 2..20 are reserved for classes */ + /* #define HIDPP_QUIRK_CONNECT_EVENTS BIT(21) disabled */ + #define HIDPP_QUIRK_WTP_PHYSICAL_BUTTONS BIT(22) +-#define HIDPP_QUIRK_NO_HIDINPUT BIT(23) ++#define HIDPP_QUIRK_DELAYED_INIT BIT(23) + #define HIDPP_QUIRK_FORCE_OUTPUT_REPORTS BIT(24) + #define HIDPP_QUIRK_UNIFYING BIT(25) + #define HIDPP_QUIRK_HI_RES_SCROLL_1P0 BIT(26) +@@ -80,8 +80,6 @@ MODULE_PARM_DESC(disable_tap_to_click, + HIDPP_QUIRK_HI_RES_SCROLL_X2120 | \ + HIDPP_QUIRK_HI_RES_SCROLL_X2121) + +-#define HIDPP_QUIRK_DELAYED_INIT HIDPP_QUIRK_NO_HIDINPUT +- + #define HIDPP_CAPABILITY_HIDPP10_BATTERY BIT(0) + #define HIDPP_CAPABILITY_HIDPP20_BATTERY BIT(1) + #define HIDPP_CAPABILITY_BATTERY_MILEAGE BIT(2) +@@ -3702,7 +3700,7 @@ static void hidpp_connect_event(struct hidpp_device *hidpp) + if (hidpp->quirks & HIDPP_QUIRK_HI_RES_SCROLL) + hi_res_scroll_enable(hidpp); + +- if (!(hidpp->quirks & HIDPP_QUIRK_NO_HIDINPUT) || hidpp->delayed_input) ++ if (!(hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT) || hidpp->delayed_input) + /* if the input nodes are already created, we can stop now */ + return; + +@@ -3935,7 +3933,7 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + hid_hw_close(hdev); + hid_hw_stop(hdev); + +- if (hidpp->quirks & HIDPP_QUIRK_NO_HIDINPUT) ++ if (hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT) + connect_mask &= ~HID_CONNECT_HIDINPUT; + + /* Now export the actual inputs and hidraw nodes to the world */ +-- +2.42.0 + diff --git a/queue-5.10/hid-logitech-hidpp-revert-don-t-restart-communicatio.patch b/queue-5.10/hid-logitech-hidpp-revert-don-t-restart-communicatio.patch new file mode 100644 index 00000000000..6e122c05e8e --- /dev/null +++ b/queue-5.10/hid-logitech-hidpp-revert-don-t-restart-communicatio.patch @@ -0,0 +1,129 @@ +From 34ddc0fce86c4f7df689d464a4586ed7b04ff03f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 10 Oct 2023 12:20:19 +0200 +Subject: HID: logitech-hidpp: Revert "Don't restart communication if not + necessary" + +From: Hans de Goede + +[ Upstream commit 55bf70362ffc4ddd7c8745e2fe880edac00e4aff ] + +Commit 91cf9a98ae41 ("HID: logitech-hidpp: make .probe usbhid capable") +makes hidpp_probe() first call hid_hw_start(hdev, 0) to allow IO +without connecting any hid subdrivers (hid-input, hidraw). + +This is done to allow to retrieve the device's name and serial number +and store these in hdev->name and hdev->uniq. + +Then later on IO was stopped and started again with hid_hw_start(hdev, +HID_CONNECT_DEFAULT) connecting hid-input and hidraw after the name +and serial number have been setup. + +Commit 498ba2069035 ("HID: logitech-hidpp: Don't restart communication +if not necessary") changed the probe() code to only do the start with +a 0 connect-mask + restart later for unifying devices. + +But for non unifying devices hdev->name and hdev->uniq are updated too. +So this change re-introduces the problem for which the start with +a 0 connect-mask + restart later behavior was introduced. + +The previous patch in this series changes the unifying path to instead of +restarting IO only call hid_connect() later. This avoids possible issues +with restarting IO seen on non unifying devices. + +Revert the change to limit the restart behavior to unifying devices to +fix hdev->name changing after userspace facing devices have already been +registered. + +This series has been tested on the following devices: +Logitech Bluetooth Laser Travel Mouse (bluetooth, HID++ 1.0) +Logitech M720 Triathlon (bluetooth, HID++ 4.5) +Logitech M720 Triathlon (unifying, HID++ 4.5) +Logitech K400 Pro (unifying, HID++ 4.1) +Logitech K270 (eQUAD nano Lite, HID++ 2.0) +Logitech M185 (eQUAD nano Lite, HID++ 4.5) +Logitech LX501 keyboard (27 Mhz, HID++ builtin scroll-wheel, HID++ 1.0) +Logitech M-RAZ105 mouse (27 Mhz, HID++ extra mouse buttons, HID++ 1.0) + +And by bentiss: +Logitech Touchpad T650 (unifying) +Logitech Touchpad T651 (bluetooth) +Logitech MX Master 3B (BLE) +Logitech G403 (plain USB / Gaming receiver) + +Fixes: 498ba2069035 ("HID: logitech-hidpp: Don't restart communication if not necessary") +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20231010102029.111003-3-hdegoede@redhat.com +Signed-off-by: Benjamin Tissoires +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-logitech-hidpp.c | 24 ++++++++---------------- + 1 file changed, 8 insertions(+), 16 deletions(-) + +diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c +index 5755b3e63c338..6342363248cc1 100644 +--- a/drivers/hid/hid-logitech-hidpp.c ++++ b/drivers/hid/hid-logitech-hidpp.c +@@ -3803,7 +3803,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + bool connected; + unsigned int connect_mask = HID_CONNECT_DEFAULT; + struct hidpp_ff_private_data data; +- bool will_restart = false; + + /* report_fixup needs drvdata to be set before we call hid_parse */ + hidpp = devm_kzalloc(&hdev->dev, sizeof(*hidpp), GFP_KERNEL); +@@ -3854,10 +3853,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + return ret; + } + +- if (hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT || +- hidpp->quirks & HIDPP_QUIRK_UNIFYING) +- will_restart = true; +- + INIT_WORK(&hidpp->work, delayed_work_cb); + mutex_init(&hidpp->send_mutex); + init_waitqueue_head(&hidpp->wait); +@@ -3874,7 +3869,7 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + * name and serial number and store these in hdev->name and hdev->uniq, + * before the hid-input and hidraw drivers expose these to userspace. + */ +- ret = hid_hw_start(hdev, will_restart ? 0 : connect_mask); ++ ret = hid_hw_start(hdev, 0); + if (ret) { + hid_err(hdev, "hw start failed\n"); + goto hid_hw_start_fail; +@@ -3913,7 +3908,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + hidpp->wireless_feature_index = 0; + else if (ret) + goto hid_hw_init_fail; +- ret = 0; + } + + if (connected && (hidpp->quirks & HIDPP_QUIRK_CLASS_WTP)) { +@@ -3929,16 +3923,14 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + schedule_work(&hidpp->work); + flush_work(&hidpp->work); + +- if (will_restart) { +- if (hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT) +- connect_mask &= ~HID_CONNECT_HIDINPUT; ++ if (hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT) ++ connect_mask &= ~HID_CONNECT_HIDINPUT; + +- /* Now export the actual inputs and hidraw nodes to the world */ +- ret = hid_connect(hdev, connect_mask); +- if (ret) { +- hid_err(hdev, "%s:hid_connect returned error %d\n", __func__, ret); +- goto hid_hw_init_fail; +- } ++ /* Now export the actual inputs and hidraw nodes to the world */ ++ ret = hid_connect(hdev, connect_mask); ++ if (ret) { ++ hid_err(hdev, "%s:hid_connect returned error %d\n", __func__, ret); ++ goto hid_hw_init_fail; + } + + if (hidpp->quirks & HIDPP_QUIRK_CLASS_G920) { +-- +2.42.0 + diff --git a/queue-5.10/hwmon-axi-fan-control-fix-possible-null-pointer-dere.patch b/queue-5.10/hwmon-axi-fan-control-fix-possible-null-pointer-dere.patch new file mode 100644 index 00000000000..15c32b7dea8 --- /dev/null +++ b/queue-5.10/hwmon-axi-fan-control-fix-possible-null-pointer-dere.patch @@ -0,0 +1,74 @@ +From 48ea371c3cd4a30ccded797f428b9297e681ea68 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 Oct 2023 15:21:00 +0200 +Subject: hwmon: (axi-fan-control) Fix possible NULL pointer dereference + +From: Dragos Bogdan + +[ Upstream commit 2a5b3370a1d9750eca325292e291c8c7cb8cf2e0 ] + +axi_fan_control_irq_handler(), dependent on the private +axi_fan_control_data structure, might be called before the hwmon +device is registered. That will cause an "Unable to handle kernel +NULL pointer dereference" error. + +Fixes: 8412b410fa5e ("hwmon: Support ADI Fan Control IP") +Signed-off-by: Dragos Bogdan +Signed-off-by: Nuno Sa +Link: https://lore.kernel.org/r/20231025132100.649499-1-nuno.sa@analog.com +Signed-off-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/hwmon/axi-fan-control.c | 29 ++++++++++++++++------------- + 1 file changed, 16 insertions(+), 13 deletions(-) + +diff --git a/drivers/hwmon/axi-fan-control.c b/drivers/hwmon/axi-fan-control.c +index da0c3b6101f59..4b8250f2bb421 100644 +--- a/drivers/hwmon/axi-fan-control.c ++++ b/drivers/hwmon/axi-fan-control.c +@@ -495,6 +495,21 @@ static int axi_fan_control_probe(struct platform_device *pdev) + return -ENODEV; + } + ++ ret = axi_fan_control_init(ctl, pdev->dev.of_node); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to initialize device\n"); ++ return ret; ++ } ++ ++ ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev, ++ name, ++ ctl, ++ &axi_chip_info, ++ axi_fan_control_groups); ++ ++ if (IS_ERR(ctl->hdev)) ++ return PTR_ERR(ctl->hdev); ++ + ctl->irq = platform_get_irq(pdev, 0); + if (ctl->irq < 0) + return ctl->irq; +@@ -508,19 +523,7 @@ static int axi_fan_control_probe(struct platform_device *pdev) + return ret; + } + +- ret = axi_fan_control_init(ctl, pdev->dev.of_node); +- if (ret) { +- dev_err(&pdev->dev, "Failed to initialize device\n"); +- return ret; +- } +- +- ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev, +- name, +- ctl, +- &axi_chip_info, +- axi_fan_control_groups); +- +- return PTR_ERR_OR_ZERO(ctl->hdev); ++ return 0; + } + + static struct platform_driver axi_fan_control_driver = { +-- +2.42.0 + diff --git a/queue-5.10/hwmon-axi-fan-control-support-temperature-vs-pwm-poi.patch b/queue-5.10/hwmon-axi-fan-control-support-temperature-vs-pwm-poi.patch new file mode 100644 index 00000000000..baa78338ac5 --- /dev/null +++ b/queue-5.10/hwmon-axi-fan-control-support-temperature-vs-pwm-poi.patch @@ -0,0 +1,158 @@ +From b41b662f57ba309137d35572e094fc4cd1202916 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 11 Aug 2021 13:48:53 +0200 +Subject: hwmon: (axi-fan-control) Support temperature vs pwm points +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nuno Sá + +[ Upstream commit 2aee7e67bee7a5aa741bad6a0a472f108b29ad40 ] + +The HW has some predefined points where it will associate a PWM value. +However some users might want to better set these points to their +usecases. This patch exposes these points as pwm auto_points: + + * pwm1_auto_point1_temp_hyst: temperature threshold below which PWM should + be 0%; + * pwm1_auto_point1_temp: temperature threshold above which PWM should be + 25%; + * pwm1_auto_point2_temp_hyst: temperature threshold below which PWM should + be 25%; + * pwm1_auto_point2_temp: temperature threshold above which PWM should be + 50%; + * pwm1_auto_point3_temp_hyst: temperature threshold below which PWM should + be 50%; + * pwm1_auto_point3_temp: temperature threshold above which PWM should be + 75%; + * pwm1_auto_point4_temp_hyst: temperature threshold below which PWM should + be 75%; + * pwm1_auto_point4_temp: temperature threshold above which PWM should be + 100%; + +Signed-off-by: Nuno Sá +Link: https://lore.kernel.org/r/20210811114853.159298-4-nuno.sa@analog.com +Signed-off-by: Guenter Roeck +Stable-dep-of: 2a5b3370a1d9 ("hwmon: (axi-fan-control) Fix possible NULL pointer dereference") +Signed-off-by: Sasha Levin +--- + drivers/hwmon/axi-fan-control.c | 74 ++++++++++++++++++++++++++++++++- + 1 file changed, 73 insertions(+), 1 deletion(-) + +diff --git a/drivers/hwmon/axi-fan-control.c b/drivers/hwmon/axi-fan-control.c +index e3f6b03e6764b..da0c3b6101f59 100644 +--- a/drivers/hwmon/axi-fan-control.c ++++ b/drivers/hwmon/axi-fan-control.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -23,6 +24,14 @@ + #define ADI_REG_PWM_PERIOD 0x00c0 + #define ADI_REG_TACH_MEASUR 0x00c4 + #define ADI_REG_TEMPERATURE 0x00c8 ++#define ADI_REG_TEMP_00_H 0x0100 ++#define ADI_REG_TEMP_25_L 0x0104 ++#define ADI_REG_TEMP_25_H 0x0108 ++#define ADI_REG_TEMP_50_L 0x010c ++#define ADI_REG_TEMP_50_H 0x0110 ++#define ADI_REG_TEMP_75_L 0x0114 ++#define ADI_REG_TEMP_75_H 0x0118 ++#define ADI_REG_TEMP_100_L 0x011c + + #define ADI_REG_IRQ_MASK 0x0040 + #define ADI_REG_IRQ_PENDING 0x0044 +@@ -62,6 +71,39 @@ static inline u32 axi_ioread(const u32 reg, + return ioread32(ctl->base + reg); + } + ++/* ++ * The core calculates the temperature as: ++ * T = /raw * 509.3140064 / 65535) - 280.2308787 ++ */ ++static ssize_t axi_fan_control_show(struct device *dev, struct device_attribute *da, char *buf) ++{ ++ struct axi_fan_control_data *ctl = dev_get_drvdata(dev); ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(da); ++ u32 temp = axi_ioread(attr->index, ctl); ++ ++ temp = DIV_ROUND_CLOSEST_ULL(temp * 509314ULL, 65535) - 280230; ++ ++ return sprintf(buf, "%u\n", temp); ++} ++ ++static ssize_t axi_fan_control_store(struct device *dev, struct device_attribute *da, ++ const char *buf, size_t count) ++{ ++ struct axi_fan_control_data *ctl = dev_get_drvdata(dev); ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(da); ++ u32 temp; ++ int ret; ++ ++ ret = kstrtou32(buf, 10, &temp); ++ if (ret) ++ return ret; ++ ++ temp = DIV_ROUND_CLOSEST_ULL((temp + 280230) * 65535ULL, 509314); ++ axi_iowrite(temp, attr->index, ctl); ++ ++ return count; ++} ++ + static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl) + { + u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl); +@@ -370,6 +412,36 @@ static const struct hwmon_chip_info axi_chip_info = { + .info = axi_fan_control_info, + }; + ++/* temperature threshold below which PWM should be 0% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp_hyst, axi_fan_control, ADI_REG_TEMP_00_H); ++/* temperature threshold above which PWM should be 25% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp, axi_fan_control, ADI_REG_TEMP_25_L); ++/* temperature threshold below which PWM should be 25% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_temp_hyst, axi_fan_control, ADI_REG_TEMP_25_H); ++/* temperature threshold above which PWM should be 50% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_temp, axi_fan_control, ADI_REG_TEMP_50_L); ++/* temperature threshold below which PWM should be 50% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point3_temp_hyst, axi_fan_control, ADI_REG_TEMP_50_H); ++/* temperature threshold above which PWM should be 75% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point3_temp, axi_fan_control, ADI_REG_TEMP_75_L); ++/* temperature threshold below which PWM should be 75% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point4_temp_hyst, axi_fan_control, ADI_REG_TEMP_75_H); ++/* temperature threshold above which PWM should be 100% */ ++static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point4_temp, axi_fan_control, ADI_REG_TEMP_100_L); ++ ++static struct attribute *axi_fan_control_attrs[] = { ++ &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, ++ &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, ++ &sensor_dev_attr_pwm1_auto_point2_temp_hyst.dev_attr.attr, ++ &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, ++ &sensor_dev_attr_pwm1_auto_point3_temp_hyst.dev_attr.attr, ++ &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, ++ &sensor_dev_attr_pwm1_auto_point4_temp_hyst.dev_attr.attr, ++ &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, ++ NULL, ++}; ++ATTRIBUTE_GROUPS(axi_fan_control); ++ + static const u32 version_1_0_0 = ADI_AXI_PCORE_VER(1, 0, 'a'); + + static const struct of_device_id axi_fan_control_of_match[] = { +@@ -446,7 +518,7 @@ static int axi_fan_control_probe(struct platform_device *pdev) + name, + ctl, + &axi_chip_info, +- NULL); ++ axi_fan_control_groups); + + return PTR_ERR_OR_ZERO(ctl->hdev); + } +-- +2.42.0 + diff --git a/queue-5.10/hwmon-coretemp-fix-potentially-truncated-sysfs-attri.patch b/queue-5.10/hwmon-coretemp-fix-potentially-truncated-sysfs-attri.patch new file mode 100644 index 00000000000..f1ab4db426a --- /dev/null +++ b/queue-5.10/hwmon-coretemp-fix-potentially-truncated-sysfs-attri.patch @@ -0,0 +1,59 @@ +From 94796d4868f0b32418b740bdafeca036426a44bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 Oct 2023 20:23:16 +0800 +Subject: hwmon: (coretemp) Fix potentially truncated sysfs attribute name + +From: Zhang Rui + +[ Upstream commit bbfff736d30e5283ad09e748caff979d75ddef7f ] + +When build with W=1 and "-Werror=format-truncation", below error is +observed in coretemp driver, + + drivers/hwmon/coretemp.c: In function 'create_core_data': +>> drivers/hwmon/coretemp.c:393:34: error: '%s' directive output may be truncated writing likely 5 or more bytes into a region of size between 3 and 13 [-Werror=format-truncation=] + 393 | "temp%d_%s", attr_no, suffixes[i]); + | ^~ + drivers/hwmon/coretemp.c:393:26: note: assuming directive output of 5 bytes + 393 | "temp%d_%s", attr_no, suffixes[i]); + | ^~~~~~~~~~~ + drivers/hwmon/coretemp.c:392:17: note: 'snprintf' output 7 or more bytes (assuming 22) into a destination of size 19 + 392 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + 393 | "temp%d_%s", attr_no, suffixes[i]); + | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + cc1: all warnings being treated as errors + +Given that +1. '%d' could take 10 charactors, +2. '%s' could take 10 charactors ("crit_alarm"), +3. "temp", "_" and the NULL terminator take 6 charactors, +fix the problem by increasing CORETEMP_NAME_LENGTH to 28. + +Signed-off-by: Zhang Rui +Fixes: 7108b80a542b ("hwmon/coretemp: Handle large core ID value") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202310200443.iD3tUbbK-lkp@intel.com/ +Link: https://lore.kernel.org/r/20231025122316.836400-1-rui.zhang@intel.com +Signed-off-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/hwmon/coretemp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c +index eaae5de2ab616..5b2057ce5a59d 100644 +--- a/drivers/hwmon/coretemp.c ++++ b/drivers/hwmon/coretemp.c +@@ -41,7 +41,7 @@ MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); + #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ + #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ + #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ +-#define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ ++#define CORETEMP_NAME_LENGTH 28 /* String Length of attrs */ + #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ + #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) + #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) +-- +2.42.0 + diff --git a/queue-5.10/hwrng-geode-fix-accessing-registers.patch b/queue-5.10/hwrng-geode-fix-accessing-registers.patch new file mode 100644 index 00000000000..29c93f75b88 --- /dev/null +++ b/queue-5.10/hwrng-geode-fix-accessing-registers.patch @@ -0,0 +1,58 @@ +From 9876c2d04c29e2bf420bc77b460d307a461cb612 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 10 Sep 2023 10:34:17 +0200 +Subject: hwrng: geode - fix accessing registers + +From: Jonas Gorski + +[ Upstream commit 464bd8ec2f06707f3773676a1bd2c64832a3c805 ] + +When the membase and pci_dev pointer were moved to a new struct in priv, +the actual membase users were left untouched, and they started reading +out arbitrary memory behind the struct instead of registers. This +unfortunately turned the RNG into a constant number generator, depending +on the content of what was at that offset. + +To fix this, update geode_rng_data_{read,present}() to also get the +membase via amd_geode_priv, and properly read from the right addresses +again. + +Fixes: 9f6ec8dc574e ("hwrng: geode - Fix PCI device refcount leak") +Reported-by: Timur I. Davletshin +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217882 +Tested-by: Timur I. Davletshin +Suggested-by: Jo-Philipp Wich +Signed-off-by: Jonas Gorski +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/char/hw_random/geode-rng.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/char/hw_random/geode-rng.c b/drivers/char/hw_random/geode-rng.c +index 207272979f233..2f8289865ec81 100644 +--- a/drivers/char/hw_random/geode-rng.c ++++ b/drivers/char/hw_random/geode-rng.c +@@ -58,7 +58,8 @@ struct amd_geode_priv { + + static int geode_rng_data_read(struct hwrng *rng, u32 *data) + { +- void __iomem *mem = (void __iomem *)rng->priv; ++ struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv; ++ void __iomem *mem = priv->membase; + + *data = readl(mem + GEODE_RNG_DATA_REG); + +@@ -67,7 +68,8 @@ static int geode_rng_data_read(struct hwrng *rng, u32 *data) + + static int geode_rng_data_present(struct hwrng *rng, int wait) + { +- void __iomem *mem = (void __iomem *)rng->priv; ++ struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv; ++ void __iomem *mem = priv->membase; + int data, i; + + for (i = 0; i < 20; i++) { +-- +2.42.0 + diff --git a/queue-5.10/i3c-fix-potential-refcount-leak-in-i3c_master_regist.patch b/queue-5.10/i3c-fix-potential-refcount-leak-in-i3c_master_regist.patch new file mode 100644 index 00000000000..35c0f92df37 --- /dev/null +++ b/queue-5.10/i3c-fix-potential-refcount-leak-in-i3c_master_regist.patch @@ -0,0 +1,41 @@ +From c1d1a4a884155c60266c276ca49c970a78e39fcc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Sep 2023 16:24:10 +0800 +Subject: i3c: Fix potential refcount leak in i3c_master_register_new_i3c_devs + +From: Dinghao Liu + +[ Upstream commit cab63f64887616e3c4e31cfd8103320be6ebc8d3 ] + +put_device() needs to be called on failure of device_register() +to give up the reference initialized in it to avoid refcount leak. + +Fixes: 3a379bbcea0a ("i3c: Add core I3C infrastructure") +Signed-off-by: Dinghao Liu +Link: https://lore.kernel.org/r/20230921082410.25548-1-dinghao.liu@zju.edu.cn +Signed-off-by: Alexandre Belloni +Signed-off-by: Sasha Levin +--- + drivers/i3c/master.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c +index 1c6b78ad5ade4..828fb236a63ae 100644 +--- a/drivers/i3c/master.c ++++ b/drivers/i3c/master.c +@@ -1509,9 +1509,11 @@ i3c_master_register_new_i3c_devs(struct i3c_master_controller *master) + desc->dev->dev.of_node = desc->boardinfo->of_node; + + ret = device_register(&desc->dev->dev); +- if (ret) ++ if (ret) { + dev_err(&master->dev, + "Failed to add I3C device (err = %d)\n", ret); ++ put_device(&desc->dev->dev); ++ } + } + } + +-- +2.42.0 + diff --git a/queue-5.10/i40e-fix-potential-memory-leaks-in-i40e_remove.patch b/queue-5.10/i40e-fix-potential-memory-leaks-in-i40e_remove.patch new file mode 100644 index 00000000000..14784414e64 --- /dev/null +++ b/queue-5.10/i40e-fix-potential-memory-leaks-in-i40e_remove.patch @@ -0,0 +1,50 @@ +From ba953cc21f2a4e8d3e12b005f287a61aa672ac66 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Sep 2023 14:42:01 +0200 +Subject: i40e: fix potential memory leaks in i40e_remove() + +From: Andrii Staikov + +[ Upstream commit 5ca636d927a106780451d957734f02589b972e2b ] + +Instead of freeing memory of a single VSI, make sure +the memory for all VSIs is cleared before releasing VSIs. +Add releasing of their resources in a loop with the iteration +number equal to the number of allocated VSIs. + +Fixes: 41c445ff0f48 ("i40e: main driver core") +Signed-off-by: Andrii Staikov +Signed-off-by: Aleksandr Loktionov +Reviewed-by: Simon Horman +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e_main.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c +index d23a467d0d209..64e1f6f407b48 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_main.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c +@@ -15601,11 +15601,15 @@ static void i40e_remove(struct pci_dev *pdev) + i40e_switch_branch_release(pf->veb[i]); + } + +- /* Now we can shutdown the PF's VSI, just before we kill ++ /* Now we can shutdown the PF's VSIs, just before we kill + * adminq and hmc. + */ +- if (pf->vsi[pf->lan_vsi]) +- i40e_vsi_release(pf->vsi[pf->lan_vsi]); ++ for (i = pf->num_alloc_vsi; i--;) ++ if (pf->vsi[i]) { ++ i40e_vsi_close(pf->vsi[i]); ++ i40e_vsi_release(pf->vsi[i]); ++ pf->vsi[i] = NULL; ++ } + + i40e_cloud_filter_exit(pf); + +-- +2.42.0 + diff --git a/queue-5.10/ib-mlx5-fix-rdma-counter-binding-for-raw-qp.patch b/queue-5.10/ib-mlx5-fix-rdma-counter-binding-for-raw-qp.patch new file mode 100644 index 00000000000..6f691529071 --- /dev/null +++ b/queue-5.10/ib-mlx5-fix-rdma-counter-binding-for-raw-qp.patch @@ -0,0 +1,76 @@ +From c50d94f7c8dc9af590ecddb408c53975a33a19bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 9 Oct 2023 13:41:20 +0300 +Subject: IB/mlx5: Fix rdma counter binding for RAW QP + +From: Patrisious Haddad + +[ Upstream commit c1336bb4aa5e809a622a87d74311275514086596 ] + +Previously when we had a RAW QP, we bound a counter to it when it moved +to INIT state, using the counter context inside RQC. + +But when we try to modify that counter later in RTS state we used +modify QP which tries to change the counter inside QPC instead of RQC. + +Now we correctly modify the counter set_id inside of RQC instead of QPC +for the RAW QP. + +Fixes: d14133dd4161 ("IB/mlx5: Support set qp counter") +Signed-off-by: Patrisious Haddad +Reviewed-by: Mark Zhang +Link: https://lore.kernel.org/r/2e5ab6713784a8fe997d19c508187a0dfecf2dfc.1696847964.git.leon@kernel.org +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/hw/mlx5/qp.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c +index 0c47e3e24b2a4..e3cc856e70e5d 100644 +--- a/drivers/infiniband/hw/mlx5/qp.c ++++ b/drivers/infiniband/hw/mlx5/qp.c +@@ -3714,6 +3714,30 @@ static unsigned int get_tx_affinity(struct ib_qp *qp, + return tx_affinity; + } + ++static int __mlx5_ib_qp_set_raw_qp_counter(struct mlx5_ib_qp *qp, u32 set_id, ++ struct mlx5_core_dev *mdev) ++{ ++ struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; ++ struct mlx5_ib_rq *rq = &raw_packet_qp->rq; ++ u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {}; ++ void *rqc; ++ ++ if (!qp->rq.wqe_cnt) ++ return 0; ++ ++ MLX5_SET(modify_rq_in, in, rq_state, rq->state); ++ MLX5_SET(modify_rq_in, in, uid, to_mpd(qp->ibqp.pd)->uid); ++ ++ rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); ++ MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); ++ ++ MLX5_SET64(modify_rq_in, in, modify_bitmask, ++ MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); ++ MLX5_SET(rqc, rqc, counter_set_id, set_id); ++ ++ return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in); ++} ++ + static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, + struct rdma_counter *counter) + { +@@ -3729,6 +3753,9 @@ static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, + else + set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); + ++ if (mqp->type == IB_QPT_RAW_PACKET) ++ return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev); ++ + base = &mqp->trans_qp.base; + MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); + MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); +-- +2.42.0 + diff --git a/queue-5.10/interconnect-qcom-osm-l3-replace-custom-implementati.patch b/queue-5.10/interconnect-qcom-osm-l3-replace-custom-implementati.patch new file mode 100644 index 00000000000..09d186967b8 --- /dev/null +++ b/queue-5.10/interconnect-qcom-osm-l3-replace-custom-implementati.patch @@ -0,0 +1,45 @@ +From 90a5b29a481739bfc3122204a99938738ab5927c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Sep 2023 18:49:27 +0300 +Subject: interconnect: qcom: osm-l3: Replace custom implementation of + COUNT_ARGS() + +From: Andy Shevchenko + +[ Upstream commit 577a3c5af1fe87b65931ea94d5515266da301f56 ] + +Replace custom and non-portable implementation of COUNT_ARGS(). + +Fixes: 5bc9900addaf ("interconnect: qcom: Add OSM L3 interconnect provider support") +Signed-off-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20230920154927.2090732-1-andriy.shevchenko@linux.intel.com +Signed-off-by: Georgi Djakov +Signed-off-by: Sasha Levin +--- + drivers/interconnect/qcom/osm-l3.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c +index 08a282d573203..f7407b930d23c 100644 +--- a/drivers/interconnect/qcom/osm-l3.c ++++ b/drivers/interconnect/qcom/osm-l3.c +@@ -3,6 +3,7 @@ + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + ++#include + #include + #include + #include +@@ -77,7 +78,7 @@ struct qcom_icc_desc { + .name = #_name, \ + .id = _id, \ + .buswidth = _buswidth, \ +- .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ ++ .num_links = COUNT_ARGS(__VA_ARGS__), \ + .links = { __VA_ARGS__ }, \ + } + +-- +2.42.0 + diff --git a/queue-5.10/interconnect-qcom-sc7180-retire-define_qbcm.patch b/queue-5.10/interconnect-qcom-sc7180-retire-define_qbcm.patch new file mode 100644 index 00000000000..9dbbd285764 --- /dev/null +++ b/queue-5.10/interconnect-qcom-sc7180-retire-define_qbcm.patch @@ -0,0 +1,290 @@ +From 154b25bf92203e7fbe569990530fae52579c11ac Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 11 Aug 2023 14:15:22 +0200 +Subject: interconnect: qcom: sc7180: Retire DEFINE_QBCM + +From: Konrad Dybcio + +[ Upstream commit e451b2ea5a11fb3f6d83e1f834ae6a5f55a02bba ] + +The struct definition macros are hard to read and compare, expand them. + +Signed-off-by: Konrad Dybcio +Reviewed-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-11-c03aaeffc769@linaro.org +Signed-off-by: Georgi Djakov +Stable-dep-of: 1ad83c479272 ("interconnect: qcom: sc7180: Set ACV enable_mask") +Signed-off-by: Sasha Levin +--- + drivers/interconnect/qcom/sc7180.c | 255 ++++++++++++++++++++++++++--- + 1 file changed, 231 insertions(+), 24 deletions(-) + +diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c +index 597a7ee7a9bbf..c179cbb1f1d28 100644 +--- a/drivers/interconnect/qcom/sc7180.c ++++ b/drivers/interconnect/qcom/sc7180.c +@@ -153,30 +153,237 @@ DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4); + DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4); + DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8); + +-DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); +-DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); +-DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); +-DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); +-DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); +-DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); +-DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9); +-DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); +-DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); +-DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2); +-DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); +-DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0); +-DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); +-DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); +-DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); +-DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2); +-DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc); +-DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); +-DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); +-DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); +-DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); +-DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); +-DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc); +-DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc); ++static struct qcom_icc_bcm bcm_acv = { ++ .name = "ACV", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &ebi }, ++}; ++ ++static struct qcom_icc_bcm bcm_mc0 = { ++ .name = "MC0", ++ .keepalive = true, ++ .num_nodes = 1, ++ .nodes = { &ebi }, ++}; ++ ++static struct qcom_icc_bcm bcm_sh0 = { ++ .name = "SH0", ++ .keepalive = true, ++ .num_nodes = 1, ++ .nodes = { &qns_llcc }, ++}; ++ ++static struct qcom_icc_bcm bcm_mm0 = { ++ .name = "MM0", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qns_mem_noc_hf }, ++}; ++ ++static struct qcom_icc_bcm bcm_ce0 = { ++ .name = "CE0", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qxm_crypto }, ++}; ++ ++static struct qcom_icc_bcm bcm_cn0 = { ++ .name = "CN0", ++ .keepalive = true, ++ .num_nodes = 48, ++ .nodes = { &qnm_snoc, ++ &xm_qdss_dap, ++ &qhs_a1_noc_cfg, ++ &qhs_a2_noc_cfg, ++ &qhs_ahb2phy0, ++ &qhs_aop, ++ &qhs_aoss, ++ &qhs_boot_rom, ++ &qhs_camera_cfg, ++ &qhs_camera_nrt_throttle_cfg, ++ &qhs_camera_rt_throttle_cfg, ++ &qhs_clk_ctl, ++ &qhs_cpr_cx, ++ &qhs_cpr_mx, ++ &qhs_crypto0_cfg, ++ &qhs_dcc_cfg, ++ &qhs_ddrss_cfg, ++ &qhs_display_cfg, ++ &qhs_display_rt_throttle_cfg, ++ &qhs_display_throttle_cfg, ++ &qhs_glm, ++ &qhs_gpuss_cfg, ++ &qhs_imem_cfg, ++ &qhs_ipa, ++ &qhs_mnoc_cfg, ++ &qhs_mss_cfg, ++ &qhs_npu_cfg, ++ &qhs_npu_dma_throttle_cfg, ++ &qhs_npu_dsp_throttle_cfg, ++ &qhs_pimem_cfg, ++ &qhs_prng, ++ &qhs_qdss_cfg, ++ &qhs_qm_cfg, ++ &qhs_qm_mpu_cfg, ++ &qhs_qup0, ++ &qhs_qup1, ++ &qhs_security, ++ &qhs_snoc_cfg, ++ &qhs_tcsr, ++ &qhs_tlmm_1, ++ &qhs_tlmm_2, ++ &qhs_tlmm_3, ++ &qhs_ufs_mem_cfg, ++ &qhs_usb3, ++ &qhs_venus_cfg, ++ &qhs_venus_throttle_cfg, ++ &qhs_vsense_ctrl_cfg, ++ &srvc_cnoc ++ }, ++}; ++ ++static struct qcom_icc_bcm bcm_mm1 = { ++ .name = "MM1", ++ .keepalive = false, ++ .num_nodes = 8, ++ .nodes = { &qxm_camnoc_hf0_uncomp, ++ &qxm_camnoc_hf1_uncomp, ++ &qxm_camnoc_sf_uncomp, ++ &qhm_mnoc_cfg, ++ &qxm_mdp0, ++ &qxm_rot, ++ &qxm_venus0, ++ &qxm_venus_arm9 ++ }, ++}; ++ ++static struct qcom_icc_bcm bcm_sh2 = { ++ .name = "SH2", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &acm_sys_tcu }, ++}; ++ ++static struct qcom_icc_bcm bcm_mm2 = { ++ .name = "MM2", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qns_mem_noc_sf }, ++}; ++ ++static struct qcom_icc_bcm bcm_qup0 = { ++ .name = "QUP0", ++ .keepalive = false, ++ .num_nodes = 2, ++ .nodes = { &qup_core_master_1, &qup_core_master_2 }, ++}; ++ ++static struct qcom_icc_bcm bcm_sh3 = { ++ .name = "SH3", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qnm_cmpnoc }, ++}; ++ ++static struct qcom_icc_bcm bcm_sh4 = { ++ .name = "SH4", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &acm_apps0 }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn0 = { ++ .name = "SN0", ++ .keepalive = true, ++ .num_nodes = 1, ++ .nodes = { &qns_gemnoc_sf }, ++}; ++ ++static struct qcom_icc_bcm bcm_co0 = { ++ .name = "CO0", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qns_cdsp_gemnoc }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn1 = { ++ .name = "SN1", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qxs_imem }, ++}; ++ ++static struct qcom_icc_bcm bcm_cn1 = { ++ .name = "CN1", ++ .keepalive = false, ++ .num_nodes = 8, ++ .nodes = { &qhm_qspi, ++ &xm_sdc2, ++ &xm_emmc, ++ &qhs_ahb2phy2, ++ &qhs_emmc_cfg, ++ &qhs_pdm, ++ &qhs_qspi, ++ &qhs_sdc2 ++ }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn2 = { ++ .name = "SN2", ++ .keepalive = false, ++ .num_nodes = 2, ++ .nodes = { &qxm_pimem, &qns_gemnoc_gc }, ++}; ++ ++static struct qcom_icc_bcm bcm_co2 = { ++ .name = "CO2", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qnm_npu }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn3 = { ++ .name = "SN3", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qxs_pimem }, ++}; ++ ++static struct qcom_icc_bcm bcm_co3 = { ++ .name = "CO3", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qxm_npu_dsp }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn4 = { ++ .name = "SN4", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &xs_qdss_stm }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn7 = { ++ .name = "SN7", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qnm_aggre1_noc }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn9 = { ++ .name = "SN9", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qnm_aggre2_noc }, ++}; ++ ++static struct qcom_icc_bcm bcm_sn12 = { ++ .name = "SN12", ++ .keepalive = false, ++ .num_nodes = 1, ++ .nodes = { &qnm_gemnoc }, ++}; + + static struct qcom_icc_bcm *aggre1_noc_bcms[] = { + &bcm_cn1, +-- +2.42.0 + diff --git a/queue-5.10/interconnect-qcom-sc7180-set-acv-enable_mask.patch b/queue-5.10/interconnect-qcom-sc7180-set-acv-enable_mask.patch new file mode 100644 index 00000000000..b45f714af20 --- /dev/null +++ b/queue-5.10/interconnect-qcom-sc7180-set-acv-enable_mask.patch @@ -0,0 +1,35 @@ +From 3769335e89c122cd907cb31c57a78a20ba44d508 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 12 Aug 2023 01:20:45 +0200 +Subject: interconnect: qcom: sc7180: Set ACV enable_mask + +From: Konrad Dybcio + +[ Upstream commit 1ad83c4792722fe134c1352591420702ff7b9091 ] + +ACV expects an enable_mask corresponding to the APPS RSC, fill it in. + +Fixes: 2d1f95ab9feb ("interconnect: qcom: Add SC7180 interconnect provider driver") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230811-topic-acv-v2-2-765ad70e539a@linaro.org +Signed-off-by: Georgi Djakov +Signed-off-by: Sasha Levin +--- + drivers/interconnect/qcom/sc7180.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c +index c179cbb1f1d28..f5b3c68bb66c2 100644 +--- a/drivers/interconnect/qcom/sc7180.c ++++ b/drivers/interconnect/qcom/sc7180.c +@@ -155,6 +155,7 @@ DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8); + + static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", ++ .enable_mask = BIT(3), + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +-- +2.42.0 + diff --git a/queue-5.10/iov_iter-x86-be-consistent-about-the-__user-tag-on-c.patch b/queue-5.10/iov_iter-x86-be-consistent-about-the-__user-tag-on-c.patch new file mode 100644 index 00000000000..d61211b5d20 --- /dev/null +++ b/queue-5.10/iov_iter-x86-be-consistent-about-the-__user-tag-on-c.patch @@ -0,0 +1,90 @@ +From 12e078f2330e1a1cb44e1c60e24759b704fefe98 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 25 Sep 2023 13:02:59 +0100 +Subject: iov_iter, x86: Be consistent about the __user tag on + copy_mc_to_user() + +From: David Howells + +[ Upstream commit 066baf92bed934c9fb4bcee97a193f47aa63431c ] + +copy_mc_to_user() has the destination marked __user on powerpc, but not on +x86; the latter results in a sparse warning in lib/iov_iter.c. + +Fix this by applying the tag on x86 too. + +Fixes: ec6347bb4339 ("x86, powerpc: Rename memcpy_mcsafe() to copy_mc_to_{user, kernel}()") +Signed-off-by: David Howells +Link: https://lore.kernel.org/r/20230925120309.1731676-3-dhowells@redhat.com +cc: Dan Williams +cc: Thomas Gleixner +cc: Ingo Molnar +cc: Borislav Petkov +cc: Dave Hansen +cc: "H. Peter Anvin" +cc: Alexander Viro +cc: Jens Axboe +cc: Christoph Hellwig +cc: Christian Brauner +cc: Matthew Wilcox +cc: Linus Torvalds +cc: David Laight +cc: x86@kernel.org +cc: linux-block@vger.kernel.org +cc: linux-fsdevel@vger.kernel.org +cc: linux-mm@kvack.org +Signed-off-by: Christian Brauner +Signed-off-by: Sasha Levin +--- + arch/x86/include/asm/uaccess.h | 2 +- + arch/x86/lib/copy_mc.c | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h +index bb1430283c726..bf2561a5eb581 100644 +--- a/arch/x86/include/asm/uaccess.h ++++ b/arch/x86/include/asm/uaccess.h +@@ -446,7 +446,7 @@ copy_mc_to_kernel(void *to, const void *from, unsigned len); + #define copy_mc_to_kernel copy_mc_to_kernel + + unsigned long __must_check +-copy_mc_to_user(void *to, const void *from, unsigned len); ++copy_mc_to_user(void __user *to, const void *from, unsigned len); + #endif + + /* +diff --git a/arch/x86/lib/copy_mc.c b/arch/x86/lib/copy_mc.c +index c13e8c9ee926b..e058ef2d454d0 100644 +--- a/arch/x86/lib/copy_mc.c ++++ b/arch/x86/lib/copy_mc.c +@@ -74,23 +74,23 @@ unsigned long __must_check copy_mc_to_kernel(void *dst, const void *src, unsigne + } + EXPORT_SYMBOL_GPL(copy_mc_to_kernel); + +-unsigned long __must_check copy_mc_to_user(void *dst, const void *src, unsigned len) ++unsigned long __must_check copy_mc_to_user(void __user *dst, const void *src, unsigned len) + { + unsigned long ret; + + if (copy_mc_fragile_enabled) { + __uaccess_begin(); +- ret = copy_mc_fragile(dst, src, len); ++ ret = copy_mc_fragile((__force void *)dst, src, len); + __uaccess_end(); + return ret; + } + + if (static_cpu_has(X86_FEATURE_ERMS)) { + __uaccess_begin(); +- ret = copy_mc_enhanced_fast_string(dst, src, len); ++ ret = copy_mc_enhanced_fast_string((__force void *)dst, src, len); + __uaccess_end(); + return ret; + } + +- return copy_user_generic(dst, src, len); ++ return copy_user_generic((__force void *)dst, src, len); + } +-- +2.42.0 + diff --git a/queue-5.10/ipv6-avoid-atomic-fragment-on-gso-packets.patch b/queue-5.10/ipv6-avoid-atomic-fragment-on-gso-packets.patch new file mode 100644 index 00000000000..65830c5ba8b --- /dev/null +++ b/queue-5.10/ipv6-avoid-atomic-fragment-on-gso-packets.patch @@ -0,0 +1,54 @@ +From 5f3d496b11090ce3e44a91aa71c046fb5e971fbc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 24 Oct 2023 07:26:40 -0700 +Subject: ipv6: avoid atomic fragment on GSO packets + +From: Yan Zhai + +[ Upstream commit 03d6c848bfb406e9ef6d9846d759e97beaeea113 ] + +When the ipv6 stack output a GSO packet, if its gso_size is larger than +dst MTU, then all segments would be fragmented. However, it is possible +for a GSO packet to have a trailing segment with smaller actual size +than both gso_size as well as the MTU, which leads to an "atomic +fragment". Atomic fragments are considered harmful in RFC-8021. An +Existing report from APNIC also shows that atomic fragments are more +likely to be dropped even it is equivalent to a no-op [1]. + +Add an extra check in the GSO slow output path. For each segment from +the original over-sized packet, if it fits with the path MTU, then avoid +generating an atomic fragment. + +Link: https://www.potaroo.net/presentations/2022-03-01-ipv6-frag.pdf [1] +Fixes: b210de4f8c97 ("net: ipv6: Validate GSO SKB before finish IPv6 processing") +Reported-by: David Wragg +Signed-off-by: Yan Zhai +Link: https://lore.kernel.org/r/90912e3503a242dca0bc36958b11ed03a2696e5e.1698156966.git.yan@cloudflare.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + net/ipv6/ip6_output.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c +index 58b5ab5fcdbf1..4126be15e0d9b 100644 +--- a/net/ipv6/ip6_output.c ++++ b/net/ipv6/ip6_output.c +@@ -178,7 +178,13 @@ ip6_finish_output_gso_slowpath_drop(struct net *net, struct sock *sk, + int err; + + skb_mark_not_on_list(segs); +- err = ip6_fragment(net, sk, segs, ip6_finish_output2); ++ /* Last GSO segment can be smaller than gso_size (and MTU). ++ * Adding a fragment header would produce an "atomic fragment", ++ * which is considered harmful (RFC-8021). Avoid that. ++ */ ++ err = segs->len > mtu ? ++ ip6_fragment(net, sk, segs, ip6_finish_output2) : ++ ip6_finish_output2(net, sk, segs); + if (err && ret == 0) + ret = err; + } +-- +2.42.0 + diff --git a/queue-5.10/ipvlan-properly-track-tx_errors.patch b/queue-5.10/ipvlan-properly-track-tx_errors.patch new file mode 100644 index 00000000000..1c836d32add --- /dev/null +++ b/queue-5.10/ipvlan-properly-track-tx_errors.patch @@ -0,0 +1,81 @@ +From 2351539749227c71f342aab791c5d7ae718070ac Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 26 Oct 2023 13:14:46 +0000 +Subject: ipvlan: properly track tx_errors + +From: Eric Dumazet + +[ Upstream commit ff672b9ffeb3f82135488ac16c5c5eb4b992999b ] + +Both ipvlan_process_v4_outbound() and ipvlan_process_v6_outbound() +increment dev->stats.tx_errors in case of errors. + +Unfortunately there are two issues : + +1) ipvlan_get_stats64() does not propagate dev->stats.tx_errors to user. + +2) Increments are not atomic. KCSAN would complain eventually. + +Use DEV_STATS_INC() to not miss an update, and change ipvlan_get_stats64() +to copy the value back to user. + +Fixes: 2ad7bf363841 ("ipvlan: Initial check-in of the IPVLAN driver.") +Signed-off-by: Eric Dumazet +Cc: Mahesh Bandewar +Link: https://lore.kernel.org/r/20231026131446.3933175-1-edumazet@google.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ipvlan/ipvlan_core.c | 8 ++++---- + drivers/net/ipvlan/ipvlan_main.c | 1 + + 2 files changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c +index ab09d110760ec..b5a61b16a7eab 100644 +--- a/drivers/net/ipvlan/ipvlan_core.c ++++ b/drivers/net/ipvlan/ipvlan_core.c +@@ -442,12 +442,12 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) + + err = ip_local_out(net, skb->sk, skb); + if (unlikely(net_xmit_eval(err))) +- dev->stats.tx_errors++; ++ DEV_STATS_INC(dev, tx_errors); + else + ret = NET_XMIT_SUCCESS; + goto out; + err: +- dev->stats.tx_errors++; ++ DEV_STATS_INC(dev, tx_errors); + kfree_skb(skb); + out: + return ret; +@@ -483,12 +483,12 @@ static int ipvlan_process_v6_outbound(struct sk_buff *skb) + + err = ip6_local_out(net, skb->sk, skb); + if (unlikely(net_xmit_eval(err))) +- dev->stats.tx_errors++; ++ DEV_STATS_INC(dev, tx_errors); + else + ret = NET_XMIT_SUCCESS; + goto out; + err: +- dev->stats.tx_errors++; ++ DEV_STATS_INC(dev, tx_errors); + kfree_skb(skb); + out: + return ret; +diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c +index 93be7dd571fc5..f59ef2e2a614b 100644 +--- a/drivers/net/ipvlan/ipvlan_main.c ++++ b/drivers/net/ipvlan/ipvlan_main.c +@@ -322,6 +322,7 @@ static void ipvlan_get_stats64(struct net_device *dev, + s->rx_dropped = rx_errs; + s->tx_dropped = tx_drps; + } ++ s->tx_errors = DEV_STATS_READ(dev, tx_errors); + } + + static int ipvlan_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) +-- +2.42.0 + diff --git a/queue-5.10/leds-pwm-don-t-disable-the-pwm-when-the-led-should-b.patch b/queue-5.10/leds-pwm-don-t-disable-the-pwm-when-the-led-should-b.patch new file mode 100644 index 00000000000..e80fe64284f --- /dev/null +++ b/queue-5.10/leds-pwm-don-t-disable-the-pwm-when-the-led-should-b.patch @@ -0,0 +1,53 @@ +From be104f75975fdfa77cee8dca700f5157c4fd71b0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Sep 2023 21:28:34 +0200 +Subject: leds: pwm: Don't disable the PWM when the LED should be off +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit 76fe464c8e64e71b2e4af11edeef0e5d85eeb6aa ] + +Disabling a PWM (i.e. calling pwm_apply_state with .enabled = false) +gives no guarantees what the PWM output does. It might freeze where it +currently is, or go in a High-Z state or drive the active or inactive +state, it might even continue to toggle. + +To ensure that the LED gets really disabled, don't disable the PWM even +when .duty_cycle is zero. + +This fixes disabling a leds-pwm LED on i.MX28. The PWM on this SoC is +one of those that freezes its output on disable, so if you disable an +LED that is full on, it stays on. If you disable a LED with half +brightness it goes off in 50% of the cases and full on in the other 50%. + +Fixes: 41c42ff5dbe2 ("leds: simple driver for pwm driven LEDs") +Reported-by: Rogan Dawes +Reported-by: Fabio Estevam +Signed-off-by: Uwe Kleine-König +Reviewed-by: Fabio Estevam +Link: https://lore.kernel.org/r/20230922192834.1695727-1-u.kleine-koenig@pengutronix.de +Signed-off-by: Lee Jones +Signed-off-by: Sasha Levin +--- + drivers/leds/leds-pwm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c +index f53f9309ca6cc..f4c0507becb31 100644 +--- a/drivers/leds/leds-pwm.c ++++ b/drivers/leds/leds-pwm.c +@@ -51,7 +51,7 @@ static int led_pwm_set(struct led_classdev *led_cdev, + duty = led_dat->pwmstate.period - duty; + + led_dat->pwmstate.duty_cycle = duty; +- led_dat->pwmstate.enabled = duty > 0; ++ led_dat->pwmstate.enabled = true; + return pwm_apply_state(led_dat->pwm, &led_dat->pwmstate); + } + +-- +2.42.0 + diff --git a/queue-5.10/leds-trigger-ledtrig-cpu-fix-output-may-be-truncated.patch b/queue-5.10/leds-trigger-ledtrig-cpu-fix-output-may-be-truncated.patch new file mode 100644 index 00000000000..c10447ad4e6 --- /dev/null +++ b/queue-5.10/leds-trigger-ledtrig-cpu-fix-output-may-be-truncated.patch @@ -0,0 +1,63 @@ +From c72923be101c72fcab1b6290b5fd3046d888c245 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 23 Sep 2023 09:15:38 +0200 +Subject: leds: trigger: ledtrig-cpu:: Fix 'output may be truncated' issue for + 'cpu' +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christophe JAILLET + +[ Upstream commit ff50f53276131a3059e8307d11293af388ed2bcd ] + +In order to teach the compiler that 'trig->name' will never be truncated, +we need to tell it that 'cpu' is not negative. + +When building with W=1, this fixes the following warnings: + + drivers/leds/trigger/ledtrig-cpu.c: In function ‘ledtrig_cpu_init’: + drivers/leds/trigger/ledtrig-cpu.c:155:56: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 5 [-Werror=format-truncation=] + 155 | snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); + | ^~ + drivers/leds/trigger/ledtrig-cpu.c:155:52: note: directive argument in the range [-2147483648, 7] + 155 | snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); + | ^~~~~~~ + drivers/leds/trigger/ledtrig-cpu.c:155:17: note: ‘snprintf’ output between 5 and 15 bytes into a destination of size 8 + 155 | snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Fixes: 8f88731d052d ("led-triggers: create a trigger for CPU activity") +Signed-off-by: Christophe JAILLET +Link: https://lore.kernel.org/r/3f4be7a99933cf8566e630da54f6ab913caac432.1695453322.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Lee Jones +Signed-off-by: Sasha Levin +--- + drivers/leds/trigger/ledtrig-cpu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c +index fca62d5035909..f19baed615023 100644 +--- a/drivers/leds/trigger/ledtrig-cpu.c ++++ b/drivers/leds/trigger/ledtrig-cpu.c +@@ -130,7 +130,7 @@ static int ledtrig_prepare_down_cpu(unsigned int cpu) + + static int __init ledtrig_cpu_init(void) + { +- int cpu; ++ unsigned int cpu; + int ret; + + /* Supports up to 9999 cpu cores */ +@@ -152,7 +152,7 @@ static int __init ledtrig_cpu_init(void) + if (cpu >= 8) + continue; + +- snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); ++ snprintf(trig->name, MAX_NAME_LEN, "cpu%u", cpu); + + led_trigger_register_simple(trig->name, &trig->_trig); + } +-- +2.42.0 + diff --git a/queue-5.10/libnvdimm-of_pmem-use-devm_kstrdup-instead-of-kstrdu.patch b/queue-5.10/libnvdimm-of_pmem-use-devm_kstrdup-instead-of-kstrdu.patch new file mode 100644 index 00000000000..7b416f70e05 --- /dev/null +++ b/queue-5.10/libnvdimm-of_pmem-use-devm_kstrdup-instead-of-kstrdu.patch @@ -0,0 +1,45 @@ +From 834144b0240e1bd1ec773fd2450883b6cb1f4220 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Sep 2023 07:03:27 +0000 +Subject: libnvdimm/of_pmem: Use devm_kstrdup instead of kstrdup and check its + return value + +From: Chen Ni + +[ Upstream commit 6fd4ebfc4d61e3097b595ab2725d513e3bbd6739 ] + +Use devm_kstrdup() instead of kstrdup() and check its return value to +avoid memory leak. + +Fixes: 49bddc73d15c ("libnvdimm/of_pmem: Provide a unique name for bus provider") +Signed-off-by: Chen Ni +Reviewed-by: Ira Weiny +Reviewed-by: Dave Jiang +Signed-off-by: Ira Weiny +Signed-off-by: Sasha Levin +--- + drivers/nvdimm/of_pmem.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/nvdimm/of_pmem.c b/drivers/nvdimm/of_pmem.c +index 10dbdcdfb9ce9..0243789ba914b 100644 +--- a/drivers/nvdimm/of_pmem.c ++++ b/drivers/nvdimm/of_pmem.c +@@ -30,7 +30,13 @@ static int of_pmem_region_probe(struct platform_device *pdev) + if (!priv) + return -ENOMEM; + +- priv->bus_desc.provider_name = kstrdup(pdev->name, GFP_KERNEL); ++ priv->bus_desc.provider_name = devm_kstrdup(&pdev->dev, pdev->name, ++ GFP_KERNEL); ++ if (!priv->bus_desc.provider_name) { ++ kfree(priv); ++ return -ENOMEM; ++ } ++ + priv->bus_desc.module = THIS_MODULE; + priv->bus_desc.of_node = np; + +-- +2.42.0 + diff --git a/queue-5.10/livepatch-fix-missing-newline-character-in-klp_resol.patch b/queue-5.10/livepatch-fix-missing-newline-character-in-klp_resol.patch new file mode 100644 index 00000000000..0f55fae733b --- /dev/null +++ b/queue-5.10/livepatch-fix-missing-newline-character-in-klp_resol.patch @@ -0,0 +1,38 @@ +From 97a68c25b7bbe82541cc86b3881e77d830e3fe76 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Sep 2023 15:26:44 +0800 +Subject: livepatch: Fix missing newline character in klp_resolve_symbols() + +From: Zheng Yejian + +[ Upstream commit 67e18e132f0fd738f8c8cac3aa1420312073f795 ] + +Without the newline character, the log may not be printed immediately +after the error occurs. + +Fixes: ca376a937486 ("livepatch: Prevent module-specific KLP rela sections from referencing vmlinux symbols") +Signed-off-by: Zheng Yejian +Reviewed-by: Petr Mladek +Signed-off-by: Petr Mladek +Link: https://lore.kernel.org/r/20230914072644.4098857-1-zhengyejian1@huawei.com +Signed-off-by: Sasha Levin +--- + kernel/livepatch/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/livepatch/core.c b/kernel/livepatch/core.c +index e8bdce6fdd647..f5faf935c2d8f 100644 +--- a/kernel/livepatch/core.c ++++ b/kernel/livepatch/core.c +@@ -245,7 +245,7 @@ static int klp_resolve_symbols(Elf_Shdr *sechdrs, const char *strtab, + * symbols are exported and normal relas can be used instead. + */ + if (!sec_vmlinux && sym_vmlinux) { +- pr_err("invalid access to vmlinux symbol '%s' from module-specific livepatch relocation section", ++ pr_err("invalid access to vmlinux symbol '%s' from module-specific livepatch relocation section\n", + sym_name); + return -EINVAL; + } +-- +2.42.0 + diff --git a/queue-5.10/media-bttv-fix-use-after-free-error-due-to-btv-timeo.patch b/queue-5.10/media-bttv-fix-use-after-free-error-due-to-btv-timeo.patch new file mode 100644 index 00000000000..215ebbbd714 --- /dev/null +++ b/queue-5.10/media-bttv-fix-use-after-free-error-due-to-btv-timeo.patch @@ -0,0 +1,52 @@ +From b4b34f6ccd97e164c20b02fa60a3674353a5801e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 13 Apr 2023 11:49:42 +0800 +Subject: media: bttv: fix use after free error due to btv->timeout timer + +From: Zheng Wang + +[ Upstream commit bd5b50b329e850d467e7bcc07b2b6bde3752fbda ] + +There may be some a race condition between timer function +bttv_irq_timeout and bttv_remove. The timer is setup in +probe and there is no timer_delete operation in remove +function. When it hit kfree btv, the function might still be +invoked, which will cause use after free bug. + +This bug is found by static analysis, it may be false positive. + +Fix it by adding del_timer_sync invoking to the remove function. + +cpu0 cpu1 + bttv_probe + ->timer_setup + ->bttv_set_dma + ->mod_timer; +bttv_remove + ->kfree(btv); + ->bttv_irq_timeout + ->USE btv + +Fixes: 162e6376ac58 ("media: pci: Convert timers to use timer_setup()") +Signed-off-by: Zheng Wang +Signed-off-by: Hans Verkuil +Signed-off-by: Sasha Levin +--- + drivers/media/pci/bt8xx/bttv-driver.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/media/pci/bt8xx/bttv-driver.c b/drivers/media/pci/bt8xx/bttv-driver.c +index 1f0e4b913a053..5f1bd9b38e75f 100644 +--- a/drivers/media/pci/bt8xx/bttv-driver.c ++++ b/drivers/media/pci/bt8xx/bttv-driver.c +@@ -4258,6 +4258,7 @@ static void bttv_remove(struct pci_dev *pci_dev) + + /* free resources */ + free_irq(btv->c.pci->irq,btv); ++ del_timer_sync(&btv->timeout); + iounmap(btv->bt848_mmio); + release_mem_region(pci_resource_start(btv->c.pci,0), + pci_resource_len(btv->c.pci,0)); +-- +2.42.0 + diff --git a/queue-5.10/media-cedrus-fix-clock-reset-sequence.patch b/queue-5.10/media-cedrus-fix-clock-reset-sequence.patch new file mode 100644 index 00000000000..b12a65e66bf --- /dev/null +++ b/queue-5.10/media-cedrus-fix-clock-reset-sequence.patch @@ -0,0 +1,87 @@ +From ffcee3d78edc76b70d44d9f306973d9841d160eb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Sep 2023 20:46:12 +0200 +Subject: media: cedrus: Fix clock/reset sequence + +From: Jernej Skrabec + +[ Upstream commit 36fe515c1a3cd5eac148e8a591a82108d92d5522 ] + +According to H6 user manual, resets should always be de-asserted before +clocks are enabled. This is also consistent with vendor driver. + +Fixes: d5aecd289bab ("media: cedrus: Implement runtime PM") +Signed-off-by: Jernej Skrabec +Acked-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +Signed-off-by: Sasha Levin +--- + .../staging/media/sunxi/cedrus/cedrus_hw.c | 24 +++++++++---------- + 1 file changed, 12 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index bcf050a04ffc4..e782731f0a6a4 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -145,12 +145,12 @@ int cedrus_hw_suspend(struct device *device) + { + struct cedrus_dev *dev = dev_get_drvdata(device); + +- reset_control_assert(dev->rstc); +- + clk_disable_unprepare(dev->ram_clk); + clk_disable_unprepare(dev->mod_clk); + clk_disable_unprepare(dev->ahb_clk); + ++ reset_control_assert(dev->rstc); ++ + return 0; + } + +@@ -159,11 +159,18 @@ int cedrus_hw_resume(struct device *device) + struct cedrus_dev *dev = dev_get_drvdata(device); + int ret; + ++ ret = reset_control_reset(dev->rstc); ++ if (ret) { ++ dev_err(dev->dev, "Failed to apply reset\n"); ++ ++ return ret; ++ } ++ + ret = clk_prepare_enable(dev->ahb_clk); + if (ret) { + dev_err(dev->dev, "Failed to enable AHB clock\n"); + +- return ret; ++ goto err_rst; + } + + ret = clk_prepare_enable(dev->mod_clk); +@@ -180,21 +187,14 @@ int cedrus_hw_resume(struct device *device) + goto err_mod_clk; + } + +- ret = reset_control_reset(dev->rstc); +- if (ret) { +- dev_err(dev->dev, "Failed to apply reset\n"); +- +- goto err_ram_clk; +- } +- + return 0; + +-err_ram_clk: +- clk_disable_unprepare(dev->ram_clk); + err_mod_clk: + clk_disable_unprepare(dev->mod_clk); + err_ahb_clk: + clk_disable_unprepare(dev->ahb_clk); ++err_rst: ++ reset_control_assert(dev->rstc); + + return ret; + } +-- +2.42.0 + diff --git a/queue-5.10/media-dvb-usb-v2-af9035-fix-missing-unlock.patch b/queue-5.10/media-dvb-usb-v2-af9035-fix-missing-unlock.patch new file mode 100644 index 00000000000..4619ec81c1f --- /dev/null +++ b/queue-5.10/media-dvb-usb-v2-af9035-fix-missing-unlock.patch @@ -0,0 +1,67 @@ +From f02f3c2e5dc366f9d5b8e5cce8a56d8fc520f4b8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 6 Oct 2023 12:08:45 +0200 +Subject: media: dvb-usb-v2: af9035: fix missing unlock + +From: Hans Verkuil + +[ Upstream commit f31b2cb85f0ee165d78e1c43f6d69f82cc3b2145 ] + +Instead of returning an error, goto the mutex unlock at +the end of the function. + +Fixes smatch warning: + +drivers/media/usb/dvb-usb-v2/af9035.c:467 af9035_i2c_master_xfer() warn: inconsistent returns '&d->i2c_mutex'. + Locked on : 326,387 + Unlocked on: 465,467 + +Signed-off-by: Hans Verkuil +Fixes: 7bf744f2de0a ("media: dvb-usb-v2: af9035: Fix null-ptr-deref in af9035_i2c_master_xfer") +Signed-off-by: Hans Verkuil +Signed-off-by: Sasha Levin +--- + drivers/media/usb/dvb-usb-v2/af9035.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c +index 8cbaab9a60844..f0bc3e060ab8d 100644 +--- a/drivers/media/usb/dvb-usb-v2/af9035.c ++++ b/drivers/media/usb/dvb-usb-v2/af9035.c +@@ -322,8 +322,10 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, + ret = -EOPNOTSUPP; + } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || + (msg[0].addr == state->af9033_i2c_addr[1])) { +- if (msg[0].len < 3 || msg[1].len < 1) +- return -EOPNOTSUPP; ++ if (msg[0].len < 3 || msg[1].len < 1) { ++ ret = -EOPNOTSUPP; ++ goto unlock; ++ } + /* demod access via firmware interface */ + reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | + msg[0].buf[2]; +@@ -383,8 +385,10 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, + ret = -EOPNOTSUPP; + } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || + (msg[0].addr == state->af9033_i2c_addr[1])) { +- if (msg[0].len < 3) +- return -EOPNOTSUPP; ++ if (msg[0].len < 3) { ++ ret = -EOPNOTSUPP; ++ goto unlock; ++ } + /* demod access via firmware interface */ + reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | + msg[0].buf[2]; +@@ -459,6 +463,7 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, + ret = -EOPNOTSUPP; + } + ++unlock: + mutex_unlock(&d->i2c_mutex); + + if (ret < 0) +-- +2.42.0 + diff --git a/queue-5.10/media-i2c-max9286-fix-some-redundant-of_node_put-cal.patch b/queue-5.10/media-i2c-max9286-fix-some-redundant-of_node_put-cal.patch new file mode 100644 index 00000000000..dd32a4371fd --- /dev/null +++ b/queue-5.10/media-i2c-max9286-fix-some-redundant-of_node_put-cal.patch @@ -0,0 +1,50 @@ +From 501247976bf8c5de21af72d58c6c08848a84fb9d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 26 Aug 2023 00:13:40 +0200 +Subject: media: i2c: max9286: Fix some redundant of_node_put() calls + +From: Christophe JAILLET + +[ Upstream commit 0822315e46b400f611cba1193456ee6a5dc3e41d ] + +This is odd to have a of_node_put() just after a for_each_child_of_node() +or a for_each_endpoint_of_node() loop. It should already be called +during the last iteration. + +Remove these calls. + +Fixes: 66d8c9d2422d ("media: i2c: Add MAX9286 driver") +Signed-off-by: Christophe JAILLET +Reviewed-by: Jacopo Mondi +Reviewed-by: Laurent Pinchart +Reviewed-by: Kieran Bingham +Signed-off-by: Sakari Ailus +Signed-off-by: Hans Verkuil +Signed-off-by: Sasha Levin +--- + drivers/media/i2c/max9286.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/media/i2c/max9286.c b/drivers/media/i2c/max9286.c +index 62ce27552dd3c..a358eb3fe0f4d 100644 +--- a/drivers/media/i2c/max9286.c ++++ b/drivers/media/i2c/max9286.c +@@ -1143,7 +1143,6 @@ static int max9286_parse_dt(struct max9286_priv *priv) + + i2c_mux_mask |= BIT(id); + } +- of_node_put(node); + of_node_put(i2c_mux); + + /* Parse the endpoints */ +@@ -1207,7 +1206,6 @@ static int max9286_parse_dt(struct max9286_priv *priv) + priv->source_mask |= BIT(ep.port); + priv->nsources++; + } +- of_node_put(node); + + priv->route_mask = priv->source_mask; + +-- +2.42.0 + diff --git a/queue-5.10/media-s3c-camif-avoid-inappropriate-kfree.patch b/queue-5.10/media-s3c-camif-avoid-inappropriate-kfree.patch new file mode 100644 index 00000000000..11b191f69f9 --- /dev/null +++ b/queue-5.10/media-s3c-camif-avoid-inappropriate-kfree.patch @@ -0,0 +1,54 @@ +From 8283c0e701bfb9180398da275ec019c0b3a045bc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Sep 2023 14:55:06 +0300 +Subject: media: s3c-camif: Avoid inappropriate kfree() + +From: Katya Orlova + +[ Upstream commit 61334819aca018c3416ee6c330a08a49c1524fc3 ] + +s3c_camif_register_video_node() works with video_device structure stored +as a field of camif_vp, so it should not be kfreed. +But there is video_device_release() on error path that do it. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: babde1c243b2 ("[media] V4L: Add driver for S3C24XX/S3C64XX SoC series camera interface") +Signed-off-by: Katya Orlova +Signed-off-by: Hans Verkuil +Signed-off-by: Sasha Levin +--- + drivers/media/platform/s3c-camif/camif-capture.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/media/platform/s3c-camif/camif-capture.c b/drivers/media/platform/s3c-camif/camif-capture.c +index 9ca49af29542d..a3ba72a08daec 100644 +--- a/drivers/media/platform/s3c-camif/camif-capture.c ++++ b/drivers/media/platform/s3c-camif/camif-capture.c +@@ -1132,12 +1132,12 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) + + ret = vb2_queue_init(q); + if (ret) +- goto err_vd_rel; ++ return ret; + + vp->pad.flags = MEDIA_PAD_FL_SINK; + ret = media_entity_pads_init(&vfd->entity, 1, &vp->pad); + if (ret) +- goto err_vd_rel; ++ return ret; + + video_set_drvdata(vfd, vp); + +@@ -1170,8 +1170,6 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) + v4l2_ctrl_handler_free(&vp->ctrl_handler); + err_me_cleanup: + media_entity_cleanup(&vfd->entity); +-err_vd_rel: +- video_device_release(vfd); + return ret; + } + +-- +2.42.0 + diff --git a/queue-5.10/media-vidtv-mux-add-check-and-kfree-for-kstrdup.patch b/queue-5.10/media-vidtv-mux-add-check-and-kfree-for-kstrdup.patch new file mode 100644 index 00000000000..3bfc8144659 --- /dev/null +++ b/queue-5.10/media-vidtv-mux-add-check-and-kfree-for-kstrdup.patch @@ -0,0 +1,56 @@ +From c946e15017425272fc8aae068f1b61c0db14d2f8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Jun 2023 16:12:02 +0800 +Subject: media: vidtv: mux: Add check and kfree for kstrdup + +From: Jiasheng Jiang + +[ Upstream commit 1fd6eb12642e0c32692924ff359c07de4b781d78 ] + +Add check for the return value of kstrdup() and return the error +if it fails in order to avoid NULL pointer dereference. +Moreover, use kfree() in the later error handling in order to avoid +memory leak. + +Fixes: c2f78f0cb294 ("media: vidtv: psi: add a Network Information Table (NIT)") +Signed-off-by: Jiasheng Jiang +Signed-off-by: Hans Verkuil +Signed-off-by: Sasha Levin +--- + drivers/media/test-drivers/vidtv/vidtv_mux.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/media/test-drivers/vidtv/vidtv_mux.c b/drivers/media/test-drivers/vidtv/vidtv_mux.c +index b51e6a3b8cbeb..f99878eff7ace 100644 +--- a/drivers/media/test-drivers/vidtv/vidtv_mux.c ++++ b/drivers/media/test-drivers/vidtv/vidtv_mux.c +@@ -504,13 +504,16 @@ struct vidtv_mux *vidtv_mux_init(struct dvb_frontend *fe, + m->priv = args->priv; + m->network_id = args->network_id; + m->network_name = kstrdup(args->network_name, GFP_KERNEL); ++ if (!m->network_name) ++ goto free_mux_buf; ++ + m->timing.current_jiffies = get_jiffies_64(); + + if (args->channels) + m->channels = args->channels; + else + if (vidtv_channels_init(m) < 0) +- goto free_mux_buf; ++ goto free_mux_network_name; + + /* will alloc data for pmt_sections after initializing pat */ + if (vidtv_channel_si_init(m) < 0) +@@ -527,6 +530,8 @@ struct vidtv_mux *vidtv_mux_init(struct dvb_frontend *fe, + vidtv_channel_si_destroy(m); + free_channels: + vidtv_channels_destroy(m); ++free_mux_network_name: ++ kfree(m->network_name); + free_mux_buf: + vfree(m->mux_buf); + free_mux: +-- +2.42.0 + diff --git a/queue-5.10/media-vidtv-psi-add-check-for-kstrdup.patch b/queue-5.10/media-vidtv-psi-add-check-for-kstrdup.patch new file mode 100644 index 00000000000..092b0460eb7 --- /dev/null +++ b/queue-5.10/media-vidtv-psi-add-check-for-kstrdup.patch @@ -0,0 +1,111 @@ +From 4907640434d2dfde30daa3fb055e255f16e8e6ec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Jun 2023 16:12:01 +0800 +Subject: media: vidtv: psi: Add check for kstrdup + +From: Jiasheng Jiang + +[ Upstream commit 76a2c5df6ca8bd8ada45e953b8c72b746f42918d ] + +Add check for the return value of kstrdup() and return the error +if it fails in order to avoid NULL pointer dereference. + +Fixes: 7a7899f6f58e ("media: vidtv: psi: Implement an Event Information Table (EIT)") +Fixes: c2f78f0cb294 ("media: vidtv: psi: add a Network Information Table (NIT)") +Fixes: f90cf6079bf6 ("media: vidtv: add a bridge driver") +Signed-off-by: Jiasheng Jiang +Signed-off-by: Hans Verkuil +Signed-off-by: Sasha Levin +--- + drivers/media/test-drivers/vidtv/vidtv_psi.c | 45 +++++++++++++++++--- + 1 file changed, 40 insertions(+), 5 deletions(-) + +diff --git a/drivers/media/test-drivers/vidtv/vidtv_psi.c b/drivers/media/test-drivers/vidtv/vidtv_psi.c +index 1724bb485e670..1726e76f0106a 100644 +--- a/drivers/media/test-drivers/vidtv/vidtv_psi.c ++++ b/drivers/media/test-drivers/vidtv/vidtv_psi.c +@@ -308,16 +308,29 @@ struct vidtv_psi_desc_service *vidtv_psi_service_desc_init(struct vidtv_psi_desc + + desc->service_name_len = service_name_len; + +- if (service_name && service_name_len) ++ if (service_name && service_name_len) { + desc->service_name = kstrdup(service_name, GFP_KERNEL); ++ if (!desc->service_name) ++ goto free_desc; ++ } + + desc->provider_name_len = provider_name_len; + +- if (provider_name && provider_name_len) ++ if (provider_name && provider_name_len) { + desc->provider_name = kstrdup(provider_name, GFP_KERNEL); ++ if (!desc->provider_name) ++ goto free_desc_service_name; ++ } + + vidtv_psi_desc_chain(head, (struct vidtv_psi_desc *)desc); + return desc; ++ ++free_desc_service_name: ++ if (service_name && service_name_len) ++ kfree(desc->service_name); ++free_desc: ++ kfree(desc); ++ return NULL; + } + + struct vidtv_psi_desc_registration +@@ -362,8 +375,13 @@ struct vidtv_psi_desc_network_name + + desc->length = network_name_len; + +- if (network_name && network_name_len) ++ if (network_name && network_name_len) { + desc->network_name = kstrdup(network_name, GFP_KERNEL); ++ if (!desc->network_name) { ++ kfree(desc); ++ return NULL; ++ } ++ } + + vidtv_psi_desc_chain(head, (struct vidtv_psi_desc *)desc); + return desc; +@@ -449,15 +467,32 @@ struct vidtv_psi_desc_short_event + iso_language_code = "eng"; + + desc->iso_language_code = kstrdup(iso_language_code, GFP_KERNEL); ++ if (!desc->iso_language_code) ++ goto free_desc; + +- if (event_name && event_name_len) ++ if (event_name && event_name_len) { + desc->event_name = kstrdup(event_name, GFP_KERNEL); ++ if (!desc->event_name) ++ goto free_desc_language_code; ++ } + +- if (text && text_len) ++ if (text && text_len) { + desc->text = kstrdup(text, GFP_KERNEL); ++ if (!desc->text) ++ goto free_desc_event_name; ++ } + + vidtv_psi_desc_chain(head, (struct vidtv_psi_desc *)desc); + return desc; ++ ++free_desc_event_name: ++ if (event_name && event_name_len) ++ kfree(desc->event_name); ++free_desc_language_code: ++ kfree(desc->iso_language_code); ++free_desc: ++ kfree(desc); ++ return NULL; + } + + struct vidtv_psi_desc *vidtv_psi_desc_clone(struct vidtv_psi_desc *desc) +-- +2.42.0 + diff --git a/queue-5.10/mfd-core-ensure-disabled-devices-are-skipped-without.patch b/queue-5.10/mfd-core-ensure-disabled-devices-are-skipped-without.patch new file mode 100644 index 00000000000..ec2c3b65300 --- /dev/null +++ b/queue-5.10/mfd-core-ensure-disabled-devices-are-skipped-without.patch @@ -0,0 +1,77 @@ +From 8034826030caaa40c9e9796c3ce9250e1d53d1ad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 18 Aug 2023 18:39:17 +0200 +Subject: mfd: core: Ensure disabled devices are skipped without aborting + +From: Herve Codina + +[ Upstream commit 7ba7bdef4d14e3722e2842da3b48cbadb73e52d6 ] + +The loop searching for a matching device based on its compatible +string is aborted when a matching disabled device is found. +This abort prevents to add devices as soon as one disabled device +is found. + +Continue searching for an other device instead of aborting on the +first disabled one fixes the issue. + +Fixes: 22380b65dc70 ("mfd: mfd-core: Ensure disabled devices are ignored without error") +Signed-off-by: Herve Codina +Reviewed-by: Christophe Leroy +Signed-off-by: Christophe Leroy +Link: https://lore.kernel.org/r/528425d6472176bb1d02d79596b51f8c28a551cc.1692376361.git.christophe.leroy@csgroup.eu +Signed-off-by: Lee Jones +Signed-off-by: Sasha Levin +--- + drivers/mfd/mfd-core.c | 17 ++++++++++++----- + 1 file changed, 12 insertions(+), 5 deletions(-) + +diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c +index a3a6faa99de05..c0083e38d5273 100644 +--- a/drivers/mfd/mfd-core.c ++++ b/drivers/mfd/mfd-core.c +@@ -171,6 +171,7 @@ static int mfd_add_device(struct device *parent, int id, + struct platform_device *pdev; + struct device_node *np = NULL; + struct mfd_of_node_entry *of_entry, *tmp; ++ bool disabled = false; + int ret = -ENOMEM; + int platform_id; + int r; +@@ -208,11 +209,10 @@ static int mfd_add_device(struct device *parent, int id, + if (IS_ENABLED(CONFIG_OF) && parent->of_node && cell->of_compatible) { + for_each_child_of_node(parent->of_node, np) { + if (of_device_is_compatible(np, cell->of_compatible)) { +- /* Ignore 'disabled' devices error free */ ++ /* Skip 'disabled' devices */ + if (!of_device_is_available(np)) { +- of_node_put(np); +- ret = 0; +- goto fail_alias; ++ disabled = true; ++ continue; + } + + ret = mfd_match_of_node_to_dev(pdev, np, cell); +@@ -222,10 +222,17 @@ static int mfd_add_device(struct device *parent, int id, + if (ret) + goto fail_alias; + +- break; ++ goto match; + } + } + ++ if (disabled) { ++ /* Ignore 'disabled' devices error free */ ++ ret = 0; ++ goto fail_alias; ++ } ++ ++match: + if (!pdev->dev.of_node) + pr_warn("%s: Failed to locate of_node [id: %d]\n", + cell->name, platform_id); +-- +2.42.0 + diff --git a/queue-5.10/mfd-core-un-constify-mfd_cell.of_reg.patch b/queue-5.10/mfd-core-un-constify-mfd_cell.of_reg.patch new file mode 100644 index 00000000000..34b7b151306 --- /dev/null +++ b/queue-5.10/mfd-core-un-constify-mfd_cell.of_reg.patch @@ -0,0 +1,40 @@ +From 1a2ba4dbf1e72e88178d32280450fa5db4cfb946 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 28 Aug 2023 22:16:11 +0200 +Subject: mfd: core: Un-constify mfd_cell.of_reg +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michał Mirosław + +[ Upstream commit 3c70342f1f0045dc827bb2f02d814ce31e0e0d05 ] + +Enable dynamically filling in the whole mfd_cell structure. All other +fields already allow that. + +Fixes: 466a62d7642f ("mfd: core: Make a best effort attempt to match devices with the correct of_nodes") +Signed-off-by: Michał Mirosław +Link: https://lore.kernel.org/r/b73fe4bc4bd6ba1af90940a640ed65fe254c0408.1693253717.git.mirq-linux@rere.qmqm.pl +Signed-off-by: Lee Jones +Signed-off-by: Sasha Levin +--- + include/linux/mfd/core.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h +index 4b35baa14d308..8974c7142c94c 100644 +--- a/include/linux/mfd/core.h ++++ b/include/linux/mfd/core.h +@@ -92,7 +92,7 @@ struct mfd_cell { + * (above) when matching OF nodes with devices that have identical + * compatible strings + */ +- const u64 of_reg; ++ u64 of_reg; + + /* Set to 'true' to use 'of_reg' (above) - allows for of_reg=0 */ + bool use_of_reg; +-- +2.42.0 + diff --git a/queue-5.10/mfd-dln2-fix-double-put-in-dln2_probe.patch b/queue-5.10/mfd-dln2-fix-double-put-in-dln2_probe.patch new file mode 100644 index 00000000000..668e6239a34 --- /dev/null +++ b/queue-5.10/mfd-dln2-fix-double-put-in-dln2_probe.patch @@ -0,0 +1,37 @@ +From fd3c4bc316401d0820ebd990a394543f3b327b8a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 25 Sep 2023 10:41:33 +0800 +Subject: mfd: dln2: Fix double put in dln2_probe + +From: Dinghao Liu + +[ Upstream commit 759c409bc5fc496cbc22cd0b392d3cbb0c0e23eb ] + +The dln2_free() already contains usb_put_dev(). Therefore, +the redundant usb_put_dev() before dln2_free() may lead to +a double free. + +Fixes: 96da8f148396 ("mfd: dln2: Fix memory leak in dln2_probe()") +Signed-off-by: Dinghao Liu +Link: https://lore.kernel.org/r/20230925024134.9683-1-dinghao.liu@zju.edu.cn +Signed-off-by: Lee Jones +Signed-off-by: Sasha Levin +--- + drivers/mfd/dln2.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/mfd/dln2.c b/drivers/mfd/dln2.c +index fc65f9e25fda8..852129ea07666 100644 +--- a/drivers/mfd/dln2.c ++++ b/drivers/mfd/dln2.c +@@ -836,7 +836,6 @@ static int dln2_probe(struct usb_interface *interface, + dln2_stop_rx_urbs(dln2); + + out_free: +- usb_put_dev(dln2->usb_dev); + dln2_free(dln2); + + return ret; +-- +2.42.0 + diff --git a/queue-5.10/misc-st_core-do-not-call-kfree_skb-under-spin_lock_i.patch b/queue-5.10/misc-st_core-do-not-call-kfree_skb-under-spin_lock_i.patch new file mode 100644 index 00000000000..dcef05ba693 --- /dev/null +++ b/queue-5.10/misc-st_core-do-not-call-kfree_skb-under-spin_lock_i.patch @@ -0,0 +1,65 @@ +From 68be93da764ef739118c59ab1455281e640e26e3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 23 Aug 2023 11:50:20 +0800 +Subject: misc: st_core: Do not call kfree_skb() under spin_lock_irqsave() + +From: Jinjie Ruan + +[ Upstream commit 4d08c3d12b61022501989f9f071514d2d6f77c47 ] + +It is not allowed to call kfree_skb() from hardware interrupt +context or with hardware interrupts being disabled. +So replace kfree_skb() with dev_kfree_skb_irq() under +spin_lock_irqsave(). Compile tested only. + +Fixes: 53618cc1e51e ("Staging: sources for ST core") +Signed-off-by: Jinjie Ruan +Link: https://lore.kernel.org/r/20230823035020.1281892-1-ruanjinjie@huawei.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/misc/ti-st/st_core.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/misc/ti-st/st_core.c b/drivers/misc/ti-st/st_core.c +index f4ddd1e670151..ca115f344fa29 100644 +--- a/drivers/misc/ti-st/st_core.c ++++ b/drivers/misc/ti-st/st_core.c +@@ -15,6 +15,7 @@ + #include + + #include ++#include + + extern void st_kim_recv(void *, const unsigned char *, long); + void st_int_recv(void *, const unsigned char *, long); +@@ -436,7 +437,7 @@ static void st_int_enqueue(struct st_data_s *st_gdata, struct sk_buff *skb) + case ST_LL_AWAKE_TO_ASLEEP: + pr_err("ST LL is illegal state(%ld)," + "purging received skb.", st_ll_getstate(st_gdata)); +- kfree_skb(skb); ++ dev_kfree_skb_irq(skb); + break; + case ST_LL_ASLEEP: + skb_queue_tail(&st_gdata->tx_waitq, skb); +@@ -445,7 +446,7 @@ static void st_int_enqueue(struct st_data_s *st_gdata, struct sk_buff *skb) + default: + pr_err("ST LL is illegal state(%ld)," + "purging received skb.", st_ll_getstate(st_gdata)); +- kfree_skb(skb); ++ dev_kfree_skb_irq(skb); + break; + } + +@@ -499,7 +500,7 @@ void st_tx_wakeup(struct st_data_s *st_data) + spin_unlock_irqrestore(&st_data->lock, flags); + break; + } +- kfree_skb(skb); ++ dev_kfree_skb_irq(skb); + spin_unlock_irqrestore(&st_data->lock, flags); + } + /* if wake-up is set in another context- restart sending */ +-- +2.42.0 + diff --git a/queue-5.10/mlxsw-use-size_mul-in-call-to-struct_size.patch b/queue-5.10/mlxsw-use-size_mul-in-call-to-struct_size.patch new file mode 100644 index 00000000000..a8429031a53 --- /dev/null +++ b/queue-5.10/mlxsw-use-size_mul-in-call-to-struct_size.patch @@ -0,0 +1,39 @@ +From 90abba10c36efa030d6815fd7a783a23233c7852 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Sep 2023 13:01:23 -0600 +Subject: mlxsw: Use size_mul() in call to struct_size() + +From: Gustavo A. R. Silva + +[ Upstream commit e22c6ea025013ae447fe269269753ffec763dde5 ] + +If, for any reason, the open-coded arithmetic causes a wraparound, the +protection that `struct_size()` adds against potential integer overflows +is defeated. Fix this by hardening call to `struct_size()` with `size_mul()`. + +Fixes: 2285ec872d9d ("mlxsw: spectrum_acl_bloom_filter: use struct_size() in kzalloc()") +Signed-off-by: Gustavo A. R. Silva +Reviewed-by: Kees Cook +Reviewed-by: Ido Schimmel +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_bloom_filter.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_bloom_filter.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_bloom_filter.c +index dbd3bebf11eca..2e8b17e3b9358 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_bloom_filter.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_bloom_filter.c +@@ -251,7 +251,7 @@ mlxsw_sp_acl_bf_init(struct mlxsw_sp *mlxsw_sp, unsigned int num_erp_banks) + * is 2^ACL_MAX_BF_LOG + */ + bf_bank_size = 1 << MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_BF_LOG); +- bf = kzalloc(struct_size(bf, refcnt, bf_bank_size * num_erp_banks), ++ bf = kzalloc(struct_size(bf, refcnt, size_mul(bf_bank_size, num_erp_banks)), + GFP_KERNEL); + if (!bf) + return ERR_PTR(-ENOMEM); +-- +2.42.0 + diff --git a/queue-5.10/modpost-fix-tee-module_device_table-built-on-big-end.patch b/queue-5.10/modpost-fix-tee-module_device_table-built-on-big-end.patch new file mode 100644 index 00000000000..33aa4a1cd8f --- /dev/null +++ b/queue-5.10/modpost-fix-tee-module_device_table-built-on-big-end.patch @@ -0,0 +1,71 @@ +From e6a6f748a5ad163026856c0dd6e9418eb91ffa75 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 8 Oct 2023 02:04:44 +0900 +Subject: modpost: fix tee MODULE_DEVICE_TABLE built on big-endian host + +From: Masahiro Yamada + +[ Upstream commit 7f54e00e5842663c2cea501bbbdfa572c94348a3 ] + +When MODULE_DEVICE_TABLE(tee, ) is built on a host with a different +endianness from the target architecture, it results in an incorrect +MODULE_ALIAS(). + +For example, see a case where drivers/char/hw_random/optee-rng.c +is built as a module for ARM little-endian. + +If you build it on a little-endian host, you will get the correct +MODULE_ALIAS: + + $ grep MODULE_ALIAS drivers/char/hw_random/optee-rng.mod.c + MODULE_ALIAS("tee:ab7a617c-b8e7-4d8f-8301-d09b61036b64*"); + +However, if you build it on a big-endian host, you will get a wrong +MODULE_ALIAS: + + $ grep MODULE_ALIAS drivers/char/hw_random/optee-rng.mod.c + MODULE_ALIAS("tee:646b0361-9bd0-0183-8f4d-e7b87c617aab*"); + +The same problem also occurs when you enable CONFIG_CPU_BIG_ENDIAN, +and build it on a little-endian host. + +This issue has been unnoticed because the ARM kernel is configured for +little-endian by default, and most likely built on a little-endian host +(cross-build on x86 or native-build on ARM). + +The uuid field must not be reversed because uuid_t is an array of __u8. + +Fixes: 0fc1db9d1059 ("tee: add bus driver framework for TEE based devices") +Signed-off-by: Masahiro Yamada +Reviewed-by: Sumit Garg +Signed-off-by: Sasha Levin +--- + scripts/mod/file2alias.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c +index da4df53ee6955..7154df094f40b 100644 +--- a/scripts/mod/file2alias.c ++++ b/scripts/mod/file2alias.c +@@ -1326,13 +1326,13 @@ static int do_typec_entry(const char *filename, void *symval, char *alias) + /* Looks like: tee:uuid */ + static int do_tee_entry(const char *filename, void *symval, char *alias) + { +- DEF_FIELD(symval, tee_client_device_id, uuid); ++ DEF_FIELD_ADDR(symval, tee_client_device_id, uuid); + + sprintf(alias, "tee:%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x", +- uuid.b[0], uuid.b[1], uuid.b[2], uuid.b[3], uuid.b[4], +- uuid.b[5], uuid.b[6], uuid.b[7], uuid.b[8], uuid.b[9], +- uuid.b[10], uuid.b[11], uuid.b[12], uuid.b[13], uuid.b[14], +- uuid.b[15]); ++ uuid->b[0], uuid->b[1], uuid->b[2], uuid->b[3], uuid->b[4], ++ uuid->b[5], uuid->b[6], uuid->b[7], uuid->b[8], uuid->b[9], ++ uuid->b[10], uuid->b[11], uuid->b[12], uuid->b[13], uuid->b[14], ++ uuid->b[15]); + + add_wildcard(alias); + return 1; +-- +2.42.0 + diff --git a/queue-5.10/nd_btt-make-btt-lanes-preemptible.patch b/queue-5.10/nd_btt-make-btt-lanes-preemptible.patch new file mode 100644 index 00000000000..90535851539 --- /dev/null +++ b/queue-5.10/nd_btt-make-btt-lanes-preemptible.patch @@ -0,0 +1,94 @@ +From 88379ef5535c69920c73f88e62e28f0d558c8240 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Sep 2023 07:37:12 +0200 +Subject: nd_btt: Make BTT lanes preemptible + +From: Tomas Glozar + +[ Upstream commit 36c75ce3bd299878fd9b238e9803d3817ddafbf3 ] + +nd_region_acquire_lane uses get_cpu, which disables preemption. This is +an issue on PREEMPT_RT kernels, since btt_write_pg and also +nd_region_acquire_lane itself take a spin lock, resulting in BUG: +sleeping function called from invalid context. + +Fix the issue by replacing get_cpu with smp_process_id and +migrate_disable when needed. This makes BTT operations preemptible, thus +permitting the use of spin_lock. + +BUG example occurring when running ndctl tests on PREEMPT_RT kernel: + +BUG: sleeping function called from invalid context at +kernel/locking/spinlock_rt.c:48 +in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 4903, name: +libndctl +preempt_count: 1, expected: 0 +RCU nest depth: 0, expected: 0 +Preemption disabled at: +[] nd_region_acquire_lane+0x15/0x90 [libnvdimm] +Call Trace: + + dump_stack_lvl+0x8e/0xb0 + __might_resched+0x19b/0x250 + rt_spin_lock+0x4c/0x100 + ? btt_write_pg+0x2d7/0x500 [nd_btt] + btt_write_pg+0x2d7/0x500 [nd_btt] + ? local_clock_noinstr+0x9/0xc0 + btt_submit_bio+0x16d/0x270 [nd_btt] + __submit_bio+0x48/0x80 + __submit_bio_noacct+0x7e/0x1e0 + submit_bio_wait+0x58/0xb0 + __blkdev_direct_IO_simple+0x107/0x240 + ? inode_set_ctime_current+0x51/0x110 + ? __pfx_submit_bio_wait_endio+0x10/0x10 + blkdev_write_iter+0x1d8/0x290 + vfs_write+0x237/0x330 + ... + + +Fixes: 5212e11fde4d ("nd_btt: atomic sector updates") +Signed-off-by: Tomas Glozar +Reviewed-by: Ira Weiny +Reviewed-by: Vishal Verma +Signed-off-by: Ira Weiny +Signed-off-by: Sasha Levin +--- + drivers/nvdimm/region_devs.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c +index 1d72653b5c8d1..0a75948cde5a1 100644 +--- a/drivers/nvdimm/region_devs.c ++++ b/drivers/nvdimm/region_devs.c +@@ -959,7 +959,8 @@ unsigned int nd_region_acquire_lane(struct nd_region *nd_region) + { + unsigned int cpu, lane; + +- cpu = get_cpu(); ++ migrate_disable(); ++ cpu = smp_processor_id(); + if (nd_region->num_lanes < nr_cpu_ids) { + struct nd_percpu_lane *ndl_lock, *ndl_count; + +@@ -978,16 +979,15 @@ EXPORT_SYMBOL(nd_region_acquire_lane); + void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) + { + if (nd_region->num_lanes < nr_cpu_ids) { +- unsigned int cpu = get_cpu(); ++ unsigned int cpu = smp_processor_id(); + struct nd_percpu_lane *ndl_lock, *ndl_count; + + ndl_count = per_cpu_ptr(nd_region->lane, cpu); + ndl_lock = per_cpu_ptr(nd_region->lane, lane); + if (--ndl_count->count == 0) + spin_unlock(&ndl_lock->lock); +- put_cpu(); + } +- put_cpu(); ++ migrate_enable(); + } + EXPORT_SYMBOL(nd_region_release_lane); + +-- +2.42.0 + diff --git a/queue-5.10/net-add-dev_stats_read-helper.patch b/queue-5.10/net-add-dev_stats_read-helper.patch new file mode 100644 index 00000000000..8d4a9984c2a --- /dev/null +++ b/queue-5.10/net-add-dev_stats_read-helper.patch @@ -0,0 +1,55 @@ +From 21a58e3002964ba267157e9f8d848f44be6310cc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Sep 2023 08:52:16 +0000 +Subject: net: add DEV_STATS_READ() helper + +From: Eric Dumazet + +[ Upstream commit 0b068c714ca9479d2783cc333fff5bc2d4a6d45c ] + +Companion of DEV_STATS_INC() & DEV_STATS_ADD(). + +This is going to be used in the series. + +Use it in macsec_get_stats64(). + +Signed-off-by: Eric Dumazet +Signed-off-by: David S. Miller +Stable-dep-of: ff672b9ffeb3 ("ipvlan: properly track tx_errors") +Signed-off-by: Sasha Levin +--- + drivers/net/macsec.c | 6 +++--- + include/linux/netdevice.h | 1 + + 2 files changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c +index 0ffcef2fa10af..83b02dc7dfd2d 100644 +--- a/drivers/net/macsec.c ++++ b/drivers/net/macsec.c +@@ -3686,9 +3686,9 @@ static void macsec_get_stats64(struct net_device *dev, + + dev_fetch_sw_netstats(s, dev->tstats); + +- s->rx_dropped = atomic_long_read(&dev->stats.__rx_dropped); +- s->tx_dropped = atomic_long_read(&dev->stats.__tx_dropped); +- s->rx_errors = atomic_long_read(&dev->stats.__rx_errors); ++ s->rx_dropped = DEV_STATS_READ(dev, rx_dropped); ++ s->tx_dropped = DEV_STATS_READ(dev, tx_dropped); ++ s->rx_errors = DEV_STATS_READ(dev, rx_errors); + } + + static int macsec_get_iflink(const struct net_device *dev) +diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h +index e814ce78a1965..3380668478e8a 100644 +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -5286,5 +5286,6 @@ extern struct net_device *blackhole_netdev; + #define DEV_STATS_INC(DEV, FIELD) atomic_long_inc(&(DEV)->stats.__##FIELD) + #define DEV_STATS_ADD(DEV, FIELD, VAL) \ + atomic_long_add((VAL), &(DEV)->stats.__##FIELD) ++#define DEV_STATS_READ(DEV, FIELD) atomic_long_read(&(DEV)->stats.__##FIELD) + + #endif /* _LINUX_NETDEVICE_H */ +-- +2.42.0 + diff --git a/queue-5.10/net-spider_net-use-size_add-in-call-to-struct_size.patch b/queue-5.10/net-spider_net-use-size_add-in-call-to-struct_size.patch new file mode 100644 index 00000000000..82550abdd6c --- /dev/null +++ b/queue-5.10/net-spider_net-use-size_add-in-call-to-struct_size.patch @@ -0,0 +1,40 @@ +From 1ca0aec53a08a60c3e3ca6a765be0f22ab5ead4b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Sep 2023 13:25:36 -0600 +Subject: net: spider_net: Use size_add() in call to struct_size() + +From: Gustavo A. R. Silva + +[ Upstream commit 0201409079b975e46cc40e8bdff4bd61329ee10f ] + +If, for any reason, the open-coded arithmetic causes a wraparound, +the protection that `struct_size()` adds against potential integer +overflows is defeated. Fix this by hardening call to `struct_size()` +with `size_add()`. + +Fixes: 3f1071ec39f7 ("net: spider_net: Use struct_size() helper") +Signed-off-by: Gustavo A. R. Silva +Reviewed-by: Kees Cook +Signed-off-by: Geoff Levand +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/toshiba/spider_net.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/toshiba/spider_net.c b/drivers/net/ethernet/toshiba/spider_net.c +index 5f5b33e6653b2..9d4c49f28d31f 100644 +--- a/drivers/net/ethernet/toshiba/spider_net.c ++++ b/drivers/net/ethernet/toshiba/spider_net.c +@@ -2311,7 +2311,7 @@ spider_net_alloc_card(void) + struct spider_net_card *card; + + netdev = alloc_etherdev(struct_size(card, darray, +- tx_descriptors + rx_descriptors)); ++ size_add(tx_descriptors, rx_descriptors))); + if (!netdev) + return NULL; + +-- +2.42.0 + diff --git a/queue-5.10/overflow-implement-size_t-saturating-arithmetic-help.patch b/queue-5.10/overflow-implement-size_t-saturating-arithmetic-help.patch new file mode 100644 index 00000000000..80fc7e0e70c --- /dev/null +++ b/queue-5.10/overflow-implement-size_t-saturating-arithmetic-help.patch @@ -0,0 +1,377 @@ +From 914111e9eb892f616981bd610879591e6dfe5798 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 18 Sep 2021 15:17:53 -0700 +Subject: overflow: Implement size_t saturating arithmetic helpers + +From: Kees Cook + +[ Upstream commit e1be43d9b5d0d1310dbd90185a8e5c7145dde40f ] + +In order to perform more open-coded replacements of common allocation +size arithmetic, the kernel needs saturating (SIZE_MAX) helpers for +multiplication, addition, and subtraction. For example, it is common in +allocators, especially on realloc, to add to an existing size: + + p = krealloc(map->patch, + sizeof(struct reg_sequence) * (map->patch_regs + num_regs), + GFP_KERNEL); + +There is no existing saturating replacement for this calculation, and +just leaving the addition open coded inside array_size() could +potentially overflow as well. For example, an overflow in an expression +for a size_t argument might wrap to zero: + + array_size(anything, something_at_size_max + 1) == 0 + +Introduce size_mul(), size_add(), and size_sub() helpers that +implicitly promote arguments to size_t and saturated calculations for +use in allocations. With these helpers it is also possible to redefine +array_size(), array3_size(), flex_array_size(), and struct_size() in +terms of the new helpers. + +As with the check_*_overflow() helpers, the new helpers use __must_check, +though what is really desired is a way to make sure that assignment is +only to a size_t lvalue. Without this, it's still possible to introduce +overflow/underflow via type conversion (i.e. from size_t to int). +Enforcing this will currently need to be left to static analysis or +future use of -Wconversion. + +Additionally update the overflow unit tests to force runtime evaluation +for the pathological cases. + +Cc: Rasmus Villemoes +Cc: Gustavo A. R. Silva +Cc: Nathan Chancellor +Cc: Jason Gunthorpe +Cc: Nick Desaulniers +Cc: Leon Romanovsky +Cc: Keith Busch +Cc: Len Baker +Signed-off-by: Kees Cook +Stable-dep-of: d692873cbe86 ("gve: Use size_add() in call to struct_size()") +Signed-off-by: Sasha Levin +--- + Documentation/process/deprecated.rst | 20 ++++- + include/linux/overflow.h | 110 +++++++++++++++++---------- + lib/test_overflow.c | 98 ++++++++++++++++++++++++ + 3 files changed, 184 insertions(+), 44 deletions(-) + +diff --git a/Documentation/process/deprecated.rst b/Documentation/process/deprecated.rst +index 9d83b8db88740..86ea327b7e3a7 100644 +--- a/Documentation/process/deprecated.rst ++++ b/Documentation/process/deprecated.rst +@@ -70,6 +70,9 @@ Instead, the 2-factor form of the allocator should be used:: + + foo = kmalloc_array(count, size, GFP_KERNEL); + ++Specifically, kmalloc() can be replaced with kmalloc_array(), and ++kzalloc() can be replaced with kcalloc(). ++ + If no 2-factor form is available, the saturate-on-overflow helpers should + be used:: + +@@ -90,9 +93,20 @@ Instead, use the helper:: + array usage and switch to a `flexible array member + <#zero-length-and-one-element-arrays>`_ instead. + +-See array_size(), array3_size(), and struct_size(), +-for more details as well as the related check_add_overflow() and +-check_mul_overflow() family of functions. ++For other calculations, please compose the use of the size_mul(), ++size_add(), and size_sub() helpers. For example, in the case of:: ++ ++ foo = krealloc(current_size + chunk_size * (count - 3), GFP_KERNEL); ++ ++Instead, use the helpers:: ++ ++ foo = krealloc(size_add(current_size, ++ size_mul(chunk_size, ++ size_sub(count, 3))), GFP_KERNEL); ++ ++For more details, also see array3_size() and flex_array_size(), ++as well as the related check_mul_overflow(), check_add_overflow(), ++check_sub_overflow(), and check_shl_overflow() family of functions. + + simple_strtol(), simple_strtoll(), simple_strtoul(), simple_strtoull() + ---------------------------------------------------------------------- +diff --git a/include/linux/overflow.h b/include/linux/overflow.h +index ef74051d5cfed..35af574d006f5 100644 +--- a/include/linux/overflow.h ++++ b/include/linux/overflow.h +@@ -250,81 +250,94 @@ static inline bool __must_check __must_check_overflow(bool overflow) + })) + + /** +- * array_size() - Calculate size of 2-dimensional array. +- * +- * @a: dimension one +- * @b: dimension two ++ * size_mul() - Calculate size_t multiplication with saturation at SIZE_MAX + * +- * Calculates size of 2-dimensional array: @a * @b. ++ * @factor1: first factor ++ * @factor2: second factor + * +- * Returns: number of bytes needed to represent the array or SIZE_MAX on +- * overflow. ++ * Returns: calculate @factor1 * @factor2, both promoted to size_t, ++ * with any overflow causing the return value to be SIZE_MAX. The ++ * lvalue must be size_t to avoid implicit type conversion. + */ +-static inline __must_check size_t array_size(size_t a, size_t b) ++static inline size_t __must_check size_mul(size_t factor1, size_t factor2) + { + size_t bytes; + +- if (check_mul_overflow(a, b, &bytes)) ++ if (check_mul_overflow(factor1, factor2, &bytes)) + return SIZE_MAX; + + return bytes; + } + + /** +- * array3_size() - Calculate size of 3-dimensional array. ++ * size_add() - Calculate size_t addition with saturation at SIZE_MAX + * +- * @a: dimension one +- * @b: dimension two +- * @c: dimension three +- * +- * Calculates size of 3-dimensional array: @a * @b * @c. ++ * @addend1: first addend ++ * @addend2: second addend + * +- * Returns: number of bytes needed to represent the array or SIZE_MAX on +- * overflow. ++ * Returns: calculate @addend1 + @addend2, both promoted to size_t, ++ * with any overflow causing the return value to be SIZE_MAX. The ++ * lvalue must be size_t to avoid implicit type conversion. + */ +-static inline __must_check size_t array3_size(size_t a, size_t b, size_t c) ++static inline size_t __must_check size_add(size_t addend1, size_t addend2) + { + size_t bytes; + +- if (check_mul_overflow(a, b, &bytes)) +- return SIZE_MAX; +- if (check_mul_overflow(bytes, c, &bytes)) ++ if (check_add_overflow(addend1, addend2, &bytes)) + return SIZE_MAX; + + return bytes; + } + +-/* +- * Compute a*b+c, returning SIZE_MAX on overflow. Internal helper for +- * struct_size() below. ++/** ++ * size_sub() - Calculate size_t subtraction with saturation at SIZE_MAX ++ * ++ * @minuend: value to subtract from ++ * @subtrahend: value to subtract from @minuend ++ * ++ * Returns: calculate @minuend - @subtrahend, both promoted to size_t, ++ * with any overflow causing the return value to be SIZE_MAX. For ++ * composition with the size_add() and size_mul() helpers, neither ++ * argument may be SIZE_MAX (or the result with be forced to SIZE_MAX). ++ * The lvalue must be size_t to avoid implicit type conversion. + */ +-static inline __must_check size_t __ab_c_size(size_t a, size_t b, size_t c) ++static inline size_t __must_check size_sub(size_t minuend, size_t subtrahend) + { + size_t bytes; + +- if (check_mul_overflow(a, b, &bytes)) +- return SIZE_MAX; +- if (check_add_overflow(bytes, c, &bytes)) ++ if (minuend == SIZE_MAX || subtrahend == SIZE_MAX || ++ check_sub_overflow(minuend, subtrahend, &bytes)) + return SIZE_MAX; + + return bytes; + } + + /** +- * struct_size() - Calculate size of structure with trailing array. +- * @p: Pointer to the structure. +- * @member: Name of the array member. +- * @count: Number of elements in the array. ++ * array_size() - Calculate size of 2-dimensional array. + * +- * Calculates size of memory needed for structure @p followed by an +- * array of @count number of @member elements. ++ * @a: dimension one ++ * @b: dimension two + * +- * Return: number of bytes needed or SIZE_MAX on overflow. ++ * Calculates size of 2-dimensional array: @a * @b. ++ * ++ * Returns: number of bytes needed to represent the array or SIZE_MAX on ++ * overflow. + */ +-#define struct_size(p, member, count) \ +- __ab_c_size(count, \ +- sizeof(*(p)->member) + __must_be_array((p)->member),\ +- sizeof(*(p))) ++#define array_size(a, b) size_mul(a, b) ++ ++/** ++ * array3_size() - Calculate size of 3-dimensional array. ++ * ++ * @a: dimension one ++ * @b: dimension two ++ * @c: dimension three ++ * ++ * Calculates size of 3-dimensional array: @a * @b * @c. ++ * ++ * Returns: number of bytes needed to represent the array or SIZE_MAX on ++ * overflow. ++ */ ++#define array3_size(a, b, c) size_mul(size_mul(a, b), c) + + /** + * flex_array_size() - Calculate size of a flexible array member +@@ -340,7 +353,22 @@ static inline __must_check size_t __ab_c_size(size_t a, size_t b, size_t c) + * Return: number of bytes needed or SIZE_MAX on overflow. + */ + #define flex_array_size(p, member, count) \ +- array_size(count, \ +- sizeof(*(p)->member) + __must_be_array((p)->member)) ++ size_mul(count, \ ++ sizeof(*(p)->member) + __must_be_array((p)->member)) ++ ++/** ++ * struct_size() - Calculate size of structure with trailing flexible array. ++ * ++ * @p: Pointer to the structure. ++ * @member: Name of the array member. ++ * @count: Number of elements in the array. ++ * ++ * Calculates size of memory needed for structure @p followed by an ++ * array of @count number of @member elements. ++ * ++ * Return: number of bytes needed or SIZE_MAX on overflow. ++ */ ++#define struct_size(p, member, count) \ ++ size_add(sizeof(*(p)), flex_array_size(p, member, count)) + + #endif /* __LINUX_OVERFLOW_H */ +diff --git a/lib/test_overflow.c b/lib/test_overflow.c +index 7a4b6f6c5473c..7a5a5738d2d21 100644 +--- a/lib/test_overflow.c ++++ b/lib/test_overflow.c +@@ -588,12 +588,110 @@ static int __init test_overflow_allocation(void) + return err; + } + ++struct __test_flex_array { ++ unsigned long flags; ++ size_t count; ++ unsigned long data[]; ++}; ++ ++static int __init test_overflow_size_helpers(void) ++{ ++ struct __test_flex_array *obj; ++ int count = 0; ++ int err = 0; ++ int var; ++ ++#define check_one_size_helper(expected, func, args...) ({ \ ++ bool __failure = false; \ ++ size_t _r; \ ++ \ ++ _r = func(args); \ ++ if (_r != (expected)) { \ ++ pr_warn("expected " #func "(" #args ") " \ ++ "to return %zu but got %zu instead\n", \ ++ (size_t)(expected), _r); \ ++ __failure = true; \ ++ } \ ++ count++; \ ++ __failure; \ ++}) ++ ++ var = 4; ++ err |= check_one_size_helper(20, size_mul, var++, 5); ++ err |= check_one_size_helper(20, size_mul, 4, var++); ++ err |= check_one_size_helper(0, size_mul, 0, 3); ++ err |= check_one_size_helper(0, size_mul, 3, 0); ++ err |= check_one_size_helper(6, size_mul, 2, 3); ++ err |= check_one_size_helper(SIZE_MAX, size_mul, SIZE_MAX, 1); ++ err |= check_one_size_helper(SIZE_MAX, size_mul, SIZE_MAX, 3); ++ err |= check_one_size_helper(SIZE_MAX, size_mul, SIZE_MAX, -3); ++ ++ var = 4; ++ err |= check_one_size_helper(9, size_add, var++, 5); ++ err |= check_one_size_helper(9, size_add, 4, var++); ++ err |= check_one_size_helper(9, size_add, 9, 0); ++ err |= check_one_size_helper(9, size_add, 0, 9); ++ err |= check_one_size_helper(5, size_add, 2, 3); ++ err |= check_one_size_helper(SIZE_MAX, size_add, SIZE_MAX, 1); ++ err |= check_one_size_helper(SIZE_MAX, size_add, SIZE_MAX, 3); ++ err |= check_one_size_helper(SIZE_MAX, size_add, SIZE_MAX, -3); ++ ++ var = 4; ++ err |= check_one_size_helper(1, size_sub, var--, 3); ++ err |= check_one_size_helper(1, size_sub, 4, var--); ++ err |= check_one_size_helper(1, size_sub, 3, 2); ++ err |= check_one_size_helper(9, size_sub, 9, 0); ++ err |= check_one_size_helper(SIZE_MAX, size_sub, 9, -3); ++ err |= check_one_size_helper(SIZE_MAX, size_sub, 0, 9); ++ err |= check_one_size_helper(SIZE_MAX, size_sub, 2, 3); ++ err |= check_one_size_helper(SIZE_MAX, size_sub, SIZE_MAX, 0); ++ err |= check_one_size_helper(SIZE_MAX, size_sub, SIZE_MAX, 10); ++ err |= check_one_size_helper(SIZE_MAX, size_sub, 0, SIZE_MAX); ++ err |= check_one_size_helper(SIZE_MAX, size_sub, 14, SIZE_MAX); ++ err |= check_one_size_helper(SIZE_MAX - 2, size_sub, SIZE_MAX - 1, 1); ++ err |= check_one_size_helper(SIZE_MAX - 4, size_sub, SIZE_MAX - 1, 3); ++ err |= check_one_size_helper(1, size_sub, SIZE_MAX - 1, -3); ++ ++ var = 4; ++ err |= check_one_size_helper(4 * sizeof(*obj->data), ++ flex_array_size, obj, data, var++); ++ err |= check_one_size_helper(5 * sizeof(*obj->data), ++ flex_array_size, obj, data, var++); ++ err |= check_one_size_helper(0, flex_array_size, obj, data, 0); ++ err |= check_one_size_helper(sizeof(*obj->data), ++ flex_array_size, obj, data, 1); ++ err |= check_one_size_helper(7 * sizeof(*obj->data), ++ flex_array_size, obj, data, 7); ++ err |= check_one_size_helper(SIZE_MAX, ++ flex_array_size, obj, data, -1); ++ err |= check_one_size_helper(SIZE_MAX, ++ flex_array_size, obj, data, SIZE_MAX - 4); ++ ++ var = 4; ++ err |= check_one_size_helper(sizeof(*obj) + (4 * sizeof(*obj->data)), ++ struct_size, obj, data, var++); ++ err |= check_one_size_helper(sizeof(*obj) + (5 * sizeof(*obj->data)), ++ struct_size, obj, data, var++); ++ err |= check_one_size_helper(sizeof(*obj), struct_size, obj, data, 0); ++ err |= check_one_size_helper(sizeof(*obj) + sizeof(*obj->data), ++ struct_size, obj, data, 1); ++ err |= check_one_size_helper(SIZE_MAX, ++ struct_size, obj, data, -3); ++ err |= check_one_size_helper(SIZE_MAX, ++ struct_size, obj, data, SIZE_MAX - 3); ++ ++ pr_info("%d overflow size helper tests finished\n", count); ++ ++ return err; ++} ++ + static int __init test_module_init(void) + { + int err = 0; + + err |= test_overflow_calculation(); + err |= test_overflow_shift(); ++ err |= test_overflow_size_helpers(); + err |= test_overflow_allocation(); + + if (err) { +-- +2.42.0 + diff --git a/queue-5.10/padata-convert-from-atomic_t-to-refcount_t-on-parall.patch b/queue-5.10/padata-convert-from-atomic_t-to-refcount_t-on-parall.patch new file mode 100644 index 00000000000..cf2ed549edd --- /dev/null +++ b/queue-5.10/padata-convert-from-atomic_t-to-refcount_t-on-parall.patch @@ -0,0 +1,87 @@ +From 61f30f1e4d7a6fc4a9cb0c70e4969ab17b213998 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Jul 2021 11:05:11 -0400 +Subject: padata: Convert from atomic_t to refcount_t on parallel_data->refcnt + +From: Xiyu Yang + +[ Upstream commit d5ee8e750c9449e9849a09ce6fb6b8adeaa66adc ] + +refcount_t type and corresponding API can protect refcounters from +accidental underflow and overflow and further use-after-free situations. + +Signed-off-by: Xiyu Yang +Signed-off-by: Xin Tan +Acked-by: Daniel Jordan +Signed-off-by: Herbert Xu +Stable-dep-of: 7ddc21e317b3 ("padata: Fix refcnt handling in padata_free_shell()") +Signed-off-by: Sasha Levin +--- + include/linux/padata.h | 3 ++- + kernel/padata.c | 8 ++++---- + 2 files changed, 6 insertions(+), 5 deletions(-) + +diff --git a/include/linux/padata.h b/include/linux/padata.h +index a433f13fc4bf7..495b16b6b4d72 100644 +--- a/include/linux/padata.h ++++ b/include/linux/padata.h +@@ -12,6 +12,7 @@ + #ifndef PADATA_H + #define PADATA_H + ++#include + #include + #include + #include +@@ -96,7 +97,7 @@ struct parallel_data { + struct padata_shell *ps; + struct padata_list __percpu *reorder_list; + struct padata_serial_queue __percpu *squeue; +- atomic_t refcnt; ++ refcount_t refcnt; + unsigned int seq_nr; + unsigned int processed; + int cpu; +diff --git a/kernel/padata.c b/kernel/padata.c +index 11ca3ebd8b123..dc81c756da3d9 100644 +--- a/kernel/padata.c ++++ b/kernel/padata.c +@@ -211,7 +211,7 @@ int padata_do_parallel(struct padata_shell *ps, + if ((pinst->flags & PADATA_RESET)) + goto out; + +- atomic_inc(&pd->refcnt); ++ refcount_inc(&pd->refcnt); + padata->pd = pd; + padata->cb_cpu = *cb_cpu; + +@@ -385,7 +385,7 @@ static void padata_serial_worker(struct work_struct *serial_work) + } + local_bh_enable(); + +- if (atomic_sub_and_test(cnt, &pd->refcnt)) ++ if (refcount_sub_and_test(cnt, &pd->refcnt)) + padata_free_pd(pd); + } + +@@ -598,7 +598,7 @@ static struct parallel_data *padata_alloc_pd(struct padata_shell *ps) + padata_init_reorder_list(pd); + padata_init_squeues(pd); + pd->seq_nr = -1; +- atomic_set(&pd->refcnt, 1); ++ refcount_set(&pd->refcnt, 1); + spin_lock_init(&pd->lock); + pd->cpu = cpumask_first(pd->cpumask.pcpu); + INIT_WORK(&pd->reorder_work, invoke_padata_reorder); +@@ -672,7 +672,7 @@ static int padata_replace(struct padata_instance *pinst) + synchronize_rcu(); + + list_for_each_entry_continue_reverse(ps, &pinst->pslist, list) +- if (atomic_dec_and_test(&ps->opd->refcnt)) ++ if (refcount_dec_and_test(&ps->opd->refcnt)) + padata_free_pd(ps->opd); + + pinst->flags &= ~PADATA_RESET; +-- +2.42.0 + diff --git a/queue-5.10/padata-fix-refcnt-handling-in-padata_free_shell.patch b/queue-5.10/padata-fix-refcnt-handling-in-padata_free_shell.patch new file mode 100644 index 00000000000..ce389ab28c7 --- /dev/null +++ b/queue-5.10/padata-fix-refcnt-handling-in-padata_free_shell.patch @@ -0,0 +1,110 @@ +From 18904ecbd564f8edf1a126ae097583387224d1d2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Oct 2023 09:15:21 +0800 +Subject: padata: Fix refcnt handling in padata_free_shell() + +From: WangJinchao + +[ Upstream commit 7ddc21e317b360c3444de3023bcc83b85fabae2f ] + +In a high-load arm64 environment, the pcrypt_aead01 test in LTP can lead +to system UAF (Use-After-Free) issues. Due to the lengthy analysis of +the pcrypt_aead01 function call, I'll describe the problem scenario +using a simplified model: + +Suppose there's a user of padata named `user_function` that adheres to +the padata requirement of calling `padata_free_shell` after `serial()` +has been invoked, as demonstrated in the following code: + +```c +struct request { + struct padata_priv padata; + struct completion *done; +}; + +void parallel(struct padata_priv *padata) { + do_something(); +} + +void serial(struct padata_priv *padata) { + struct request *request = container_of(padata, + struct request, + padata); + complete(request->done); +} + +void user_function() { + DECLARE_COMPLETION(done) + padata->parallel = parallel; + padata->serial = serial; + padata_do_parallel(); + wait_for_completion(&done); + padata_free_shell(); +} +``` + +In the corresponding padata.c file, there's the following code: + +```c +static void padata_serial_worker(struct work_struct *serial_work) { + ... + cnt = 0; + + while (!list_empty(&local_list)) { + ... + padata->serial(padata); + cnt++; + } + + local_bh_enable(); + + if (refcount_sub_and_test(cnt, &pd->refcnt)) + padata_free_pd(pd); +} +``` + +Because of the high system load and the accumulation of unexecuted +softirq at this moment, `local_bh_enable()` in padata takes longer +to execute than usual. Subsequently, when accessing `pd->refcnt`, +`pd` has already been released by `padata_free_shell()`, resulting +in a UAF issue with `pd->refcnt`. + +The fix is straightforward: add `refcount_dec_and_test` before calling +`padata_free_pd` in `padata_free_shell`. + +Fixes: 07928d9bfc81 ("padata: Remove broken queue flushing") + +Signed-off-by: WangJinchao +Acked-by: Daniel Jordan +Acked-by: Daniel Jordan +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + kernel/padata.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/kernel/padata.c b/kernel/padata.c +index dc81c756da3d9..7d500219f96bd 100644 +--- a/kernel/padata.c ++++ b/kernel/padata.c +@@ -1107,12 +1107,16 @@ EXPORT_SYMBOL(padata_alloc_shell); + */ + void padata_free_shell(struct padata_shell *ps) + { ++ struct parallel_data *pd; ++ + if (!ps) + return; + + mutex_lock(&ps->pinst->lock); + list_del(&ps->list); +- padata_free_pd(rcu_dereference_protected(ps->pd, 1)); ++ pd = rcu_dereference_protected(ps->pd, 1); ++ if (refcount_dec_and_test(&pd->refcnt)) ++ padata_free_pd(pd); + mutex_unlock(&ps->pinst->lock); + + kfree(ps); +-- +2.42.0 + diff --git a/queue-5.10/pcmcia-cs-fix-possible-hung-task-and-memory-leak-pcc.patch b/queue-5.10/pcmcia-cs-fix-possible-hung-task-and-memory-leak-pcc.patch new file mode 100644 index 00000000000..5269bad088a --- /dev/null +++ b/queue-5.10/pcmcia-cs-fix-possible-hung-task-and-memory-leak-pcc.patch @@ -0,0 +1,43 @@ +From 59c478ee943f4f2bec0e4416be971fda6fa50529 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 12 Nov 2022 17:25:41 +0800 +Subject: pcmcia: cs: fix possible hung task and memory leak pccardd() + +From: Yang Yingliang + +[ Upstream commit e3ea1b4847e49234e691c0d66bf030bd65bb7f2b ] + +If device_register() returns error in pccardd(), it leads two issues: + +1. The socket_released has never been completed, it will block + pcmcia_unregister_socket(), because of waiting for completion + of socket_released. +2. The device name allocated by dev_set_name() is leaked. + +Fix this two issues by calling put_device() when device_register() fails. +socket_released can be completed in pcmcia_release_socket(), the name can +be freed in kobject_cleanup(). + +Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") +Signed-off-by: Yang Yingliang +Signed-off-by: Dominik Brodowski +Signed-off-by: Sasha Levin +--- + drivers/pcmcia/cs.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pcmcia/cs.c b/drivers/pcmcia/cs.c +index f70197154a362..820cce7c8b400 100644 +--- a/drivers/pcmcia/cs.c ++++ b/drivers/pcmcia/cs.c +@@ -605,6 +605,7 @@ static int pccardd(void *__skt) + dev_warn(&skt->dev, "PCMCIA: unable to register socket\n"); + skt->thread = NULL; + complete(&skt->thread_done); ++ put_device(&skt->dev); + return 0; + } + ret = pccard_sysfs_add_socket(&skt->dev); +-- +2.42.0 + diff --git a/queue-5.10/pcmcia-ds-fix-possible-name-leak-in-error-path-in-pc.patch b/queue-5.10/pcmcia-ds-fix-possible-name-leak-in-error-path-in-pc.patch new file mode 100644 index 00000000000..4b95895488f --- /dev/null +++ b/queue-5.10/pcmcia-ds-fix-possible-name-leak-in-error-path-in-pc.patch @@ -0,0 +1,53 @@ +From c389fde2f74d6e01b0eb0f9917c5e660e4bed338 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 12 Nov 2022 17:29:24 +0800 +Subject: pcmcia: ds: fix possible name leak in error path in + pcmcia_device_add() + +From: Yang Yingliang + +[ Upstream commit 99e1241049a92dd3e9a90a0f91e32ce390133278 ] + +Afer commit 1fa5ae857bb1 ("driver core: get rid of struct device's +bus_id string array"), the name of device is allocated dynamically. +Therefore, it needs to be freed, which is done by the driver core for +us once all references to the device are gone. Therefore, move the +dev_set_name() call immediately before the call device_register(), which +either succeeds (then the freeing will be done upon subsequent remvoal), +or puts the reference in the error call. Also, it is not unusual that the +return value of dev_set_name is not checked. + +Fixes: 1fa5ae857bb1 ("driver core: get rid of struct device's bus_id string array") +Signed-off-by: Yang Yingliang +[linux@dominikbrodowski.net: simplification, commit message modified] +Signed-off-by: Dominik Brodowski +Signed-off-by: Sasha Levin +--- + drivers/pcmcia/ds.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c +index 341305496b06b..bf2e856f53e97 100644 +--- a/drivers/pcmcia/ds.c ++++ b/drivers/pcmcia/ds.c +@@ -518,9 +518,6 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, + /* by default don't allow DMA */ + p_dev->dma_mask = 0; + p_dev->dev.dma_mask = &p_dev->dma_mask; +- dev_set_name(&p_dev->dev, "%d.%d", p_dev->socket->sock, p_dev->device_no); +- if (!dev_name(&p_dev->dev)) +- goto err_free; + p_dev->devname = kasprintf(GFP_KERNEL, "pcmcia%s", dev_name(&p_dev->dev)); + if (!p_dev->devname) + goto err_free; +@@ -578,6 +575,7 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, + + pcmcia_device_query(p_dev); + ++ dev_set_name(&p_dev->dev, "%d.%d", p_dev->socket->sock, p_dev->device_no); + if (device_register(&p_dev->dev)) { + mutex_lock(&s->ops_mutex); + list_del(&p_dev->socket_device_list); +-- +2.42.0 + diff --git a/queue-5.10/pcmcia-ds-fix-refcount-leak-in-pcmcia_device_add.patch b/queue-5.10/pcmcia-ds-fix-refcount-leak-in-pcmcia_device_add.patch new file mode 100644 index 00000000000..6318d4d7e33 --- /dev/null +++ b/queue-5.10/pcmcia-ds-fix-refcount-leak-in-pcmcia_device_add.patch @@ -0,0 +1,49 @@ +From 9e88b83ae96144be13f89fd4e2a1240f528aedaa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 12 Nov 2022 17:29:23 +0800 +Subject: pcmcia: ds: fix refcount leak in pcmcia_device_add() + +From: Yang Yingliang + +[ Upstream commit 402ab979b29126068e0b596b641422ff7490214c ] + +As the comment of device_register() says, it should use put_device() +to give up the reference in the error path. Then, insofar resources +will be freed in pcmcia_release_dev(), the error path is no longer +needed. In particular, this means that the (previously missing) dropping +of the reference to &p_dev->function_config->ref is now handled by +pcmcia_release_dev(). + +Fixes: 360b65b95bae ("[PATCH] pcmcia: make config_t independent, add reference counting") +Signed-off-by: Yang Yingliang +[linux@dominikbrodowski.net: simplification, commit message rewrite] +Signed-off-by: Dominik Brodowski +Signed-off-by: Sasha Levin +--- + drivers/pcmcia/ds.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c +index 72114907c0e4d..341305496b06b 100644 +--- a/drivers/pcmcia/ds.c ++++ b/drivers/pcmcia/ds.c +@@ -578,8 +578,14 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, + + pcmcia_device_query(p_dev); + +- if (device_register(&p_dev->dev)) +- goto err_unreg; ++ if (device_register(&p_dev->dev)) { ++ mutex_lock(&s->ops_mutex); ++ list_del(&p_dev->socket_device_list); ++ s->device_count--; ++ mutex_unlock(&s->ops_mutex); ++ put_device(&p_dev->dev); ++ return NULL; ++ } + + return p_dev; + +-- +2.42.0 + diff --git a/queue-5.10/perf-evlist-add-evlist__add_dummy_on_all_cpus.patch b/queue-5.10/perf-evlist-add-evlist__add_dummy_on_all_cpus.patch new file mode 100644 index 00000000000..260d0850627 --- /dev/null +++ b/queue-5.10/perf-evlist-add-evlist__add_dummy_on_all_cpus.patch @@ -0,0 +1,106 @@ +From fa816e764e0de49974df6db2bc09576c3e53e09f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 24 May 2022 10:54:26 +0300 +Subject: perf evlist: Add evlist__add_dummy_on_all_cpus() + +From: Adrian Hunter + +[ Upstream commit 126d68fdcabed8c2ca5ffaba785add93ef722da8 ] + +Add evlist__add_dummy_on_all_cpus() to enable creating a system-wide dummy +event that sets up the system-wide maps before map propagation. + +For convenience, add evlist__add_aux_dummy() so that the logic can be used +whether or not the event needs to be system-wide. + +Signed-off-by: Adrian Hunter +Acked-by: Ian Rogers +Acked-by: Namhyung Kim +Cc: Alexey Bayduraev +Cc: Ian Rogers +Cc: Jiri Olsa +Cc: Leo Yan +Link: https://lore.kernel.org/r/20220524075436.29144-6-adrian.hunter@intel.com +Signed-off-by: Arnaldo Carvalho de Melo +Stable-dep-of: f9cdeb58a9cf ("perf evlist: Avoid frequency mode for the dummy event") +Signed-off-by: Sasha Levin +--- + tools/perf/util/evlist.c | 45 ++++++++++++++++++++++++++++++++++++++++ + tools/perf/util/evlist.h | 5 +++++ + 2 files changed, 50 insertions(+) + +diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c +index 98ae432470cdd..117420abdc325 100644 +--- a/tools/perf/util/evlist.c ++++ b/tools/perf/util/evlist.c +@@ -261,6 +261,51 @@ int evlist__add_dummy(struct evlist *evlist) + return 0; + } + ++static void evlist__add_on_all_cpus(struct evlist *evlist, struct evsel *evsel) ++{ ++ evsel->core.system_wide = true; ++ ++ /* ++ * All CPUs. ++ * ++ * Note perf_event_open() does not accept CPUs that are not online, so ++ * in fact this CPU list will include only all online CPUs. ++ */ ++ perf_cpu_map__put(evsel->core.own_cpus); ++ evsel->core.own_cpus = perf_cpu_map__new(NULL); ++ perf_cpu_map__put(evsel->core.cpus); ++ evsel->core.cpus = perf_cpu_map__get(evsel->core.own_cpus); ++ ++ /* No threads */ ++ perf_thread_map__put(evsel->core.threads); ++ evsel->core.threads = perf_thread_map__new_dummy(); ++ ++ evlist__add(evlist, evsel); ++} ++ ++struct evsel *evlist__add_aux_dummy(struct evlist *evlist, bool system_wide) ++{ ++ struct evsel *evsel = evlist__dummy_event(evlist); ++ ++ if (!evsel) ++ return NULL; ++ ++ evsel->core.attr.exclude_kernel = 1; ++ evsel->core.attr.exclude_guest = 1; ++ evsel->core.attr.exclude_hv = 1; ++ evsel->core.attr.freq = 0; ++ evsel->core.attr.sample_period = 1; ++ evsel->no_aux_samples = true; ++ evsel->name = strdup("dummy:u"); ++ ++ if (system_wide) ++ evlist__add_on_all_cpus(evlist, evsel); ++ else ++ evlist__add(evlist, evsel); ++ ++ return evsel; ++} ++ + static int evlist__add_attrs(struct evlist *evlist, struct perf_event_attr *attrs, size_t nr_attrs) + { + struct evsel *evsel, *n; +diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h +index 9298fce53ea31..eb36f85ba3f3e 100644 +--- a/tools/perf/util/evlist.h ++++ b/tools/perf/util/evlist.h +@@ -111,6 +111,11 @@ int __evlist__add_default_attrs(struct evlist *evlist, + __evlist__add_default_attrs(evlist, array, ARRAY_SIZE(array)) + + int evlist__add_dummy(struct evlist *evlist); ++struct evsel *evlist__add_aux_dummy(struct evlist *evlist, bool system_wide); ++static inline struct evsel *evlist__add_dummy_on_all_cpus(struct evlist *evlist) ++{ ++ return evlist__add_aux_dummy(evlist, true); ++} + + int perf_evlist__add_sb_event(struct evlist *evlist, + struct perf_event_attr *attr, +-- +2.42.0 + diff --git a/queue-5.10/perf-evlist-avoid-frequency-mode-for-the-dummy-event.patch b/queue-5.10/perf-evlist-avoid-frequency-mode-for-the-dummy-event.patch new file mode 100644 index 00000000000..2ef068daa76 --- /dev/null +++ b/queue-5.10/perf-evlist-avoid-frequency-mode-for-the-dummy-event.patch @@ -0,0 +1,86 @@ +From 672023d6b64f7a9777388961b72745c41ec33e1b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Sep 2023 20:56:40 -0700 +Subject: perf evlist: Avoid frequency mode for the dummy event + +From: Ian Rogers + +[ Upstream commit f9cdeb58a9cf46c09b56f5f661ea8da24b6458c3 ] + +Dummy events are created with an attribute where the period and freq +are zero. evsel__config will then see the uninitialized values and +initialize them in evsel__default_freq_period. As fequency mode is +used by default the dummy event would be set to use frequency +mode. However, this has no effect on the dummy event but does cause +unnecessary timers/interrupts. Avoid this overhead by setting the +period to 1 for dummy events. + +evlist__add_aux_dummy calls evlist__add_dummy then sets freq=0 and +period=1. This isn't necessary after this change and so the setting is +removed. + +From Stephane: + +The dummy event is not counting anything. It is used to collect mmap +records and avoid a race condition during the synthesize mmap phase of +perf record. As such, it should not cause any overhead during active +profiling. Yet, it did. Because of a bug the dummy event was +programmed as a sampling event in frequency mode. Events in that mode +incur more kernel overheads because on timer tick, the kernel has to +look at the number of samples for each event and potentially adjust +the sampling period to achieve the desired frequency. The dummy event +was therefore adding a frequency event to task and ctx contexts we may +otherwise not have any, e.g., + + perf record -a -e cpu/event=0x3c,period=10000000/. + +On each timer tick the perf_adjust_freq_unthr_context() is invoked and +if ctx->nr_freq is non-zero, then the kernel will loop over ALL the +events of the context looking for frequency mode ones. In doing, so it +locks the context, and enable/disable the PMU of each hw event. If all +the events of the context are in period mode, the kernel will have to +traverse the list for nothing incurring overhead. The overhead is +multiplied by a very large factor when this happens in a guest kernel. +There is no need for the dummy event to be in frequency mode, it does +not count anything and therefore should not cause extra overhead for +no reason. + +Fixes: 5bae0250237f ("perf evlist: Introduce perf_evlist__new_dummy constructor") +Reported-by: Stephane Eranian +Signed-off-by: Ian Rogers +Acked-by: Adrian Hunter +Cc: Yang Jihong +Cc: Kan Liang +Link: https://lore.kernel.org/r/20230916035640.1074422-1-irogers@google.com +Signed-off-by: Namhyung Kim +Signed-off-by: Sasha Levin +--- + tools/perf/util/evlist.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c +index f0ca9aa7c208e..84b328d2515bd 100644 +--- a/tools/perf/util/evlist.c ++++ b/tools/perf/util/evlist.c +@@ -251,6 +251,9 @@ int evlist__add_dummy(struct evlist *evlist) + .type = PERF_TYPE_SOFTWARE, + .config = PERF_COUNT_SW_DUMMY, + .size = sizeof(attr), /* to capture ABI version */ ++ /* Avoid frequency mode for dummy events to avoid associated timers. */ ++ .freq = 0, ++ .sample_period = 1, + }; + struct evsel *evsel = evsel__new_idx(&attr, evlist->core.nr_entries); + +@@ -271,8 +274,6 @@ struct evsel *evlist__add_aux_dummy(struct evlist *evlist, bool system_wide) + evsel->core.attr.exclude_kernel = 1; + evsel->core.attr.exclude_guest = 1; + evsel->core.attr.exclude_hv = 1; +- evsel->core.attr.freq = 0; +- evsel->core.attr.sample_period = 1; + evsel->core.system_wide = system_wide; + evsel->no_aux_samples = true; + evsel->name = strdup("dummy:u"); +-- +2.42.0 + diff --git a/queue-5.10/perf-hist-add-missing-puts-to-hist__account_cycles.patch b/queue-5.10/perf-hist-add-missing-puts-to-hist__account_cycles.patch new file mode 100644 index 00000000000..ab401cfb765 --- /dev/null +++ b/queue-5.10/perf-hist-add-missing-puts-to-hist__account_cycles.patch @@ -0,0 +1,81 @@ +From d1096669c2a4b70bacb7c3831ec2f17de2f0d73a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 24 Oct 2023 15:23:08 -0700 +Subject: perf hist: Add missing puts to hist__account_cycles + +From: Ian Rogers + +[ Upstream commit c1149037f65bcf0334886180ebe3d5efcf214912 ] + +Caught using reference count checking on perf top with +"--call-graph=lbr". After this no memory leaks were detected. + +Fixes: 57849998e2cd ("perf report: Add processing for cycle histograms") +Signed-off-by: Ian Rogers +Cc: K Prateek Nayak +Cc: Ravi Bangoria +Cc: Sandipan Das +Cc: Anshuman Khandual +Cc: German Gomez +Cc: James Clark +Cc: Nick Terrell +Cc: Sean Christopherson +Cc: Changbin Du +Cc: liuwenyu +Cc: Yang Jihong +Cc: Masami Hiramatsu +Cc: Miguel Ojeda +Cc: Song Liu +Cc: Leo Yan +Cc: Kajol Jain +Cc: Andi Kleen +Cc: Kan Liang +Cc: Athira Rajeev +Cc: Yanteng Si +Cc: Liam Howlett +Cc: Paolo Bonzini +Link: https://lore.kernel.org/r/20231024222353.3024098-6-irogers@google.com +Signed-off-by: Namhyung Kim +Signed-off-by: Sasha Levin +--- + tools/perf/util/hist.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c +index 8a793e4c9400a..c78d8813811cc 100644 +--- a/tools/perf/util/hist.c ++++ b/tools/perf/util/hist.c +@@ -2624,8 +2624,6 @@ void hist__account_cycles(struct branch_stack *bs, struct addr_location *al, + + /* If we have branch cycles always annotate them. */ + if (bs && bs->nr && entries[0].flags.cycles) { +- int i; +- + bi = sample__resolve_bstack(sample, al); + if (bi) { + struct addr_map_symbol *prev = NULL; +@@ -2640,7 +2638,7 @@ void hist__account_cycles(struct branch_stack *bs, struct addr_location *al, + * Note that perf stores branches reversed from + * program order! + */ +- for (i = bs->nr - 1; i >= 0; i--) { ++ for (int i = bs->nr - 1; i >= 0; i--) { + addr_map_symbol__account_cycles(&bi[i].from, + nonany_branch_mode ? NULL : prev, + bi[i].flags.cycles); +@@ -2649,6 +2647,12 @@ void hist__account_cycles(struct branch_stack *bs, struct addr_location *al, + if (total_cycles) + *total_cycles += bi[i].flags.cycles; + } ++ for (unsigned int i = 0; i < bs->nr; i++) { ++ map__put(bi[i].to.ms.map); ++ maps__put(bi[i].to.ms.maps); ++ map__put(bi[i].from.ms.map); ++ maps__put(bi[i].from.ms.maps); ++ } + free(bi); + } + } +-- +2.42.0 + diff --git a/queue-5.10/perf-machine-avoid-out-of-bounds-lbr-memory-read.patch b/queue-5.10/perf-machine-avoid-out-of-bounds-lbr-memory-read.patch new file mode 100644 index 00000000000..3b07d3044af --- /dev/null +++ b/queue-5.10/perf-machine-avoid-out-of-bounds-lbr-memory-read.patch @@ -0,0 +1,80 @@ +From 2e02291fa5ebc16dc577681b6be27ad0ade26849 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 24 Oct 2023 15:23:05 -0700 +Subject: perf machine: Avoid out of bounds LBR memory read + +From: Ian Rogers + +[ Upstream commit ab8ce150781d326c6bfbe1e09f175ffde1186f80 ] + +Running perf top with address sanitizer and "--call-graph=lbr" fails +due to reading sample 0 when no samples exist. Add a guard to prevent +this. + +Fixes: e2b23483eb1d ("perf machine: Factor out lbr_callchain_add_lbr_ip()") +Signed-off-by: Ian Rogers +Cc: K Prateek Nayak +Cc: Ravi Bangoria +Cc: Sandipan Das +Cc: Anshuman Khandual +Cc: German Gomez +Cc: James Clark +Cc: Nick Terrell +Cc: Sean Christopherson +Cc: Changbin Du +Cc: liuwenyu +Cc: Yang Jihong +Cc: Masami Hiramatsu +Cc: Miguel Ojeda +Cc: Song Liu +Cc: Leo Yan +Cc: Kajol Jain +Cc: Andi Kleen +Cc: Kan Liang +Cc: Athira Rajeev +Cc: Yanteng Si +Cc: Liam Howlett +Cc: Paolo Bonzini +Link: https://lore.kernel.org/r/20231024222353.3024098-3-irogers@google.com +Signed-off-by: Namhyung Kim +Signed-off-by: Sasha Levin +--- + tools/perf/util/machine.c | 22 ++++++++++++---------- + 1 file changed, 12 insertions(+), 10 deletions(-) + +diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c +index df515cd8d0184..eec926c313b13 100644 +--- a/tools/perf/util/machine.c ++++ b/tools/perf/util/machine.c +@@ -2387,16 +2387,18 @@ static int lbr_callchain_add_lbr_ip(struct thread *thread, + save_lbr_cursor_node(thread, cursor, i); + } + +- /* Add LBR ip from first entries.to */ +- ip = entries[0].to; +- flags = &entries[0].flags; +- *branch_from = entries[0].from; +- err = add_callchain_ip(thread, cursor, parent, +- root_al, &cpumode, ip, +- true, flags, NULL, +- *branch_from); +- if (err) +- return err; ++ if (lbr_nr > 0) { ++ /* Add LBR ip from first entries.to */ ++ ip = entries[0].to; ++ flags = &entries[0].flags; ++ *branch_from = entries[0].from; ++ err = add_callchain_ip(thread, cursor, parent, ++ root_al, &cpumode, ip, ++ true, flags, NULL, ++ *branch_from); ++ if (err) ++ return err; ++ } + + return 0; + } +-- +2.42.0 + diff --git a/queue-5.10/perf-tools-get-rid-of-evlist__add_on_all_cpus.patch b/queue-5.10/perf-tools-get-rid-of-evlist__add_on_all_cpus.patch new file mode 100644 index 00000000000..f053b353040 --- /dev/null +++ b/queue-5.10/perf-tools-get-rid-of-evlist__add_on_all_cpus.patch @@ -0,0 +1,81 @@ +From 3627fba55acc8e51663896cb8718e6431c364cd6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 3 Oct 2022 13:46:45 -0700 +Subject: perf tools: Get rid of evlist__add_on_all_cpus() + +From: Namhyung Kim + +[ Upstream commit 60ea006f72512fd7c36f16cdbe91f4fc284f8115 ] + +The cpu and thread maps are properly handled in libperf now. No need to +do it in the perf tools anymore. Let's remove the logic. + +Reviewed-by: Adrian Hunter +Signed-off-by: Namhyung Kim +Cc: Ian Rogers +Cc: Ingo Molnar +Cc: Jiri Olsa +Cc: Kan Liang +Cc: Leo Yan +Cc: Peter Zijlstra +Link: https://lore.kernel.org/r/20221003204647.1481128-4-namhyung@kernel.org +Signed-off-by: Arnaldo Carvalho de Melo +Stable-dep-of: f9cdeb58a9cf ("perf evlist: Avoid frequency mode for the dummy event") +Signed-off-by: Sasha Levin +--- + tools/perf/util/evlist.c | 29 ++--------------------------- + 1 file changed, 2 insertions(+), 27 deletions(-) + +diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c +index 117420abdc325..f0ca9aa7c208e 100644 +--- a/tools/perf/util/evlist.c ++++ b/tools/perf/util/evlist.c +@@ -261,28 +261,6 @@ int evlist__add_dummy(struct evlist *evlist) + return 0; + } + +-static void evlist__add_on_all_cpus(struct evlist *evlist, struct evsel *evsel) +-{ +- evsel->core.system_wide = true; +- +- /* +- * All CPUs. +- * +- * Note perf_event_open() does not accept CPUs that are not online, so +- * in fact this CPU list will include only all online CPUs. +- */ +- perf_cpu_map__put(evsel->core.own_cpus); +- evsel->core.own_cpus = perf_cpu_map__new(NULL); +- perf_cpu_map__put(evsel->core.cpus); +- evsel->core.cpus = perf_cpu_map__get(evsel->core.own_cpus); +- +- /* No threads */ +- perf_thread_map__put(evsel->core.threads); +- evsel->core.threads = perf_thread_map__new_dummy(); +- +- evlist__add(evlist, evsel); +-} +- + struct evsel *evlist__add_aux_dummy(struct evlist *evlist, bool system_wide) + { + struct evsel *evsel = evlist__dummy_event(evlist); +@@ -295,14 +273,11 @@ struct evsel *evlist__add_aux_dummy(struct evlist *evlist, bool system_wide) + evsel->core.attr.exclude_hv = 1; + evsel->core.attr.freq = 0; + evsel->core.attr.sample_period = 1; ++ evsel->core.system_wide = system_wide; + evsel->no_aux_samples = true; + evsel->name = strdup("dummy:u"); + +- if (system_wide) +- evlist__add_on_all_cpus(evlist, evsel); +- else +- evlist__add(evlist, evsel); +- ++ evlist__add(evlist, evsel); + return evsel; + } + +-- +2.42.0 + diff --git a/queue-5.10/platform-x86-wmi-fix-opening-of-char-device.patch b/queue-5.10/platform-x86-wmi-fix-opening-of-char-device.patch new file mode 100644 index 00000000000..65e616e154b --- /dev/null +++ b/queue-5.10/platform-x86-wmi-fix-opening-of-char-device.patch @@ -0,0 +1,69 @@ +From 9505f38283e350a0acbfef15a1ec60934dadd51d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 Oct 2023 23:10:04 +0200 +Subject: platform/x86: wmi: Fix opening of char device +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Armin Wolf + +[ Upstream commit eba9ac7abab91c8f6d351460239108bef5e7a0b6 ] + +Since commit fa1f68db6ca7 ("drivers: misc: pass miscdevice pointer via +file private data"), the miscdevice stores a pointer to itself inside +filp->private_data, which means that private_data will not be NULL when +wmi_char_open() is called. This might cause memory corruption should +wmi_char_open() be unable to find its driver, something which can +happen when the associated WMI device is deleted in wmi_free_devices(). + +Fix the problem by using the miscdevice pointer to retrieve the WMI +device data associated with a char device using container_of(). This +also avoids wmi_char_open() picking a wrong WMI device bound to a +driver with the same name as the original driver. + +Fixes: 44b6b7661132 ("platform/x86: wmi: create userspace interface for drivers") +Signed-off-by: Armin Wolf +Link: https://lore.kernel.org/r/20231020211005.38216-5-W_Armin@gmx.de +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +Signed-off-by: Sasha Levin +--- + drivers/platform/x86/wmi.c | 20 ++++++-------------- + 1 file changed, 6 insertions(+), 14 deletions(-) + +diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c +index 6f8145520bcee..62c673660c9a5 100644 +--- a/drivers/platform/x86/wmi.c ++++ b/drivers/platform/x86/wmi.c +@@ -820,21 +820,13 @@ static int wmi_dev_match(struct device *dev, struct device_driver *driver) + } + static int wmi_char_open(struct inode *inode, struct file *filp) + { +- const char *driver_name = filp->f_path.dentry->d_iname; +- struct wmi_block *wblock; +- struct wmi_block *next; +- +- list_for_each_entry_safe(wblock, next, &wmi_block_list, list) { +- if (!wblock->dev.dev.driver) +- continue; +- if (strcmp(driver_name, wblock->dev.dev.driver->name) == 0) { +- filp->private_data = wblock; +- break; +- } +- } ++ /* ++ * The miscdevice already stores a pointer to itself ++ * inside filp->private_data ++ */ ++ struct wmi_block *wblock = container_of(filp->private_data, struct wmi_block, char_dev); + +- if (!filp->private_data) +- return -ENODEV; ++ filp->private_data = wblock; + + return nonseekable_open(inode, filp); + } +-- +2.42.0 + diff --git a/queue-5.10/platform-x86-wmi-fix-probe-failure-when-failing-to-r.patch b/queue-5.10/platform-x86-wmi-fix-probe-failure-when-failing-to-r.patch new file mode 100644 index 00000000000..0b34bf06bbe --- /dev/null +++ b/queue-5.10/platform-x86-wmi-fix-probe-failure-when-failing-to-r.patch @@ -0,0 +1,84 @@ +From cee2f3b78364f0129535e8247d0137bc754704ed Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 Oct 2023 23:10:03 +0200 +Subject: platform/x86: wmi: Fix probe failure when failing to register WMI + devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Armin Wolf + +[ Upstream commit ed85891a276edaf7a867de0e9acd0837bc3008f2 ] + +When a WMI device besides the first one somehow fails to register, +retval is returned while still containing a negative error code. This +causes the ACPI device fail to probe, leaving behind zombie WMI devices +leading to various errors later. + +Handle the single error path separately and return 0 unconditionally +after trying to register all WMI devices to solve the issue. Also +continue to register WMI devices even if some fail to allocate memory. + +Fixes: 6ee50aaa9a20 ("platform/x86: wmi: Instantiate all devices before adding them") +Signed-off-by: Armin Wolf +Link: https://lore.kernel.org/r/20231020211005.38216-4-W_Armin@gmx.de +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +Signed-off-by: Sasha Levin +--- + drivers/platform/x86/wmi.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c +index 567c28705cb1b..404fe3cac4cc5 100644 +--- a/drivers/platform/x86/wmi.c ++++ b/drivers/platform/x86/wmi.c +@@ -1157,8 +1157,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) + struct wmi_block *wblock, *next; + union acpi_object *obj; + acpi_status status; +- int retval = 0; + u32 i, total; ++ int retval; + + status = acpi_evaluate_object(device->handle, "_WDG", NULL, &out); + if (ACPI_FAILURE(status)) +@@ -1169,8 +1169,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) + return -ENXIO; + + if (obj->type != ACPI_TYPE_BUFFER) { +- retval = -ENXIO; +- goto out_free_pointer; ++ kfree(obj); ++ return -ENXIO; + } + + gblock = (const struct guid_block *)obj->buffer.pointer; +@@ -1191,8 +1191,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) + + wblock = kzalloc(sizeof(struct wmi_block), GFP_KERNEL); + if (!wblock) { +- retval = -ENOMEM; +- break; ++ dev_err(wmi_bus_dev, "Failed to allocate %pUL\n", &gblock[i].guid); ++ continue; + } + + wblock->acpi_device = device; +@@ -1231,9 +1231,9 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) + } + } + +-out_free_pointer: +- kfree(out.pointer); +- return retval; ++ kfree(obj); ++ ++ return 0; + } + + /* +-- +2.42.0 + diff --git a/queue-5.10/platform-x86-wmi-remove-unnecessary-initializations.patch b/queue-5.10/platform-x86-wmi-remove-unnecessary-initializations.patch new file mode 100644 index 00000000000..389f348a21b --- /dev/null +++ b/queue-5.10/platform-x86-wmi-remove-unnecessary-initializations.patch @@ -0,0 +1,94 @@ +From b973a27c2971f4de89f279e163721ce6156cd979 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 4 Sep 2021 17:55:10 +0000 +Subject: platform/x86: wmi: remove unnecessary initializations +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Barnabás Pőcze + +[ Upstream commit 43aacf838ef7384d985ef5385ecb0124f8c70007 ] + +Some pointers are initialized when they are defined, +but they are almost immediately reassigned in the +following lines. Remove these superfluous assignments. + +Signed-off-by: Barnabás Pőcze +Link: https://lore.kernel.org/r/20210904175450.156801-6-pobrn@protonmail.com +Reviewed-by: Hans de Goede +Signed-off-by: Hans de Goede +Stable-dep-of: eba9ac7abab9 ("platform/x86: wmi: Fix opening of char device") +Signed-off-by: Sasha Levin +--- + drivers/platform/x86/wmi.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c +index 404fe3cac4cc5..6f8145520bcee 100644 +--- a/drivers/platform/x86/wmi.c ++++ b/drivers/platform/x86/wmi.c +@@ -185,7 +185,7 @@ static int get_subobj_info(acpi_handle handle, const char *pathname, + + static acpi_status wmi_method_enable(struct wmi_block *wblock, int enable) + { +- struct guid_block *block = NULL; ++ struct guid_block *block; + char method[5]; + acpi_status status; + acpi_handle handle; +@@ -259,8 +259,8 @@ EXPORT_SYMBOL_GPL(wmi_evaluate_method); + acpi_status wmidev_evaluate_method(struct wmi_device *wdev, u8 instance, + u32 method_id, const struct acpi_buffer *in, struct acpi_buffer *out) + { +- struct guid_block *block = NULL; +- struct wmi_block *wblock = NULL; ++ struct guid_block *block; ++ struct wmi_block *wblock; + acpi_handle handle; + acpi_status status; + struct acpi_object_list input; +@@ -307,7 +307,7 @@ EXPORT_SYMBOL_GPL(wmidev_evaluate_method); + static acpi_status __query_block(struct wmi_block *wblock, u8 instance, + struct acpi_buffer *out) + { +- struct guid_block *block = NULL; ++ struct guid_block *block; + acpi_handle handle; + acpi_status status, wc_status = AE_ERROR; + struct acpi_object_list input; +@@ -420,8 +420,8 @@ EXPORT_SYMBOL_GPL(wmidev_block_query); + acpi_status wmi_set_block(const char *guid_string, u8 instance, + const struct acpi_buffer *in) + { +- struct guid_block *block = NULL; + struct wmi_block *wblock = NULL; ++ struct guid_block *block; + acpi_handle handle; + struct acpi_object_list input; + union acpi_object params[2]; +@@ -821,8 +821,8 @@ static int wmi_dev_match(struct device *dev, struct device_driver *driver) + static int wmi_char_open(struct inode *inode, struct file *filp) + { + const char *driver_name = filp->f_path.dentry->d_iname; +- struct wmi_block *wblock = NULL; +- struct wmi_block *next = NULL; ++ struct wmi_block *wblock; ++ struct wmi_block *next; + + list_for_each_entry_safe(wblock, next, &wmi_block_list, list) { + if (!wblock->dev.dev.driver) +@@ -854,8 +854,8 @@ static long wmi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) + struct wmi_ioctl_buffer __user *input = + (struct wmi_ioctl_buffer __user *) arg; + struct wmi_block *wblock = filp->private_data; +- struct wmi_ioctl_buffer *buf = NULL; +- struct wmi_driver *wdriver = NULL; ++ struct wmi_ioctl_buffer *buf; ++ struct wmi_driver *wdriver; + int ret; + + if (_IOC_TYPE(cmd) != WMI_IOC) +-- +2.42.0 + diff --git a/queue-5.10/pm-devfreq-rockchip-dfi-make-pmu-regmap-mandatory.patch b/queue-5.10/pm-devfreq-rockchip-dfi-make-pmu-regmap-mandatory.patch new file mode 100644 index 00000000000..edce504eb10 --- /dev/null +++ b/queue-5.10/pm-devfreq-rockchip-dfi-make-pmu-regmap-mandatory.patch @@ -0,0 +1,53 @@ +From 715cb32453e9403b2ea2a32fc59edd464231c07b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Jul 2023 11:32:17 +0200 +Subject: PM / devfreq: rockchip-dfi: Make pmu regmap mandatory + +From: Sascha Hauer + +[ Upstream commit 1e0731c05c985deb68a97fa44c1adcd3305dda90 ] + +As a matter of fact the regmap_pmu already is mandatory because +it is used unconditionally in the driver. Bail out gracefully in +probe() rather than crashing later. + +Link: https://lore.kernel.org/lkml/20230704093242.583575-2-s.hauer@pengutronix.de/ +Fixes: b9d1262bca0af ("PM / devfreq: event: support rockchip dfi controller") +Reviewed-by: Sebastian Reichel +Signed-off-by: Sascha Hauer +Signed-off-by: Chanwoo Choi +Signed-off-by: Sasha Levin +--- + drivers/devfreq/event/rockchip-dfi.c | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c +index 9a88faaf8b27f..4dafdf23197b9 100644 +--- a/drivers/devfreq/event/rockchip-dfi.c ++++ b/drivers/devfreq/event/rockchip-dfi.c +@@ -194,14 +194,15 @@ static int rockchip_dfi_probe(struct platform_device *pdev) + return PTR_ERR(data->clk); + } + +- /* try to find the optional reference to the pmu syscon */ + node = of_parse_phandle(np, "rockchip,pmu", 0); +- if (node) { +- data->regmap_pmu = syscon_node_to_regmap(node); +- of_node_put(node); +- if (IS_ERR(data->regmap_pmu)) +- return PTR_ERR(data->regmap_pmu); +- } ++ if (!node) ++ return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n"); ++ ++ data->regmap_pmu = syscon_node_to_regmap(node); ++ of_node_put(node); ++ if (IS_ERR(data->regmap_pmu)) ++ return PTR_ERR(data->regmap_pmu); ++ + data->dev = dev; + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); +-- +2.42.0 + diff --git a/queue-5.10/powerpc-40x-remove-stale-pte_atomic_updates-macro.patch b/queue-5.10/powerpc-40x-remove-stale-pte_atomic_updates-macro.patch new file mode 100644 index 00000000000..cf184907430 --- /dev/null +++ b/queue-5.10/powerpc-40x-remove-stale-pte_atomic_updates-macro.patch @@ -0,0 +1,44 @@ +From 07e97d99abb83a6473d4a2cafac243a7040d7be7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 25 Sep 2023 20:31:17 +0200 +Subject: powerpc/40x: Remove stale PTE_ATOMIC_UPDATES macro + +From: Christophe Leroy + +[ Upstream commit cc8ee288f484a2a59c01ccd4d8a417d6ed3466e3 ] + +40x TLB handlers were reworked by commit 2c74e2586bb9 ("powerpc/40x: +Rework 40x PTE access and TLB miss") to not require PTE_ATOMIC_UPDATES +anymore. + +Then commit 4e1df545e2fa ("powerpc/pgtable: Drop PTE_ATOMIC_UPDATES") +removed all code related to PTE_ATOMIC_UPDATES. + +Remove left over PTE_ATOMIC_UPDATES macro. + +Fixes: 2c74e2586bb9 ("powerpc/40x: Rework 40x PTE access and TLB miss") +Signed-off-by: Christophe Leroy +Signed-off-by: Michael Ellerman +Link: https://msgid.link/f061db5857fcd748f84a6707aad01754686ce97e.1695659959.git.christophe.leroy@csgroup.eu +Signed-off-by: Sasha Levin +--- + arch/powerpc/include/asm/nohash/32/pte-40x.h | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/arch/powerpc/include/asm/nohash/32/pte-40x.h b/arch/powerpc/include/asm/nohash/32/pte-40x.h +index 2d3153cfc0d79..acf61242e85bf 100644 +--- a/arch/powerpc/include/asm/nohash/32/pte-40x.h ++++ b/arch/powerpc/include/asm/nohash/32/pte-40x.h +@@ -69,9 +69,6 @@ + + #define _PTE_NONE_MASK 0 + +-/* Until my rework is finished, 40x still needs atomic PTE updates */ +-#define PTE_ATOMIC_UPDATES 1 +- + #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) + #define _PAGE_BASE (_PAGE_BASE_NC) + +-- +2.42.0 + diff --git a/queue-5.10/powerpc-imc-pmu-use-the-correct-spinlock-initializer.patch b/queue-5.10/powerpc-imc-pmu-use-the-correct-spinlock-initializer.patch new file mode 100644 index 00000000000..1829a864545 --- /dev/null +++ b/queue-5.10/powerpc-imc-pmu-use-the-correct-spinlock-initializer.patch @@ -0,0 +1,40 @@ +From 2c56a3e944af4c605260794cb480ff9c222b2ee3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Mar 2023 14:48:31 +0100 +Subject: powerpc/imc-pmu: Use the correct spinlock initializer. + +From: Sebastian Andrzej Siewior + +[ Upstream commit 007240d59c11f87ac4f6cfc6a1d116630b6b634c ] + +The macro __SPIN_LOCK_INITIALIZER() is implementation specific. Users +that desire to initialize a spinlock in a struct must use +__SPIN_LOCK_UNLOCKED(). + +Use __SPIN_LOCK_UNLOCKED() for the spinlock_t in imc_global_refc. + +Fixes: 76d588dddc459 ("powerpc/imc-pmu: Fix use of mutex in IRQs disabled section") +Signed-off-by: Sebastian Andrzej Siewior +Signed-off-by: Michael Ellerman +Link: https://msgid.link/20230309134831.Nz12nqsU@linutronix.de +Signed-off-by: Sasha Levin +--- + arch/powerpc/perf/imc-pmu.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c +index b773c411aa5c2..3e15d0d054b2d 100644 +--- a/arch/powerpc/perf/imc-pmu.c ++++ b/arch/powerpc/perf/imc-pmu.c +@@ -50,7 +50,7 @@ static int trace_imc_mem_size; + * core and trace-imc + */ + static struct imc_pmu_ref imc_global_refc = { +- .lock = __SPIN_LOCK_INITIALIZER(imc_global_refc.lock), ++ .lock = __SPIN_LOCK_UNLOCKED(imc_global_refc.lock), + .id = 0, + .refc = 0, + }; +-- +2.42.0 + diff --git a/queue-5.10/powerpc-pseries-fix-potential-memory-leak-in-init_cp.patch b/queue-5.10/powerpc-pseries-fix-potential-memory-leak-in-init_cp.patch new file mode 100644 index 00000000000..2e5a5098e36 --- /dev/null +++ b/queue-5.10/powerpc-pseries-fix-potential-memory-leak-in-init_cp.patch @@ -0,0 +1,43 @@ +From 3640fd6e9fce5b12b9f7799b711ff766969fafbe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 14 Dec 2022 15:46:23 +0800 +Subject: powerpc/pseries: fix potential memory leak in + init_cpu_associativity() + +From: Wang Yufen + +[ Upstream commit 95f1a128cd728a7257d78e868f1f5a145fc43736 ] + +If the vcpu_associativity alloc memory successfully but the +pcpu_associativity fails to alloc memory, the vcpu_associativity +memory leaks. + +Fixes: d62c8deeb6e6 ("powerpc/pseries: Provide vcpu dispatch statistics") +Signed-off-by: Wang Yufen +Reviewed-by: "Naveen N. Rao" +Signed-off-by: Michael Ellerman +Link: https://msgid.link/1671003983-10794-1-git-send-email-wangyufen@huawei.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/platforms/pseries/lpar.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c +index 68f3b082245e0..4a3425fb19398 100644 +--- a/arch/powerpc/platforms/pseries/lpar.c ++++ b/arch/powerpc/platforms/pseries/lpar.c +@@ -523,8 +523,10 @@ static ssize_t vcpudispatch_stats_write(struct file *file, const char __user *p, + + if (cmd) { + rc = init_cpu_associativity(); +- if (rc) ++ if (rc) { ++ destroy_cpu_associativity(); + goto out; ++ } + + for_each_possible_cpu(cpu) { + disp = per_cpu_ptr(&vcpu_disp_data, cpu); +-- +2.42.0 + diff --git a/queue-5.10/powerpc-xive-fix-endian-conversion-size.patch b/queue-5.10/powerpc-xive-fix-endian-conversion-size.patch new file mode 100644 index 00000000000..b73f12da191 --- /dev/null +++ b/queue-5.10/powerpc-xive-fix-endian-conversion-size.patch @@ -0,0 +1,41 @@ +From 334fce87f3fa0fb81a75e7b884ab23883e95a6b2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 11 Oct 2023 16:37:00 +1100 +Subject: powerpc/xive: Fix endian conversion size + +From: Benjamin Gray + +[ Upstream commit ff7a60ab1e065257a0e467c13b519f4debcd7fcf ] + +Sparse reports a size mismatch in the endian swap. The Opal +implementation[1] passes the value as a __be64, and the receiving +variable out_qsize is a u64, so the use of be32_to_cpu() appears to be +an error. + +[1]: https://github.com/open-power/skiboot/blob/80e2b1dc73/hw/xive.c#L3854 + +Fixes: 88ec6b93c8e7 ("powerpc/xive: add OPAL extensions for the XIVE native exploitation support") +Signed-off-by: Benjamin Gray +Signed-off-by: Michael Ellerman +Link: https://msgid.link/20231011053711.93427-2-bgray@linux.ibm.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/sysdev/xive/native.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c +index cb58ec7ce77ac..1c7e49d9eaeea 100644 +--- a/arch/powerpc/sysdev/xive/native.c ++++ b/arch/powerpc/sysdev/xive/native.c +@@ -779,7 +779,7 @@ int xive_native_get_queue_info(u32 vp_id, u32 prio, + if (out_qpage) + *out_qpage = be64_to_cpu(qpage); + if (out_qsize) +- *out_qsize = be32_to_cpu(qsize); ++ *out_qsize = be64_to_cpu(qsize); + if (out_qeoi_page) + *out_qeoi_page = be64_to_cpu(qeoi_page); + if (out_escalate_irq) +-- +2.42.0 + diff --git a/queue-5.10/pstore-platform-add-check-for-kstrdup.patch b/queue-5.10/pstore-platform-add-check-for-kstrdup.patch new file mode 100644 index 00000000000..79d2ec6d750 --- /dev/null +++ b/queue-5.10/pstore-platform-add-check-for-kstrdup.patch @@ -0,0 +1,63 @@ +From a57883acfc07f3915d8897ebd4727c92f4f6c71a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 23 Jun 2023 10:27:06 +0800 +Subject: pstore/platform: Add check for kstrdup + +From: Jiasheng Jiang + +[ Upstream commit a19d48f7c5d57c0f0405a7d4334d1d38fe9d3c1c ] + +Add check for the return value of kstrdup() and return the error +if it fails in order to avoid NULL pointer dereference. + +Fixes: 563ca40ddf40 ("pstore/platform: Switch pstore_info::name to const") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/20230623022706.32125-1-jiasheng@iscas.ac.cn +Signed-off-by: Kees Cook +Signed-off-by: Sasha Levin +--- + fs/pstore/platform.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/fs/pstore/platform.c b/fs/pstore/platform.c +index ce03c3dbb5c30..d59f13b1fb96b 100644 +--- a/fs/pstore/platform.c ++++ b/fs/pstore/platform.c +@@ -558,6 +558,8 @@ static int pstore_write_user_compat(struct pstore_record *record, + */ + int pstore_register(struct pstore_info *psi) + { ++ char *new_backend; ++ + if (backend && strcmp(backend, psi->name)) { + pr_warn("ignoring unexpected backend '%s'\n", psi->name); + return -EPERM; +@@ -577,11 +579,16 @@ int pstore_register(struct pstore_info *psi) + return -EINVAL; + } + ++ new_backend = kstrdup(psi->name, GFP_KERNEL); ++ if (!new_backend) ++ return -ENOMEM; ++ + mutex_lock(&psinfo_lock); + if (psinfo) { + pr_warn("backend '%s' already loaded: ignoring '%s'\n", + psinfo->name, psi->name); + mutex_unlock(&psinfo_lock); ++ kfree(new_backend); + return -EBUSY; + } + +@@ -614,7 +621,7 @@ int pstore_register(struct pstore_info *psi) + * Update the module parameter backend, so it is visible + * through /sys/module/pstore/parameters/backend + */ +- backend = kstrdup(psi->name, GFP_KERNEL); ++ backend = new_backend; + + pr_info("Registered %s as persistent store backend\n", psi->name); + +-- +2.42.0 + diff --git a/queue-5.10/r8169-fix-rare-issue-with-broken-rx-after-link-down-.patch b/queue-5.10/r8169-fix-rare-issue-with-broken-rx-after-link-down-.patch new file mode 100644 index 00000000000..4e585dc55ce --- /dev/null +++ b/queue-5.10/r8169-fix-rare-issue-with-broken-rx-after-link-down-.patch @@ -0,0 +1,52 @@ +From 595b46bc6251661107ac44ab766c3454ab313b95 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 12 Oct 2023 08:51:13 +0200 +Subject: r8169: fix rare issue with broken rx after link-down on RTL8125 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Heiner Kallweit + +[ Upstream commit 621735f590643e3048ca2060c285b80551660601 ] + +In very rare cases (I've seen two reports so far about different +RTL8125 chip versions) it seems the MAC locks up when link goes down +and requires a software reset to get revived. +Realtek doesn't publish hw errata information, therefore the root cause +is unknown. Realtek vendor drivers do a full hw re-initialization on +each link-up event, the slimmed-down variant here was reported to fix +the issue for the reporting user. +It's not fully clear which parts of the NIC are reset as part of the +software reset, therefore I can't rule out side effects. + +Fixes: f1bce4ad2f1c ("r8169: add support for RTL8125") +Reported-by: Martin Kjær Jørgensen +Link: https://lore.kernel.org/netdev/97ec2232-3257-316c-c3e7-a08192ce16a6@gmail.com/T/ +Signed-off-by: Heiner Kallweit +Link: https://lore.kernel.org/r/9edde757-9c3b-4730-be3b-0ef3a374ff71@gmail.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 4fb204962a11c..9a920e0677e54 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4693,7 +4693,11 @@ static void r8169_phylink_handler(struct net_device *ndev) + if (netif_carrier_ok(ndev)) { + rtl_link_chg_patch(tp); + pm_request_resume(d); ++ netif_wake_queue(tp->dev); + } else { ++ /* In few cases rx is broken after link-down otherwise */ ++ if (rtl_is_8125(tp)) ++ rtl_reset_work(tp); + pm_runtime_idle(d); + } + +-- +2.42.0 + diff --git a/queue-5.10/r8169-use-tp_to_dev-instead-of-open-code.patch b/queue-5.10/r8169-use-tp_to_dev-instead-of-open-code.patch new file mode 100644 index 00000000000..b4b1c216267 --- /dev/null +++ b/queue-5.10/r8169-use-tp_to_dev-instead-of-open-code.patch @@ -0,0 +1,49 @@ +From af734e3f283eac481e233a17e41d11b4bc5d2ac9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 30 Nov 2022 01:12:44 +0900 +Subject: r8169: use tp_to_dev instead of open code + +From: Juhee Kang + +[ Upstream commit 4b6c6065fca123d419afef005a696f51e6590470 ] + +The open code is defined as a helper function(tp_to_dev) on r8169_main.c, +which the open code is &tp->pci_dev->dev. The helper function was added +in commit 1e1205b7d3e9 ("r8169: add helper tp_to_dev"). And then later, +commit f1e911d5d0df ("r8169: add basic phylib support") added +r8169_phylink_handler function but it didn't use the helper function. +Thus, tp_to_dev() replaces the open code. This patch doesn't change logic. + +Signed-off-by: Juhee Kang +Reviewed-by: Heiner Kallweit +Link: https://lore.kernel.org/r/20221129161244.5356-1-claudiajkang@gmail.com +Signed-off-by: Paolo Abeni +Stable-dep-of: 621735f59064 ("r8169: fix rare issue with broken rx after link-down on RTL8125") +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 37e34d8f7946e..4fb204962a11c 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4688,12 +4688,13 @@ static int rtl8169_poll(struct napi_struct *napi, int budget) + static void r8169_phylink_handler(struct net_device *ndev) + { + struct rtl8169_private *tp = netdev_priv(ndev); ++ struct device *d = tp_to_dev(tp); + + if (netif_carrier_ok(ndev)) { + rtl_link_chg_patch(tp); +- pm_request_resume(&tp->pci_dev->dev); ++ pm_request_resume(d); + } else { +- pm_runtime_idle(&tp->pci_dev->dev); ++ pm_runtime_idle(d); + } + + if (net_ratelimit()) +-- +2.42.0 + diff --git a/queue-5.10/rdma-hfi1-workaround-truncation-compilation-error.patch b/queue-5.10/rdma-hfi1-workaround-truncation-compilation-error.patch new file mode 100644 index 00000000000..444a2072ee6 --- /dev/null +++ b/queue-5.10/rdma-hfi1-workaround-truncation-compilation-error.patch @@ -0,0 +1,57 @@ +From 1b4171c12d0b5e75c16a4cb2e056b2403d33dcee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 24 Oct 2023 18:07:31 +0300 +Subject: RDMA/hfi1: Workaround truncation compilation error +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Leon Romanovsky + +[ Upstream commit d4b2d165714c0ce8777d5131f6e0aad617b7adc4 ] + +Increase name array to be large enough to overcome the following +compilation error. + +drivers/infiniband/hw/hfi1/efivar.c: In function ‘read_hfi1_efi_var’: +drivers/infiniband/hw/hfi1/efivar.c:124:44: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] + 124 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); + | ^ +drivers/infiniband/hw/hfi1/efivar.c:124:9: note: ‘snprintf’ output 2 or more bytes (assuming 65) into a destination of size 64 + 124 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +drivers/infiniband/hw/hfi1/efivar.c:133:52: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] + 133 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); + | ^ +drivers/infiniband/hw/hfi1/efivar.c:133:17: note: ‘snprintf’ output 2 or more bytes (assuming 65) into a destination of size 64 + 133 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +cc1: all warnings being treated as errors +make[6]: *** [scripts/Makefile.build:243: drivers/infiniband/hw/hfi1/efivar.o] Error 1 + +Fixes: c03c08d50b3d ("IB/hfi1: Check upper-case EFI variables") +Signed-off-by: Leon Romanovsky +Link: https://lore.kernel.org/r/238fa39a8fd60e87a5ad7e1ca6584fcdf32e9519.1698159993.git.leonro@nvidia.com +Acked-by: Dennis Dalessandro +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/hw/hfi1/efivar.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/infiniband/hw/hfi1/efivar.c b/drivers/infiniband/hw/hfi1/efivar.c +index c22ab7b5163b3..49b2c751197e2 100644 +--- a/drivers/infiniband/hw/hfi1/efivar.c ++++ b/drivers/infiniband/hw/hfi1/efivar.c +@@ -152,7 +152,7 @@ int read_hfi1_efi_var(struct hfi1_devdata *dd, const char *kind, + unsigned long *size, void **return_data) + { + char prefix_name[64]; +- char name[64]; ++ char name[128]; + int result; + int i; + +-- +2.42.0 + diff --git a/queue-5.10/rdma-hns-fix-signed-unsigned-mixed-comparisons.patch b/queue-5.10/rdma-hns-fix-signed-unsigned-mixed-comparisons.patch new file mode 100644 index 00000000000..6eada84f51a --- /dev/null +++ b/queue-5.10/rdma-hns-fix-signed-unsigned-mixed-comparisons.patch @@ -0,0 +1,41 @@ +From 2e6011ea9e3681f5164f4a243ffc20da16c1369c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 17 Oct 2023 20:52:35 +0800 +Subject: RDMA/hns: Fix signed-unsigned mixed comparisons + +From: Chengchang Tang + +[ Upstream commit b5f9efff101b06fd06a5e280a2b00b1335f5f476 ] + +The ib_mtu_enum_to_int() and uverbs_attr_get_len() may returns a negative +value. In this case, mixed comparisons of signed and unsigned types will +throw wrong results. + +This patch adds judgement for this situation. + +Fixes: 30b707886aeb ("RDMA/hns: Support inline data in extented sge space for RC") +Signed-off-by: Chengchang Tang +Signed-off-by: Junxian Huang +Link: https://lore.kernel.org/r/20231017125239.164455-4-huangjunxian6@hisilicon.com +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +index 322f341f41458..518b38e9158d4 100644 +--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c ++++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +@@ -247,7 +247,7 @@ static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) + struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); + int mtu = ib_mtu_enum_to_int(qp->path_mtu); + +- if (len > qp->max_inline_data || len > mtu) { ++ if (mtu < 0 || len > qp->max_inline_data || len > mtu) { + ibdev_err(&hr_dev->ib_dev, + "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", + len, qp->max_inline_data, mtu); +-- +2.42.0 + diff --git a/queue-5.10/rdma-hns-fix-uninitialized-ucmd-in-hns_roce_create_q.patch b/queue-5.10/rdma-hns-fix-uninitialized-ucmd-in-hns_roce_create_q.patch new file mode 100644 index 00000000000..d78ddd0f7d4 --- /dev/null +++ b/queue-5.10/rdma-hns-fix-uninitialized-ucmd-in-hns_roce_create_q.patch @@ -0,0 +1,44 @@ +From 9ed55a2e5d2fe6e86f9645279d544fc97f820499 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 17 Oct 2023 20:52:34 +0800 +Subject: RDMA/hns: Fix uninitialized ucmd in hns_roce_create_qp_common() + +From: Chengchang Tang + +[ Upstream commit c64e9710f9241e38a1c761ed1c1a30854784da66 ] + +ucmd in hns_roce_create_qp_common() are not initialized. But it works fine +until new member sdb_addr is added to struct hns_roce_ib_create_qp. + +If the user-mode driver uses an old version ABI, then the value of the new +member will be undefined after ib_copy_from_udata(). + +This patch fixes it by initialize this variable to 0. And the default value +of the new member sdb_addr will be 0 which is invalid. + +Fixes: 0425e3e6e0c7 ("RDMA/hns: Support flush cqe for hip08 in kernel space") +Signed-off-by: Chengchang Tang +Signed-off-by: Junxian Huang +Link: https://lore.kernel.org/r/20231017125239.164455-3-huangjunxian6@hisilicon.com +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/hw/hns/hns_roce_qp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c +index c42c6761382d1..d1c07f1f8fe98 100644 +--- a/drivers/infiniband/hw/hns/hns_roce_qp.c ++++ b/drivers/infiniband/hw/hns/hns_roce_qp.c +@@ -906,7 +906,7 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, + { + struct hns_roce_ib_create_qp_resp resp = {}; + struct ib_device *ibdev = &hr_dev->ib_dev; +- struct hns_roce_ib_create_qp ucmd; ++ struct hns_roce_ib_create_qp ucmd = {}; + int ret; + + mutex_init(&hr_qp->mutex); +-- +2.42.0 + diff --git a/queue-5.10/regmap-debugfs-fix-a-erroneous-check-after-snprintf.patch b/queue-5.10/regmap-debugfs-fix-a-erroneous-check-after-snprintf.patch new file mode 100644 index 00000000000..e9179880ccb --- /dev/null +++ b/queue-5.10/regmap-debugfs-fix-a-erroneous-check-after-snprintf.patch @@ -0,0 +1,37 @@ +From 1842edd3a6ea70e71bc883042c07fc0768b3338a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Sep 2023 22:04:06 +0200 +Subject: regmap: debugfs: Fix a erroneous check after snprintf() + +From: Christophe JAILLET + +[ Upstream commit d3601857e14de6369f00ae19564f1d817d175d19 ] + +This error handling looks really strange. +Check if the string has been truncated instead. + +Fixes: f0c2319f9f19 ("regmap: Expose the driver name in debugfs") +Signed-off-by: Christophe JAILLET +Link: https://lore.kernel.org/r/8595de2462c490561f70020a6d11f4d6b652b468.1693857825.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/base/regmap/regmap-debugfs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c +index 211a335a608d7..ed54dc31e6fd4 100644 +--- a/drivers/base/regmap/regmap-debugfs.c ++++ b/drivers/base/regmap/regmap-debugfs.c +@@ -48,7 +48,7 @@ static ssize_t regmap_name_read_file(struct file *file, + name = map->dev->driver->name; + + ret = snprintf(buf, PAGE_SIZE, "%s\n", name); +- if (ret < 0) { ++ if (ret >= PAGE_SIZE) { + kfree(buf); + return ret; + } +-- +2.42.0 + diff --git a/queue-5.10/regmap-prevent-noinc-writes-from-clobbering-cache.patch b/queue-5.10/regmap-prevent-noinc-writes-from-clobbering-cache.patch new file mode 100644 index 00000000000..bca8e0a1e3f --- /dev/null +++ b/queue-5.10/regmap-prevent-noinc-writes-from-clobbering-cache.patch @@ -0,0 +1,57 @@ +From 67fcbc1721418f39b8b6ebb4435b7b6a46933cba Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 1 Nov 2023 10:29:27 -0400 +Subject: regmap: prevent noinc writes from clobbering cache + +From: Ben Wolsieffer + +[ Upstream commit 984a4afdc87a1fc226fd657b1cd8255c13d3fc1a ] + +Currently, noinc writes are cached as if they were standard incrementing +writes, overwriting unrelated register values in the cache. Instead, we +want to cache the last value written to the register, as is done in the +accelerated noinc handler (regmap_noinc_readwrite). + +Fixes: cdf6b11daa77 ("regmap: Add regmap_noinc_write API") +Signed-off-by: Ben Wolsieffer +Link: https://lore.kernel.org/r/20231101142926.2722603-2-ben.wolsieffer@hefring.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/base/regmap/regmap.c | 16 +++++++++------- + 1 file changed, 9 insertions(+), 7 deletions(-) + +diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c +index 3edff8606ac95..7bc603145bd98 100644 +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -1643,17 +1643,19 @@ static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg, + } + + if (!map->cache_bypass && map->format.parse_val) { +- unsigned int ival; ++ unsigned int ival, offset; + int val_bytes = map->format.val_bytes; +- for (i = 0; i < val_len / val_bytes; i++) { +- ival = map->format.parse_val(val + (i * val_bytes)); +- ret = regcache_write(map, +- reg + regmap_get_offset(map, i), +- ival); ++ ++ /* Cache the last written value for noinc writes */ ++ i = noinc ? val_len - val_bytes : 0; ++ for (; i < val_len; i += val_bytes) { ++ ival = map->format.parse_val(val + i); ++ offset = noinc ? 0 : regmap_get_offset(map, i / val_bytes); ++ ret = regcache_write(map, reg + offset, ival); + if (ret) { + dev_err(map->dev, + "Error in caching of register: %x ret: %d\n", +- reg + regmap_get_offset(map, i), ret); ++ reg + offset, ret); + return ret; + } + } +-- +2.42.0 + diff --git a/queue-5.10/revert-hid-logitech-hidpp-add-a-module-parameter-to-.patch b/queue-5.10/revert-hid-logitech-hidpp-add-a-module-parameter-to-.patch new file mode 100644 index 00000000000..60b95ccbaf9 --- /dev/null +++ b/queue-5.10/revert-hid-logitech-hidpp-add-a-module-parameter-to-.patch @@ -0,0 +1,59 @@ +From f55a5ee48952cede8bf7f88c3389d2ac3c195b88 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Dec 2022 16:43:43 +0100 +Subject: Revert "HID: logitech-hidpp: add a module parameter to keep firmware + gestures" + +From: Bastien Nocera + +[ Upstream commit cae253d6033da885e71c29c1591b22838a52de76 ] + +Now that we're in 2022, and the majority of desktop environments can and +should support touchpad gestures through libinput, remove the legacy +module parameter that made it possible to use gestures implemented in +firmware. + +This will eventually allow simplifying the driver's initialisation code. + +This reverts commit 9188dbaed68a4b23dc96eba165265c08caa7dc2a. + +Signed-off-by: Bastien Nocera +Signed-off-by: Benjamin Tissoires +Link: https://lore.kernel.org/r/20221220154345.474596-1-hadess@hadess.net +Stable-dep-of: 11ca0322a419 ("HID: logitech-hidpp: Don't restart IO, instead defer hid_connect() only") +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-logitech-hidpp.c | 10 ---------- + 1 file changed, 10 deletions(-) + +diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c +index 651fa0966939e..8d81a700886fc 100644 +--- a/drivers/hid/hid-logitech-hidpp.c ++++ b/drivers/hid/hid-logitech-hidpp.c +@@ -31,11 +31,6 @@ MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Benjamin Tissoires "); + MODULE_AUTHOR("Nestor Lopez Casado "); + +-static bool disable_raw_mode; +-module_param(disable_raw_mode, bool, 0644); +-MODULE_PARM_DESC(disable_raw_mode, +- "Disable Raw mode reporting for touchpads and keep firmware gestures."); +- + static bool disable_tap_to_click; + module_param(disable_tap_to_click, bool, 0644); + MODULE_PARM_DESC(disable_tap_to_click, +@@ -3851,11 +3846,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) + hidpp_application_equals(hdev, HID_GD_KEYBOARD)) + hidpp->quirks |= HIDPP_QUIRK_HIDPP_CONSUMER_VENDOR_KEYS; + +- if (disable_raw_mode) { +- hidpp->quirks &= ~HIDPP_QUIRK_CLASS_WTP; +- hidpp->quirks &= ~HIDPP_QUIRK_NO_HIDINPUT; +- } +- + if (hidpp->quirks & HIDPP_QUIRK_CLASS_WTP) { + ret = wtp_allocate(hdev, id); + if (ret) +-- +2.42.0 + diff --git a/queue-5.10/rtc-pcf85363-fix-wrong-mask-val-parameters-in-regmap.patch b/queue-5.10/rtc-pcf85363-fix-wrong-mask-val-parameters-in-regmap.patch new file mode 100644 index 00000000000..51b7b5d0b42 --- /dev/null +++ b/queue-5.10/rtc-pcf85363-fix-wrong-mask-val-parameters-in-regmap.patch @@ -0,0 +1,43 @@ +From 6910cd4e9caef765057416f2ec81786be63ac971 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 13 Oct 2023 16:34:21 +0200 +Subject: rtc: pcf85363: fix wrong mask/val parameters in regmap_update_bits + call + +From: Javier Carrasco + +[ Upstream commit 2be36c09b6b07306be33519e1aa70d2e2a2161bb ] + +The current implementation passes PIN_IO_INTA_OUT (2) as a mask and +PIN_IO_INTAPM (GENMASK(1, 0)) as a value. +Swap the variables to assign mask and value the right way. + +This error was first introduced with the alarm support. For better or +worse it worked as expected because 0x02 was applied as a mask to 0x03, +resulting 0x02 anyway. This will of course not work for any other value. + +Fixes: e5aac267a10a ("rtc: pcf85363: add alarm support") +Signed-off-by: Javier Carrasco +Link: https://lore.kernel.org/r/20231013-topic-pcf85363_regmap_update_bits-v1-1-c454f016f71f@gmail.com +Signed-off-by: Alexandre Belloni +Signed-off-by: Sasha Levin +--- + drivers/rtc/rtc-pcf85363.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c +index 3450d615974d5..bb962dce3ab26 100644 +--- a/drivers/rtc/rtc-pcf85363.c ++++ b/drivers/rtc/rtc-pcf85363.c +@@ -407,7 +407,7 @@ static int pcf85363_probe(struct i2c_client *client, + if (client->irq > 0) { + regmap_write(pcf85363->regmap, CTRL_FLAGS, 0); + regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO, +- PIN_IO_INTA_OUT, PIN_IO_INTAPM); ++ PIN_IO_INTAPM, PIN_IO_INTA_OUT); + ret = devm_request_threaded_irq(&client->dev, client->irq, + NULL, pcf85363_rtc_handle_irq, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, +-- +2.42.0 + diff --git a/queue-5.10/sched-uclamp-ignore-util-0-optimization-in-feec-when.patch b/queue-5.10/sched-uclamp-ignore-util-0-optimization-in-feec-when.patch new file mode 100644 index 00000000000..bbe205c8ead --- /dev/null +++ b/queue-5.10/sched-uclamp-ignore-util-0-optimization-in-feec-when.patch @@ -0,0 +1,73 @@ +From e5f173a89a8e9ce9499060cb9db25a3e39101b42 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 17 Sep 2023 00:29:54 +0100 +Subject: sched/uclamp: Ignore (util == 0) optimization in feec() when + p_util_max = 0 + +From: Qais Yousef + +[ Upstream commit 23c9519def98ee0fa97ea5871535e9b136f522fc ] + +find_energy_efficient_cpu() bails out early if effective util of the +task is 0 as the delta at this point will be zero and there's nothing +for EAS to do. When uclamp is being used, this could lead to wrong +decisions when uclamp_max is set to 0. In this case the task is capped +to performance point 0, but it is actually running and consuming energy +and we can benefit from EAS energy calculations. + +Rework the condition so that it bails out when both util and uclamp_min +are 0. + +We can do that without needing to use uclamp_task_util(); remove it. + +Fixes: d81304bc6193 ("sched/uclamp: Cater for uclamp in find_energy_efficient_cpu()'s early exit condition") +Signed-off-by: Qais Yousef (Google) +Signed-off-by: Ingo Molnar +Reviewed-by: Vincent Guittot +Reviewed-by: Dietmar Eggemann +Acked-by: Peter Zijlstra (Intel) +Link: https://lore.kernel.org/r/20230916232955.2099394-3-qyousef@layalina.io +Signed-off-by: Sasha Levin +--- + kernel/sched/fair.c | 18 +----------------- + 1 file changed, 1 insertion(+), 17 deletions(-) + +diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c +index d53f57ac76094..73a89fbd81be8 100644 +--- a/kernel/sched/fair.c ++++ b/kernel/sched/fair.c +@@ -3927,22 +3927,6 @@ static inline unsigned long task_util_est(struct task_struct *p) + return max(task_util(p), _task_util_est(p)); + } + +-#ifdef CONFIG_UCLAMP_TASK +-static inline unsigned long uclamp_task_util(struct task_struct *p, +- unsigned long uclamp_min, +- unsigned long uclamp_max) +-{ +- return clamp(task_util_est(p), uclamp_min, uclamp_max); +-} +-#else +-static inline unsigned long uclamp_task_util(struct task_struct *p, +- unsigned long uclamp_min, +- unsigned long uclamp_max) +-{ +- return task_util_est(p); +-} +-#endif +- + static inline void util_est_enqueue(struct cfs_rq *cfs_rq, + struct task_struct *p) + { +@@ -6842,7 +6826,7 @@ static int find_energy_efficient_cpu(struct task_struct *p, int prev_cpu) + goto fail; + + sync_entity_load_avg(&p->se); +- if (!uclamp_task_util(p, p_util_min, p_util_max)) ++ if (!task_util_est(p) && p_util_min == 0) + goto unlock; + + for (; pd; pd = pd->next) { +-- +2.42.0 + diff --git a/queue-5.10/scsi-ufs-core-leave-space-for-0-in-utf8-desc-string.patch b/queue-5.10/scsi-ufs-core-leave-space-for-0-in-utf8-desc-string.patch new file mode 100644 index 00000000000..60eb75c21b7 --- /dev/null +++ b/queue-5.10/scsi-ufs-core-leave-space-for-0-in-utf8-desc-string.patch @@ -0,0 +1,48 @@ +From bcdc89f6673021e61cb8819d026a58b02ae5789c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 17 Oct 2023 11:20:26 -0700 +Subject: scsi: ufs: core: Leave space for '\0' in utf8 desc string + +From: Daniel Mentz + +[ Upstream commit a75a16c62a2540f11eeae4f2b50e95deefb652ea ] + +utf16s_to_utf8s does not NULL terminate the output string. For us to be +able to add a NULL character when utf16s_to_utf8s returns, we need to make +sure that there is space for such NULL character at the end of the output +buffer. We can achieve this by passing an output buffer size to +utf16s_to_utf8s that is one character less than what we allocated. + +Other call sites of utf16s_to_utf8s appear to be using the same technique +where they artificially reduce the buffer size by one to leave space for a +NULL character or line feed character. + +Fixes: 4b828fe156a6 ("scsi: ufs: revamp string descriptor reading") +Reviewed-by: Mars Cheng +Reviewed-by: Bart Van Assche +Reviewed-by: Yen-lin Lai +Signed-off-by: Daniel Mentz +Link: https://lore.kernel.org/r/20231017182026.2141163-1-danielmentz@google.com +Reviewed-by: Avri Altman +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/ufs/ufshcd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c +index f3389e9131794..a432aebd14be6 100644 +--- a/drivers/scsi/ufs/ufshcd.c ++++ b/drivers/scsi/ufs/ufshcd.c +@@ -3339,7 +3339,7 @@ int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, + */ + ret = utf16s_to_utf8s(uc_str->uc, + uc_str->len - QUERY_DESC_HDR_SIZE, +- UTF16_BIG_ENDIAN, str, ascii_len); ++ UTF16_BIG_ENDIAN, str, ascii_len - 1); + + /* replace non-printable or non-ASCII characters with spaces */ + for (i = 0; i < ret; i++) +-- +2.42.0 + diff --git a/queue-5.10/selftests-pidfd-fix-ksft-print-formats.patch b/queue-5.10/selftests-pidfd-fix-ksft-print-formats.patch new file mode 100644 index 00000000000..bc17bac7011 --- /dev/null +++ b/queue-5.10/selftests-pidfd-fix-ksft-print-formats.patch @@ -0,0 +1,102 @@ +From 3bcdda2538d548b96bf4ac7c9bf71d4f55735a26 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 13 Oct 2023 13:36:28 +0200 +Subject: selftests/pidfd: Fix ksft print formats + +From: Maciej Wieczor-Retman + +[ Upstream commit 4d7f4e8158b62f63031510cdc24acc520956c091 ] + +Compiling pidfd selftest after adding a __printf() attribute to +ksft_print_msg() and ksft_test_result_pass() exposes -Wformat warnings +in error_report(), test_pidfd_poll_exec_thread(), +child_poll_exec_test(), test_pidfd_poll_leader_exit_thread(), +child_poll_leader_exit_test(). + +The ksft_test_result_pass() in error_report() expects a string but +doesn't provide any argument after the format string. All the other +calls to ksft_print_msg() in the functions mentioned above have format +strings that don't match with other passed arguments. + +Fix format specifiers so they match the passed variables. + +Add a missing variable to ksft_test_result_pass() inside +error_report() so it matches other cases in the switch statement. + +Fixes: 2def297ec7fb ("pidfd: add tests for NSpid info in fdinfo") + +Signed-off-by: Maciej Wieczor-Retman +Signed-off-by: Shuah Khan +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/pidfd/pidfd_fdinfo_test.c | 2 +- + tools/testing/selftests/pidfd/pidfd_test.c | 12 ++++++------ + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/tools/testing/selftests/pidfd/pidfd_fdinfo_test.c b/tools/testing/selftests/pidfd/pidfd_fdinfo_test.c +index 3fd8e903118f5..3bc46d6151f44 100644 +--- a/tools/testing/selftests/pidfd/pidfd_fdinfo_test.c ++++ b/tools/testing/selftests/pidfd/pidfd_fdinfo_test.c +@@ -62,7 +62,7 @@ static void error_report(struct error *err, const char *test_name) + break; + + case PIDFD_PASS: +- ksft_test_result_pass("%s test: Passed\n"); ++ ksft_test_result_pass("%s test: Passed\n", test_name); + break; + + default: +diff --git a/tools/testing/selftests/pidfd/pidfd_test.c b/tools/testing/selftests/pidfd/pidfd_test.c +index 9a2d64901d591..79f543ad394c2 100644 +--- a/tools/testing/selftests/pidfd/pidfd_test.c ++++ b/tools/testing/selftests/pidfd/pidfd_test.c +@@ -380,13 +380,13 @@ static int test_pidfd_send_signal_syscall_support(void) + + static void *test_pidfd_poll_exec_thread(void *priv) + { +- ksft_print_msg("Child Thread: starting. pid %d tid %d ; and sleeping\n", ++ ksft_print_msg("Child Thread: starting. pid %d tid %ld ; and sleeping\n", + getpid(), syscall(SYS_gettid)); + ksft_print_msg("Child Thread: doing exec of sleep\n"); + + execl("/bin/sleep", "sleep", str(CHILD_THREAD_MIN_WAIT), (char *)NULL); + +- ksft_print_msg("Child Thread: DONE. pid %d tid %d\n", ++ ksft_print_msg("Child Thread: DONE. pid %d tid %ld\n", + getpid(), syscall(SYS_gettid)); + return NULL; + } +@@ -426,7 +426,7 @@ static int child_poll_exec_test(void *args) + { + pthread_t t1; + +- ksft_print_msg("Child (pidfd): starting. pid %d tid %d\n", getpid(), ++ ksft_print_msg("Child (pidfd): starting. pid %d tid %ld\n", getpid(), + syscall(SYS_gettid)); + pthread_create(&t1, NULL, test_pidfd_poll_exec_thread, NULL); + /* +@@ -477,10 +477,10 @@ static void test_pidfd_poll_exec(int use_waitpid) + + static void *test_pidfd_poll_leader_exit_thread(void *priv) + { +- ksft_print_msg("Child Thread: starting. pid %d tid %d ; and sleeping\n", ++ ksft_print_msg("Child Thread: starting. pid %d tid %ld ; and sleeping\n", + getpid(), syscall(SYS_gettid)); + sleep(CHILD_THREAD_MIN_WAIT); +- ksft_print_msg("Child Thread: DONE. pid %d tid %d\n", getpid(), syscall(SYS_gettid)); ++ ksft_print_msg("Child Thread: DONE. pid %d tid %ld\n", getpid(), syscall(SYS_gettid)); + return NULL; + } + +@@ -489,7 +489,7 @@ static int child_poll_leader_exit_test(void *args) + { + pthread_t t1, t2; + +- ksft_print_msg("Child: starting. pid %d tid %d\n", getpid(), syscall(SYS_gettid)); ++ ksft_print_msg("Child: starting. pid %d tid %ld\n", getpid(), syscall(SYS_gettid)); + pthread_create(&t1, NULL, test_pidfd_poll_leader_exit_thread, NULL); + pthread_create(&t2, NULL, test_pidfd_poll_leader_exit_thread, NULL); + +-- +2.42.0 + diff --git a/queue-5.10/selftests-resctrl-ensure-the-benchmark-commands-fits.patch b/queue-5.10/selftests-resctrl-ensure-the-benchmark-commands-fits.patch new file mode 100644 index 00000000000..7b340cd7714 --- /dev/null +++ b/queue-5.10/selftests-resctrl-ensure-the-benchmark-commands-fits.patch @@ -0,0 +1,55 @@ +From 527372d40a18f39e1a6e33dddf7211054fabb8be Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Sep 2023 12:53:32 +0300 +Subject: selftests/resctrl: Ensure the benchmark commands fits to its array +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ilpo Järvinen + +[ Upstream commit 4a28c7665c2a1ac0400864eabb0c641e135f61aa ] + +Benchmark command is copied into an array in the stack. The array is +BENCHMARK_ARGS items long but the command line could try to provide a +longer command. Argument size is also fixed by BENCHMARK_ARG_SIZE (63 +bytes of space after fitting the terminating \0 character) and user +could have inputted argument longer than that. + +Return error in case the benchmark command does not fit to the space +allocated for it. + +Fixes: ecdbb911f22d ("selftests/resctrl: Add MBM test") +Signed-off-by: Ilpo Järvinen +Tested-by: Shaopeng Tan +Reviewed-by: Shaopeng Tan +Reviewed-by: "Wieczor-Retman, Maciej" +Reviewed-by: Reinette Chatre +Signed-off-by: Shuah Khan +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/resctrl/resctrl_tests.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c +index bd98746c6f858..b33d1d6dd99ae 100644 +--- a/tools/testing/selftests/resctrl/resctrl_tests.c ++++ b/tools/testing/selftests/resctrl/resctrl_tests.c +@@ -132,9 +132,14 @@ int main(int argc, char **argv) + detect_amd(); + + if (has_ben) { ++ if (argc - ben_ind >= BENCHMARK_ARGS) ++ ksft_exit_fail_msg("Too long benchmark command.\n"); ++ + /* Extract benchmark command from command line. */ + for (i = ben_ind; i < argc; i++) { + benchmark_cmd[i - ben_ind] = benchmark_cmd_area[i]; ++ if (strlen(argv[i]) >= BENCHMARK_ARG_SIZE) ++ ksft_exit_fail_msg("Too long benchmark command argument.\n"); + sprintf(benchmark_cmd[i - ben_ind], "%s", argv[i]); + } + benchmark_cmd[ben_count] = NULL; +-- +2.42.0 + diff --git a/queue-5.10/series b/queue-5.10/series index e69de29bb2d..f419f641e97 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -0,0 +1,176 @@ +iov_iter-x86-be-consistent-about-the-__user-tag-on-c.patch +sched-uclamp-ignore-util-0-optimization-in-feec-when.patch +vfs-fix-readahead-2-on-block-devices.patch +x86-srso-fix-sbpb-enablement-for-possible-future-fix.patch +futex-don-t-include-process-mm-in-futex-key-on-no-mm.patch +x86-boot-fix-incorrect-startup_gdt_descr.size.patch +pstore-platform-add-check-for-kstrdup.patch +genirq-matrix-exclude-managed-interrupts-in-irq_matr.patch +i40e-fix-potential-memory-leaks-in-i40e_remove.patch +wifi-iwlwifi-use-fw-rate-for-non-data-frames.patch +udp-add-missing-write_once-around-up-encap_rcv.patch +tcp-call-tcp_try_undo_recovery-when-an-rtod-tfo-syna.patch +overflow-implement-size_t-saturating-arithmetic-help.patch +gve-use-size_add-in-call-to-struct_size.patch +mlxsw-use-size_mul-in-call-to-struct_size.patch +tipc-use-size_add-in-calls-to-struct_size.patch +net-spider_net-use-size_add-in-call-to-struct_size.patch +wifi-rtw88-debug-fix-the-null-vs-is_err-bug-for-debu.patch +wifi-mt76-mt7603-rework-fix-rx-pse-hang-check.patch +tcp_metrics-add-missing-barriers-on-delete.patch +tcp_metrics-properly-set-tp-snd_ssthresh-in-tcp_init.patch +tcp_metrics-do-not-create-an-entry-from-tcp_init_met.patch +wifi-rtlwifi-fix-edca-limit-set-by-bt-coexistence.patch +can-dev-can_restart-don-t-crash-kernel-if-carrier-is.patch +can-dev-can_restart-fix-race-condition-between-contr.patch +pm-devfreq-rockchip-dfi-make-pmu-regmap-mandatory.patch +thermal-core-prevent-potential-string-overflow.patch +r8169-use-tp_to_dev-instead-of-open-code.patch +r8169-fix-rare-issue-with-broken-rx-after-link-down-.patch +chtls-fix-tp-rcv_tstamp-initialization.patch +tcp-fix-cookie_init_timestamp-overflows.patch +acpi-sysfs-fix-create_pnp_modalias-and-create_of_mod.patch +ipv6-avoid-atomic-fragment-on-gso-packets.patch +net-add-dev_stats_read-helper.patch +ipvlan-properly-track-tx_errors.patch +regmap-debugfs-fix-a-erroneous-check-after-snprintf.patch +clk-qcom-gcc-msm8996-use-array_size-instead-of-speci.patch +clk-qcom-gcc-msm8996-drop-unsupported-clock-sources.patch +clk-qcom-gcc-msm8996-move-clock-parent-tables-down.patch +clk-qcom-gcc-msm8996-use-parent_hws-_data-instead-of.patch +clk-qcom-gcc-msm8996-remove-rpm-bus-clocks.patch +clk-qcom-clk-rcg2-fix-clock-rate-overflow-for-high-p.patch +clk-qcom-mmcc-msm8998-add-hardware-clockgating-regis.patch +clk-qcom-mmcc-msm8998-don-t-check-halt-bit-on-some-b.patch +clk-qcom-mmcc-msm8998-set-bimc_smmu_gdsc-always-on.patch +clk-qcom-mmcc-msm8998-fix-the-smmu-gdsc.patch +clk-qcom-gcc-sm8150-use-array_size-instead-of-specif.patch +clk-qcom-gcc-sm8150-fix-gcc_sdcc2_apps_clk_src.patch +clk-imx-select-mxc_clk-for-clk_imx8qxp.patch +clk-imx-imx8mq-correct-error-handling-path.patch +clk-asm9260-use-parent-index-to-link-the-reference-c.patch +clk-linux-clk-provider.h-fix-kernel-doc-warnings-and.patch +spi-nxp-fspi-use-the-correct-ioremap-function.patch +clk-keystone-pll-fix-a-couple-null-vs-is_err-checks.patch +clk-ti-add-ti_dt_clk_name-helper-to-use-clock-output.patch +clk-ti-update-pll-and-clockdomain-clocks-to-use-ti_d.patch +clk-ti-update-component-clocks-to-use-ti_dt_clk_name.patch +clk-ti-change-ti_clk_register-_omap_hw-api.patch +clk-ti-fix-double-free-in-of_ti_divider_clk_setup.patch +clk-npcm7xx-fix-incorrect-kfree.patch +clk-mediatek-clk-mt6765-add-check-for-mtk_alloc_clk_.patch +clk-mediatek-clk-mt6779-add-check-for-mtk_alloc_clk_.patch +clk-mediatek-clk-mt6797-add-check-for-mtk_alloc_clk_.patch +clk-mediatek-clk-mt7629-eth-add-check-for-mtk_alloc_.patch +clk-mediatek-clk-mt7629-add-check-for-mtk_alloc_clk_.patch +clk-mediatek-clk-mt2701-add-check-for-mtk_alloc_clk_.patch +clk-qcom-config-ipq_apss_6018-should-depend-on-qcom_.patch +platform-x86-wmi-fix-probe-failure-when-failing-to-r.patch +platform-x86-wmi-remove-unnecessary-initializations.patch +platform-x86-wmi-fix-opening-of-char-device.patch +hwmon-axi-fan-control-support-temperature-vs-pwm-poi.patch +hwmon-axi-fan-control-fix-possible-null-pointer-dere.patch +hwmon-coretemp-fix-potentially-truncated-sysfs-attri.patch +drm-rockchip-vop-fix-reset-of-state-in-duplicate-sta.patch +drm-rockchip-vop-fix-call-to-crtc-reset-helper.patch +drm-radeon-possible-buffer-overflow.patch +drm-bridge-tc358768-fix-use-of-uninitialized-variabl.patch +drm-bridge-tc358768-disable-non-continuous-clock-mod.patch +drm-bridge-tc358768-fix-bit-updates.patch +drm-mediatek-fix-iommu-fault-during-crtc-enabling.patch +drm-rockchip-cdn-dp-fix-some-error-handling-paths-in.patch +arm64-arm-xen-enlighten-fix-kpti-checks.patch +drm-rockchip-fix-type-promotion-bug-in-rockchip_gem_.patch +xen-pciback-consider-intx-disabled-when-msi-msi-x-is.patch +arm64-dts-qcom-msm8916-fix-iommu-local-address-range.patch +arm64-dts-qcom-sdm845-mtp-fix-wifi-configuration.patch +arm-dts-qcom-mdm9615-populate-vsdcc-fixed-regulator.patch +soc-qcom-llcc-handle-a-second-device-without-data-co.patch +firmware-ti_sci-mark-driver-as-non-removable.patch +clk-scmi-free-scmi_clk-allocated-when-the-clocks-wit.patch +selftests-pidfd-fix-ksft-print-formats.patch +selftests-resctrl-ensure-the-benchmark-commands-fits.patch +crypto-hisilicon-hpre-fix-a-erroneous-check-after-sn.patch +hwrng-geode-fix-accessing-registers.patch +libnvdimm-of_pmem-use-devm_kstrdup-instead-of-kstrdu.patch +nd_btt-make-btt-lanes-preemptible.patch +crypto-caam-qi2-fix-chacha20-poly1305-self-test-fail.patch +crypto-caam-jr-fix-chacha20-poly1305-self-test-failu.patch +crypto-qat-mask-device-capabilities-with-soft-straps.patch +crypto-qat-increase-size-of-buffers.patch +hid-cp2112-fix-duplicate-workqueue-initialization.patch +arm-9321-1-memset-cast-the-constant-byte-to-unsigned.patch +ext4-move-ix-sanity-check-to-corrent-position.patch +asoc-fsl-mpc5200_dma.c-fix-warning-of-function-param.patch +ib-mlx5-fix-rdma-counter-binding-for-raw-qp.patch +rdma-hns-fix-uninitialized-ucmd-in-hns_roce_create_q.patch +rdma-hns-fix-signed-unsigned-mixed-comparisons.patch +asoc-fsl-fix-pm-disable-depth-imbalance-in-fsl_easrc.patch +scsi-ufs-core-leave-space-for-0-in-utf8-desc-string.patch +rdma-hfi1-workaround-truncation-compilation-error.patch +gpio-don-t-fiddle-with-irqchips-marked-as-immutable.patch +gpio-expose-the-gpiochip_irq_re-ql-res-helpers.patch +gpio-add-helpers-to-ease-the-transition-towards-immu.patch +hid-cp2112-make-irq_chip-immutable.patch +hid-cp2112-fix-irq-shutdown-stopping-polling-for-all.patch +sh-bios-revive-earlyprintk-support.patch +revert-hid-logitech-hidpp-add-a-module-parameter-to-.patch +hid-logitech-hidpp-remove-hidpp_quirk_no_hidinput-qu.patch +hid-logitech-hidpp-don-t-restart-io-instead-defer-hi.patch +hid-logitech-hidpp-revert-don-t-restart-communicatio.patch +hid-logitech-hidpp-move-get_wireless_feature_index-c.patch +asoc-intel-skylake-fix-mem-leak-when-parsing-uuids-f.patch +padata-convert-from-atomic_t-to-refcount_t-on-parall.patch +padata-fix-refcnt-handling-in-padata_free_shell.patch +asoc-ams-delta.c-use-component-after-check.patch +mfd-core-un-constify-mfd_cell.of_reg.patch +mfd-core-ensure-disabled-devices-are-skipped-without.patch +mfd-dln2-fix-double-put-in-dln2_probe.patch +leds-pwm-don-t-disable-the-pwm-when-the-led-should-b.patch +leds-trigger-ledtrig-cpu-fix-output-may-be-truncated.patch +f2fs-compress-support-chksum.patch +f2fs-add-compress_mode-mount-option.patch +f2fs-compress-deny-setting-unsupported-compress-algo.patch +f2fs-compress-support-compress-level.patch +f2fs-document-add-description-about-compressed-space.patch +f2fs-compress-add-nocompress-extensions-support.patch +f2fs-compress-fix-to-avoid-redundant-compress-extens.patch +tty-tty_jobctrl-fix-pid-memleak-in-disassociate_ctty.patch +livepatch-fix-missing-newline-character-in-klp_resol.patch +perf-evlist-add-evlist__add_dummy_on_all_cpus.patch +perf-tools-get-rid-of-evlist__add_on_all_cpus.patch +perf-evlist-avoid-frequency-mode-for-the-dummy-event.patch +usb-dwc2-fix-possible-null-pointer-dereference-cause.patch +dmaengine-ti-edma-handle-irq_of_parse_and_map-errors.patch +misc-st_core-do-not-call-kfree_skb-under-spin_lock_i.patch +tools-iio-privatize-globals-and-functions-in-iio_gen.patch +tools-iio-iio_generic_buffer-fix-some-integer-type-a.patch +tools-iio-iio_generic_buffer-ensure-alignment.patch +usb-usbip-fix-stub_dev-hub-disconnect.patch +dmaengine-pxa_dma-remove-an-erroneous-bug_on-in-pxad.patch +f2fs-fix-to-initialize-map.m_pblk-in-f2fs_precache_e.patch +interconnect-qcom-sc7180-retire-define_qbcm.patch +interconnect-qcom-sc7180-set-acv-enable_mask.patch +interconnect-qcom-osm-l3-replace-custom-implementati.patch +modpost-fix-tee-module_device_table-built-on-big-end.patch +powerpc-40x-remove-stale-pte_atomic_updates-macro.patch +powerpc-xive-fix-endian-conversion-size.patch +powerpc-imc-pmu-use-the-correct-spinlock-initializer.patch +powerpc-pseries-fix-potential-memory-leak-in-init_cp.patch +xhci-loosen-rpm-as-default-policy-to-cover-for-amd-x.patch +usb-host-xhci-plat-fix-possible-kernel-oops-while-re.patch +perf-machine-avoid-out-of-bounds-lbr-memory-read.patch +perf-hist-add-missing-puts-to-hist__account_cycles.patch +i3c-fix-potential-refcount-leak-in-i3c_master_regist.patch +rtc-pcf85363-fix-wrong-mask-val-parameters-in-regmap.patch +pcmcia-cs-fix-possible-hung-task-and-memory-leak-pcc.patch +pcmcia-ds-fix-refcount-leak-in-pcmcia_device_add.patch +pcmcia-ds-fix-possible-name-leak-in-error-path-in-pc.patch +media-i2c-max9286-fix-some-redundant-of_node_put-cal.patch +media-bttv-fix-use-after-free-error-due-to-btv-timeo.patch +media-s3c-camif-avoid-inappropriate-kfree.patch +media-vidtv-psi-add-check-for-kstrdup.patch +media-vidtv-mux-add-check-and-kfree-for-kstrdup.patch +media-cedrus-fix-clock-reset-sequence.patch +media-dvb-usb-v2-af9035-fix-missing-unlock.patch +regmap-prevent-noinc-writes-from-clobbering-cache.patch diff --git a/queue-5.10/sh-bios-revive-earlyprintk-support.patch b/queue-5.10/sh-bios-revive-earlyprintk-support.patch new file mode 100644 index 00000000000..7f07308646a --- /dev/null +++ b/queue-5.10/sh-bios-revive-earlyprintk-support.patch @@ -0,0 +1,52 @@ +From 2180f3df0296c7119a66ef1061635b7cd8aadc24 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 19 Oct 2023 11:46:43 +0200 +Subject: sh: bios: Revive earlyprintk support + +From: Geert Uytterhoeven + +[ Upstream commit 553f7ac78fbb41b2c93ab9b9d78e42274d27daa9 ] + +The SuperH BIOS earlyprintk code is protected by CONFIG_EARLY_PRINTK. +However, when this protection was added, it was missed that SuperH no +longer defines an EARLY_PRINTK config symbol since commit +e76fe57447e88916 ("sh: Remove old early serial console code V2"), so +BIOS earlyprintk can no longer be used. + +Fix this by reviving the EARLY_PRINTK config symbol. + +Fixes: d0380e6c3c0f6edb ("early_printk: consolidate random copies of identical code") +Signed-off-by: Geert Uytterhoeven +Reviewed-by: John Paul Adrian Glaubitz +Link: https://lore.kernel.org/r/c40972dfec3dcc6719808d5df388857360262878.1697708489.git.geert+renesas@glider.be +Signed-off-by: John Paul Adrian Glaubitz +Signed-off-by: Sasha Levin +--- + arch/sh/Kconfig.debug | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug +index 7bc1b10b81c96..f030dd4c08607 100644 +--- a/arch/sh/Kconfig.debug ++++ b/arch/sh/Kconfig.debug +@@ -25,6 +25,17 @@ config STACK_DEBUG + every function call and will therefore incur a major + performance hit. Most users should say N. + ++config EARLY_PRINTK ++ bool "Early printk" ++ depends on SH_STANDARD_BIOS ++ help ++ Say Y here to redirect kernel printk messages to the serial port ++ used by the SH-IPL bootloader, starting very early in the boot ++ process and ending when the kernel's serial console is initialised. ++ This option is only useful while porting the kernel to a new machine, ++ when the kernel may crash or hang before the serial console is ++ initialised. If unsure, say N. ++ + config 4KSTACKS + bool "Use 4Kb for kernel stacks instead of 8Kb" + depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB +-- +2.42.0 + diff --git a/queue-5.10/soc-qcom-llcc-handle-a-second-device-without-data-co.patch b/queue-5.10/soc-qcom-llcc-handle-a-second-device-without-data-co.patch new file mode 100644 index 00000000000..c9f5dd8561a --- /dev/null +++ b/queue-5.10/soc-qcom-llcc-handle-a-second-device-without-data-co.patch @@ -0,0 +1,42 @@ +From 53032ca39a7e6b05770819aebfbce5359a2901c2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 26 Sep 2023 10:32:29 +0200 +Subject: soc: qcom: llcc: Handle a second device without data corruption +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit f1a1bc8775b26345aba2be278118999e7f661d3d ] + +Usually there is only one llcc device. But if there were a second, even +a failed probe call would modify the global drv_data pointer. So check +if drv_data is valid before overwriting it. + +Signed-off-by: Uwe Kleine-König +Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") +Link: https://lore.kernel.org/r/20230926083229.2073890-1-u.kleine-koenig@pengutronix.de +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/soc/qcom/llcc-qcom.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c +index c60fe98f03e37..8cf7b142e1410 100644 +--- a/drivers/soc/qcom/llcc-qcom.c ++++ b/drivers/soc/qcom/llcc-qcom.c +@@ -413,6 +413,9 @@ static int qcom_llcc_probe(struct platform_device *pdev) + const struct llcc_slice_config *llcc_cfg; + u32 sz; + ++ if (!IS_ERR(drv_data)) ++ return -EBUSY; ++ + drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); + if (!drv_data) { + ret = -ENOMEM; +-- +2.42.0 + diff --git a/queue-5.10/spi-nxp-fspi-use-the-correct-ioremap-function.patch b/queue-5.10/spi-nxp-fspi-use-the-correct-ioremap-function.patch new file mode 100644 index 00000000000..01128698bf0 --- /dev/null +++ b/queue-5.10/spi-nxp-fspi-use-the-correct-ioremap-function.patch @@ -0,0 +1,38 @@ +From f3db60f844227f9ec83b6729a2627ff68aeeb187 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 10 Oct 2023 15:15:24 -0500 +Subject: spi: nxp-fspi: use the correct ioremap function + +From: Han Xu + +[ Upstream commit c3aa5cb264a38ae9bbcce32abca4c155af0456df ] + +AHB memory as MMIO should be mapped with ioremap rather than ioremap_wc, +which should have been used initially just to handle unaligned access as +a workaround. + +Fixes: d166a73503ef ("spi: fspi: dynamically alloc AHB memory") +Signed-off-by: Han Xu +Link: https://lore.kernel.org/r/20231010201524.2021340-1-han.xu@nxp.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-nxp-fspi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c +index 90b5fbc914ae2..f40b93960b893 100644 +--- a/drivers/spi/spi-nxp-fspi.c ++++ b/drivers/spi/spi-nxp-fspi.c +@@ -685,7 +685,7 @@ static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) + f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? + len : NXP_FSPI_MIN_IOMAP; + +- f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, ++ f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start, + f->memmap_len); + + if (!f->ahb_addr) { +-- +2.42.0 + diff --git a/queue-5.10/tcp-call-tcp_try_undo_recovery-when-an-rtod-tfo-syna.patch b/queue-5.10/tcp-call-tcp_try_undo_recovery-when-an-rtod-tfo-syna.patch new file mode 100644 index 00000000000..faafed48680 --- /dev/null +++ b/queue-5.10/tcp-call-tcp_try_undo_recovery-when-an-rtod-tfo-syna.patch @@ -0,0 +1,71 @@ +From eea6a6be3ec6f662054b0fabc9f8eb1a46b09512 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Sep 2023 14:36:20 +0000 +Subject: tcp: call tcp_try_undo_recovery when an RTOd TFO SYNACK is ACKed + +From: Aananth V + +[ Upstream commit e326578a21414738de45f77badd332fb00bd0f58 ] + +For passive TCP Fast Open sockets that had SYN/ACK timeout and did not +send more data in SYN_RECV, upon receiving the final ACK in 3WHS, the +congestion state may awkwardly stay in CA_Loss mode unless the CA state +was undone due to TCP timestamp checks. However, if +tcp_rcv_synrecv_state_fastopen() decides not to undo, then we should +enter CA_Open, because at that point we have received an ACK covering +the retransmitted SYNACKs. Currently, the icsk_ca_state is only set to +CA_Open after we receive an ACK for a data-packet. This is because +tcp_ack does not call tcp_fastretrans_alert (and tcp_process_loss) if +!prior_packets + +Note that tcp_process_loss() calls tcp_try_undo_recovery(), so having +tcp_rcv_synrecv_state_fastopen() decide that if we're in CA_Loss we +should call tcp_try_undo_recovery() is consistent with that, and +low risk. + +Fixes: dad8cea7add9 ("tcp: fix TFO SYNACK undo to avoid double-timestamp-undo") +Signed-off-by: Aananth V +Signed-off-by: Neal Cardwell +Signed-off-by: Yuchung Cheng +Reviewed-by: Eric Dumazet +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/ipv4/tcp_input.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c +index 0c935904ced82..a8948c76d19b6 100644 +--- a/net/ipv4/tcp_input.c ++++ b/net/ipv4/tcp_input.c +@@ -6349,22 +6349,23 @@ static int tcp_rcv_synsent_state_process(struct sock *sk, struct sk_buff *skb, + + static void tcp_rcv_synrecv_state_fastopen(struct sock *sk) + { ++ struct tcp_sock *tp = tcp_sk(sk); + struct request_sock *req; + + /* If we are still handling the SYNACK RTO, see if timestamp ECR allows + * undo. If peer SACKs triggered fast recovery, we can't undo here. + */ +- if (inet_csk(sk)->icsk_ca_state == TCP_CA_Loss) +- tcp_try_undo_loss(sk, false); ++ if (inet_csk(sk)->icsk_ca_state == TCP_CA_Loss && !tp->packets_out) ++ tcp_try_undo_recovery(sk); + + /* Reset rtx states to prevent spurious retransmits_timed_out() */ +- tcp_sk(sk)->retrans_stamp = 0; ++ tp->retrans_stamp = 0; + inet_csk(sk)->icsk_retransmits = 0; + + /* Once we leave TCP_SYN_RECV or TCP_FIN_WAIT_1, + * we no longer need req so release it. + */ +- req = rcu_dereference_protected(tcp_sk(sk)->fastopen_rsk, ++ req = rcu_dereference_protected(tp->fastopen_rsk, + lockdep_sock_is_held(sk)); + reqsk_fastopen_remove(sk, req, false); + +-- +2.42.0 + diff --git a/queue-5.10/tcp-fix-cookie_init_timestamp-overflows.patch b/queue-5.10/tcp-fix-cookie_init_timestamp-overflows.patch new file mode 100644 index 00000000000..cd5672d9c92 --- /dev/null +++ b/queue-5.10/tcp-fix-cookie_init_timestamp-overflows.patch @@ -0,0 +1,102 @@ +From bab34f644bda429553cdf43233d96258ae89a0a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 Oct 2023 12:57:37 +0000 +Subject: tcp: fix cookie_init_timestamp() overflows + +From: Eric Dumazet + +[ Upstream commit 73ed8e03388d16c12fc577e5c700b58a29045a15 ] + +cookie_init_timestamp() is supposed to return a 64bit timestamp +suitable for both TSval determination and setting of skb->tstamp. + +Unfortunately it uses 32bit fields and overflows after +2^32 * 10^6 nsec (~49 days) of uptime. + +Generated TSval are still correct, but skb->tstamp might be set +far away in the past, potentially confusing other layers. + +tcp_ns_to_ts() is changed to return a full 64bit value, +ts and ts_now variables are changed to u64 type, +and TSMASK is removed in favor of shifts operations. + +While we are at it, change this sequence: + ts >>= TSBITS; + ts--; + ts <<= TSBITS; + ts |= options; +to: + ts -= (1UL << TSBITS); + +Fixes: 9a568de4818d ("tcp: switch TCP TS option (RFC 7323) to 1ms clock") +Signed-off-by: Eric Dumazet +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + include/net/tcp.h | 2 +- + net/ipv4/syncookies.c | 20 +++++++------------- + 2 files changed, 8 insertions(+), 14 deletions(-) + +diff --git a/include/net/tcp.h b/include/net/tcp.h +index 772e593910287..5c03dc6d0f792 100644 +--- a/include/net/tcp.h ++++ b/include/net/tcp.h +@@ -776,7 +776,7 @@ static inline u32 tcp_time_stamp(const struct tcp_sock *tp) + } + + /* Convert a nsec timestamp into TCP TSval timestamp (ms based currently) */ +-static inline u32 tcp_ns_to_ts(u64 ns) ++static inline u64 tcp_ns_to_ts(u64 ns) + { + return div_u64(ns, NSEC_PER_SEC / TCP_TS_HZ); + } +diff --git a/net/ipv4/syncookies.c b/net/ipv4/syncookies.c +index 542b66783493b..cc860f2dcf658 100644 +--- a/net/ipv4/syncookies.c ++++ b/net/ipv4/syncookies.c +@@ -43,7 +43,6 @@ static siphash_key_t syncookie_secret[2] __read_mostly; + * requested/supported by the syn/synack exchange. + */ + #define TSBITS 6 +-#define TSMASK (((__u32)1 << TSBITS) - 1) + + static u32 cookie_hash(__be32 saddr, __be32 daddr, __be16 sport, __be16 dport, + u32 count, int c) +@@ -64,27 +63,22 @@ static u32 cookie_hash(__be32 saddr, __be32 daddr, __be16 sport, __be16 dport, + */ + u64 cookie_init_timestamp(struct request_sock *req, u64 now) + { +- struct inet_request_sock *ireq; +- u32 ts, ts_now = tcp_ns_to_ts(now); ++ const struct inet_request_sock *ireq = inet_rsk(req); ++ u64 ts, ts_now = tcp_ns_to_ts(now); + u32 options = 0; + +- ireq = inet_rsk(req); +- + options = ireq->wscale_ok ? ireq->snd_wscale : TS_OPT_WSCALE_MASK; + if (ireq->sack_ok) + options |= TS_OPT_SACK; + if (ireq->ecn_ok) + options |= TS_OPT_ECN; + +- ts = ts_now & ~TSMASK; ++ ts = (ts_now >> TSBITS) << TSBITS; + ts |= options; +- if (ts > ts_now) { +- ts >>= TSBITS; +- ts--; +- ts <<= TSBITS; +- ts |= options; +- } +- return (u64)ts * (NSEC_PER_SEC / TCP_TS_HZ); ++ if (ts > ts_now) ++ ts -= (1UL << TSBITS); ++ ++ return ts * (NSEC_PER_SEC / TCP_TS_HZ); + } + + +-- +2.42.0 + diff --git a/queue-5.10/tcp_metrics-add-missing-barriers-on-delete.patch b/queue-5.10/tcp_metrics-add-missing-barriers-on-delete.patch new file mode 100644 index 00000000000..266b08fbca6 --- /dev/null +++ b/queue-5.10/tcp_metrics-add-missing-barriers-on-delete.patch @@ -0,0 +1,47 @@ +From 6292f131ee3416221acb1314724bff28a219e78f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Sep 2023 22:03:53 +0000 +Subject: tcp_metrics: add missing barriers on delete + +From: Eric Dumazet + +[ Upstream commit cbc3a153222805d65f821e10f4f78b6afce06f86 ] + +When removing an item from RCU protected list, we must prevent +store-tearing, using rcu_assign_pointer() or WRITE_ONCE(). + +Fixes: 04f721c671656 ("tcp_metrics: Rewrite tcp_metrics_flush_all") +Signed-off-by: Eric Dumazet +Reviewed-by: David Ahern +Acked-by: Neal Cardwell +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + net/ipv4/tcp_metrics.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c +index a707fa1dbcafd..03ab7500f5745 100644 +--- a/net/ipv4/tcp_metrics.c ++++ b/net/ipv4/tcp_metrics.c +@@ -908,7 +908,7 @@ static void tcp_metrics_flush_all(struct net *net) + match = net ? net_eq(tm_net(tm), net) : + !refcount_read(&tm_net(tm)->count); + if (match) { +- *pp = tm->tcpm_next; ++ rcu_assign_pointer(*pp, tm->tcpm_next); + kfree_rcu(tm, rcu_head); + } else { + pp = &tm->tcpm_next; +@@ -949,7 +949,7 @@ static int tcp_metrics_nl_cmd_del(struct sk_buff *skb, struct genl_info *info) + if (addr_same(&tm->tcpm_daddr, &daddr) && + (!src || addr_same(&tm->tcpm_saddr, &saddr)) && + net_eq(tm_net(tm), net)) { +- *pp = tm->tcpm_next; ++ rcu_assign_pointer(*pp, tm->tcpm_next); + kfree_rcu(tm, rcu_head); + found = true; + } else { +-- +2.42.0 + diff --git a/queue-5.10/tcp_metrics-do-not-create-an-entry-from-tcp_init_met.patch b/queue-5.10/tcp_metrics-do-not-create-an-entry-from-tcp_init_met.patch new file mode 100644 index 00000000000..3e9f646d425 --- /dev/null +++ b/queue-5.10/tcp_metrics-do-not-create-an-entry-from-tcp_init_met.patch @@ -0,0 +1,39 @@ +From ca2350b3dd350e812326c6f0a6c13036824428fc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Sep 2023 22:03:55 +0000 +Subject: tcp_metrics: do not create an entry from tcp_init_metrics() + +From: Eric Dumazet + +[ Upstream commit a135798e6e200ecb2f864cecca6d257ba278370c ] + +tcp_init_metrics() only wants to get metrics if they were +previously stored in the cache. Creating an entry is adding +useless costs, especially when tcp_no_metrics_save is set. + +Fixes: 51c5d0c4b169 ("tcp: Maintain dynamic metrics in local cache.") +Signed-off-by: Eric Dumazet +Reviewed-by: David Ahern +Acked-by: Neal Cardwell +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + net/ipv4/tcp_metrics.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c +index a5d4e69acc05d..f823a15b973c4 100644 +--- a/net/ipv4/tcp_metrics.c ++++ b/net/ipv4/tcp_metrics.c +@@ -478,7 +478,7 @@ void tcp_init_metrics(struct sock *sk) + goto reset; + + rcu_read_lock(); +- tm = tcp_get_metrics(sk, dst, true); ++ tm = tcp_get_metrics(sk, dst, false); + if (!tm) { + rcu_read_unlock(); + goto reset; +-- +2.42.0 + diff --git a/queue-5.10/tcp_metrics-properly-set-tp-snd_ssthresh-in-tcp_init.patch b/queue-5.10/tcp_metrics-properly-set-tp-snd_ssthresh-in-tcp_init.patch new file mode 100644 index 00000000000..537f6153576 --- /dev/null +++ b/queue-5.10/tcp_metrics-properly-set-tp-snd_ssthresh-in-tcp_init.patch @@ -0,0 +1,52 @@ +From 02c942426585b940ddb6dc989a7a343797cee5f2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Sep 2023 22:03:54 +0000 +Subject: tcp_metrics: properly set tp->snd_ssthresh in tcp_init_metrics() + +From: Eric Dumazet + +[ Upstream commit 081480014a64a69d901f8ef1ffdd56d6085cf87e ] + +We need to set tp->snd_ssthresh to TCP_INFINITE_SSTHRESH +in the case tcp_get_metrics() fails for some reason. + +Fixes: 9ad7c049f0f7 ("tcp: RFC2988bis + taking RTT sample from 3WHS for the passive open side") +Signed-off-by: Eric Dumazet +Reviewed-by: David Ahern +Acked-by: Neal Cardwell +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + net/ipv4/tcp_metrics.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c +index 03ab7500f5745..a5d4e69acc05d 100644 +--- a/net/ipv4/tcp_metrics.c ++++ b/net/ipv4/tcp_metrics.c +@@ -470,6 +470,10 @@ void tcp_init_metrics(struct sock *sk) + u32 val, crtt = 0; /* cached RTT scaled by 8 */ + + sk_dst_confirm(sk); ++ /* ssthresh may have been reduced unnecessarily during. ++ * 3WHS. Restore it back to its initial default. ++ */ ++ tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; + if (!dst) + goto reset; + +@@ -489,11 +493,6 @@ void tcp_init_metrics(struct sock *sk) + tp->snd_ssthresh = val; + if (tp->snd_ssthresh > tp->snd_cwnd_clamp) + tp->snd_ssthresh = tp->snd_cwnd_clamp; +- } else { +- /* ssthresh may have been reduced unnecessarily during. +- * 3WHS. Restore it back to its initial default. +- */ +- tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; + } + val = tcp_metric_get(tm, TCP_METRIC_REORDERING); + if (val && tp->reordering != val) +-- +2.42.0 + diff --git a/queue-5.10/thermal-core-prevent-potential-string-overflow.patch b/queue-5.10/thermal-core-prevent-potential-string-overflow.patch new file mode 100644 index 00000000000..de3cc1c58fe --- /dev/null +++ b/queue-5.10/thermal-core-prevent-potential-string-overflow.patch @@ -0,0 +1,47 @@ +From 0664826badde416ca5b9e606066a21f366140892 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 7 Oct 2023 11:59:39 +0300 +Subject: thermal: core: prevent potential string overflow + +From: Dan Carpenter + +[ Upstream commit c99626092efca3061b387043d4a7399bf75fbdd5 ] + +The dev->id value comes from ida_alloc() so it's a number between zero +and INT_MAX. If it's too high then these sprintf()s will overflow. + +Fixes: 203d3d4aa482 ("the generic thermal sysfs driver") +Signed-off-by: Dan Carpenter +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/thermal/thermal_core.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index dd449945e1e5e..1cf49912dc96c 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -879,7 +879,8 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, + if (result) + goto release_ida; + +- sprintf(dev->attr_name, "cdev%d_trip_point", dev->id); ++ snprintf(dev->attr_name, sizeof(dev->attr_name), "cdev%d_trip_point", ++ dev->id); + sysfs_attr_init(&dev->attr.attr); + dev->attr.attr.name = dev->attr_name; + dev->attr.attr.mode = 0444; +@@ -888,7 +889,8 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, + if (result) + goto remove_symbol_link; + +- sprintf(dev->weight_attr_name, "cdev%d_weight", dev->id); ++ snprintf(dev->weight_attr_name, sizeof(dev->weight_attr_name), ++ "cdev%d_weight", dev->id); + sysfs_attr_init(&dev->weight_attr.attr); + dev->weight_attr.attr.name = dev->weight_attr_name; + dev->weight_attr.attr.mode = S_IWUSR | S_IRUGO; +-- +2.42.0 + diff --git a/queue-5.10/tipc-use-size_add-in-calls-to-struct_size.patch b/queue-5.10/tipc-use-size_add-in-calls-to-struct_size.patch new file mode 100644 index 00000000000..2f6750cd7fa --- /dev/null +++ b/queue-5.10/tipc-use-size_add-in-calls-to-struct_size.patch @@ -0,0 +1,48 @@ +From 4a26d2ecfec8afa5df7e359a057c400c111336c6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Sep 2023 13:16:26 -0600 +Subject: tipc: Use size_add() in calls to struct_size() + +From: Gustavo A. R. Silva + +[ Upstream commit 2506a91734754de690869824fb0d1ac592ec1266 ] + +If, for any reason, the open-coded arithmetic causes a wraparound, +the protection that `struct_size()` adds against potential integer +overflows is defeated. Fix this by hardening call to `struct_size()` +with `size_add()`. + +Fixes: e034c6d23bc4 ("tipc: Use struct_size() helper") +Signed-off-by: Gustavo A. R. Silva +Reviewed-by: Kees Cook +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/tipc/link.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/net/tipc/link.c b/net/tipc/link.c +index dbb1bc722ba9b..5f849c7300283 100644 +--- a/net/tipc/link.c ++++ b/net/tipc/link.c +@@ -1410,7 +1410,7 @@ u16 tipc_get_gap_ack_blks(struct tipc_gap_ack_blks **ga, struct tipc_link *l, + p = (struct tipc_gap_ack_blks *)msg_data(hdr); + sz = ntohs(p->len); + /* Sanity check */ +- if (sz == struct_size(p, gacks, p->ugack_cnt + p->bgack_cnt)) { ++ if (sz == struct_size(p, gacks, size_add(p->ugack_cnt, p->bgack_cnt))) { + /* Good, check if the desired type exists */ + if ((uc && p->ugack_cnt) || (!uc && p->bgack_cnt)) + goto ok; +@@ -1497,7 +1497,7 @@ static u16 tipc_build_gap_ack_blks(struct tipc_link *l, struct tipc_msg *hdr) + __tipc_build_gap_ack_blks(ga, l, ga->bgack_cnt) : 0; + + /* Total len */ +- len = struct_size(ga, gacks, ga->bgack_cnt + ga->ugack_cnt); ++ len = struct_size(ga, gacks, size_add(ga->bgack_cnt, ga->ugack_cnt)); + ga->len = htons(len); + return len; + } +-- +2.42.0 + diff --git a/queue-5.10/tools-iio-iio_generic_buffer-ensure-alignment.patch b/queue-5.10/tools-iio-iio_generic_buffer-ensure-alignment.patch new file mode 100644 index 00000000000..7ae1a6d03fa --- /dev/null +++ b/queue-5.10/tools-iio-iio_generic_buffer-ensure-alignment.patch @@ -0,0 +1,65 @@ +From 70829e0c36f0d36c06596f8f77b1198528fa5536 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 3 Oct 2023 12:57:47 +0300 +Subject: tools: iio: iio_generic_buffer ensure alignment + +From: Matti Vaittinen + +[ Upstream commit 2d3dff577dd0ea8fe9637a13822f7603c4a881c8 ] + +The iio_generic_buffer can return garbage values when the total size of +scan data is not a multiple of the largest element in the scan. This can be +demonstrated by reading a scan, consisting, for example of one 4-byte and +one 2-byte element, where the 4-byte element is first in the buffer. + +The IIO generic buffer code does not take into account the last two +padding bytes that are needed to ensure that the 4-byte data for next +scan is correctly aligned. + +Add the padding bytes required to align the next sample with the scan size. + +Signed-off-by: Matti Vaittinen +Fixes: e58537ccce73 ("staging: iio: update example application.") +Link: https://lore.kernel.org/r/ZRvlm4ktNLu+qmlf@dc78bmyyyyyyyyyyyyydt-3.rev.dnainternet.fi +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + tools/iio/iio_generic_buffer.c | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/tools/iio/iio_generic_buffer.c b/tools/iio/iio_generic_buffer.c +index e38c72fd58ccf..2fd10eab75b53 100644 +--- a/tools/iio/iio_generic_buffer.c ++++ b/tools/iio/iio_generic_buffer.c +@@ -52,9 +52,12 @@ enum autochan { + static unsigned int size_from_channelarray(struct iio_channel_info *channels, int num_channels) + { + unsigned int bytes = 0; +- int i = 0; ++ int i = 0, max = 0; ++ unsigned int misalignment; + + while (i < num_channels) { ++ if (channels[i].bytes > max) ++ max = channels[i].bytes; + if (bytes % channels[i].bytes == 0) + channels[i].location = bytes; + else +@@ -64,6 +67,14 @@ static unsigned int size_from_channelarray(struct iio_channel_info *channels, in + bytes = channels[i].location + channels[i].bytes; + i++; + } ++ /* ++ * We want the data in next sample to also be properly aligned so ++ * we'll add padding at the end if needed. Adding padding only ++ * works for channel data which size is 2^n bytes. ++ */ ++ misalignment = bytes % max; ++ if (misalignment) ++ bytes += max - misalignment; + + return bytes; + } +-- +2.42.0 + diff --git a/queue-5.10/tools-iio-iio_generic_buffer-fix-some-integer-type-a.patch b/queue-5.10/tools-iio-iio_generic_buffer-fix-some-integer-type-a.patch new file mode 100644 index 00000000000..88e14c7ac17 --- /dev/null +++ b/queue-5.10/tools-iio-iio_generic_buffer-fix-some-integer-type-a.patch @@ -0,0 +1,74 @@ +From 9fb65ba5b8b6b048bad575a08b7798861b9b36d6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jul 2023 09:24:07 +0000 +Subject: tools: iio: iio_generic_buffer: Fix some integer type and calculation + +From: Chenyuan Mi + +[ Upstream commit 49d736313d0975ddeb156f4f59801da833f78b30 ] + +In function size_from_channelarray(), the return value 'bytes' is defined +as int type. However, the calcution of 'bytes' in this function is designed +to use the unsigned int type. So it is necessary to change 'bytes' type to +unsigned int to avoid integer overflow. + +The size_from_channelarray() is called in main() function, its return value +is directly multipled by 'buf_len' and then used as the malloc() parameter. +The 'buf_len' is completely controllable by user, thus a multiplication +overflow may occur here. This could allocate an unexpected small area. + +Signed-off-by: Chenyuan Mi +Link: https://lore.kernel.org/r/20230725092407.62545-1-michenyuan@huawei.com +Signed-off-by: Jonathan Cameron +Stable-dep-of: 2d3dff577dd0 ("tools: iio: iio_generic_buffer ensure alignment") +Signed-off-by: Sasha Levin +--- + tools/iio/iio_generic_buffer.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +diff --git a/tools/iio/iio_generic_buffer.c b/tools/iio/iio_generic_buffer.c +index 7c72405537770..e38c72fd58ccf 100644 +--- a/tools/iio/iio_generic_buffer.c ++++ b/tools/iio/iio_generic_buffer.c +@@ -49,9 +49,9 @@ enum autochan { + * Has the side effect of filling the channels[i].location values used + * in processing the buffer output. + **/ +-static int size_from_channelarray(struct iio_channel_info *channels, int num_channels) ++static unsigned int size_from_channelarray(struct iio_channel_info *channels, int num_channels) + { +- int bytes = 0; ++ unsigned int bytes = 0; + int i = 0; + + while (i < num_channels) { +@@ -342,7 +342,7 @@ int main(int argc, char **argv) + ssize_t read_size; + int dev_num = -1, trig_num = -1; + char *buffer_access = NULL; +- int scan_size; ++ unsigned int scan_size; + int noevents = 0; + int notrigger = 0; + char *dummy; +@@ -612,7 +612,16 @@ int main(int argc, char **argv) + } + + scan_size = size_from_channelarray(channels, num_channels); +- data = malloc(scan_size * buf_len); ++ ++ size_t total_buf_len = scan_size * buf_len; ++ ++ if (scan_size > 0 && total_buf_len / scan_size != buf_len) { ++ ret = -EFAULT; ++ perror("Integer overflow happened when calculate scan_size * buf_len"); ++ goto error; ++ } ++ ++ data = malloc(total_buf_len); + if (!data) { + ret = -ENOMEM; + goto error; +-- +2.42.0 + diff --git a/queue-5.10/tools-iio-privatize-globals-and-functions-in-iio_gen.patch b/queue-5.10/tools-iio-privatize-globals-and-functions-in-iio_gen.patch new file mode 100644 index 00000000000..79057f63ab0 --- /dev/null +++ b/queue-5.10/tools-iio-privatize-globals-and-functions-in-iio_gen.patch @@ -0,0 +1,131 @@ +From 3d2f3477af444f09f158bfd9846d3a0e98620665 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Feb 2021 12:40:42 +0200 +Subject: tools: iio: privatize globals and functions in iio_generic_buffer.c + file + +From: Alexandru Ardelean + +[ Upstream commit ebe5112535b5cf389ca7d337cf6a0c1d885f9880 ] + +Mostly a tidy-up. +But also helps to understand the limits of scope of these functions and +globals. + +Signed-off-by: Alexandru Ardelean +Link: https://lore.kernel.org/r/20210215104043.91251-24-alexandru.ardelean@analog.com +Signed-off-by: Jonathan Cameron +Stable-dep-of: 2d3dff577dd0 ("tools: iio: iio_generic_buffer ensure alignment") +Signed-off-by: Sasha Levin +--- + tools/iio/iio_generic_buffer.c | 31 +++++++++++++++---------------- + 1 file changed, 15 insertions(+), 16 deletions(-) + +diff --git a/tools/iio/iio_generic_buffer.c b/tools/iio/iio_generic_buffer.c +index 34d63bcebcd28..7c72405537770 100644 +--- a/tools/iio/iio_generic_buffer.c ++++ b/tools/iio/iio_generic_buffer.c +@@ -49,7 +49,7 @@ enum autochan { + * Has the side effect of filling the channels[i].location values used + * in processing the buffer output. + **/ +-int size_from_channelarray(struct iio_channel_info *channels, int num_channels) ++static int size_from_channelarray(struct iio_channel_info *channels, int num_channels) + { + int bytes = 0; + int i = 0; +@@ -68,7 +68,7 @@ int size_from_channelarray(struct iio_channel_info *channels, int num_channels) + return bytes; + } + +-void print1byte(uint8_t input, struct iio_channel_info *info) ++static void print1byte(uint8_t input, struct iio_channel_info *info) + { + /* + * Shift before conversion to avoid sign extension +@@ -85,7 +85,7 @@ void print1byte(uint8_t input, struct iio_channel_info *info) + } + } + +-void print2byte(uint16_t input, struct iio_channel_info *info) ++static void print2byte(uint16_t input, struct iio_channel_info *info) + { + /* First swap if incorrect endian */ + if (info->be) +@@ -108,7 +108,7 @@ void print2byte(uint16_t input, struct iio_channel_info *info) + } + } + +-void print4byte(uint32_t input, struct iio_channel_info *info) ++static void print4byte(uint32_t input, struct iio_channel_info *info) + { + /* First swap if incorrect endian */ + if (info->be) +@@ -131,7 +131,7 @@ void print4byte(uint32_t input, struct iio_channel_info *info) + } + } + +-void print8byte(uint64_t input, struct iio_channel_info *info) ++static void print8byte(uint64_t input, struct iio_channel_info *info) + { + /* First swap if incorrect endian */ + if (info->be) +@@ -167,9 +167,8 @@ void print8byte(uint64_t input, struct iio_channel_info *info) + * to fill the location offsets. + * @num_channels: number of channels + **/ +-void process_scan(char *data, +- struct iio_channel_info *channels, +- int num_channels) ++static void process_scan(char *data, struct iio_channel_info *channels, ++ int num_channels) + { + int k; + +@@ -238,7 +237,7 @@ static int enable_disable_all_channels(char *dev_dir_name, int enable) + return 0; + } + +-void print_usage(void) ++static void print_usage(void) + { + fprintf(stderr, "Usage: generic_buffer [options]...\n" + "Capture, convert and output data from IIO device buffer\n" +@@ -257,12 +256,12 @@ void print_usage(void) + " -w Set delay between reads in us (event-less mode)\n"); + } + +-enum autochan autochannels = AUTOCHANNELS_DISABLED; +-char *dev_dir_name = NULL; +-char *buf_dir_name = NULL; +-bool current_trigger_set = false; ++static enum autochan autochannels = AUTOCHANNELS_DISABLED; ++static char *dev_dir_name = NULL; ++static char *buf_dir_name = NULL; ++static bool current_trigger_set = false; + +-void cleanup(void) ++static void cleanup(void) + { + int ret; + +@@ -294,14 +293,14 @@ void cleanup(void) + } + } + +-void sig_handler(int signum) ++static void sig_handler(int signum) + { + fprintf(stderr, "Caught signal %d\n", signum); + cleanup(); + exit(-signum); + } + +-void register_cleanup(void) ++static void register_cleanup(void) + { + struct sigaction sa = { .sa_handler = sig_handler }; + const int signums[] = { SIGINT, SIGTERM, SIGABRT }; +-- +2.42.0 + diff --git a/queue-5.10/tty-tty_jobctrl-fix-pid-memleak-in-disassociate_ctty.patch b/queue-5.10/tty-tty_jobctrl-fix-pid-memleak-in-disassociate_ctty.patch new file mode 100644 index 00000000000..5cffb7c4bfb --- /dev/null +++ b/queue-5.10/tty-tty_jobctrl-fix-pid-memleak-in-disassociate_ctty.patch @@ -0,0 +1,117 @@ +From a7fd25476d5a84ef23a9df70f37a707985704494 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 31 Aug 2023 10:33:29 +0800 +Subject: tty: tty_jobctrl: fix pid memleak in disassociate_ctty() + +From: Yi Yang + +[ Upstream commit 11e7f27b79757b6586645d87b95d5b78375ecdfc ] + +There is a pid leakage: +------------------------------ +unreferenced object 0xffff88810c181940 (size 224): + comm "sshd", pid 8191, jiffies 4294946950 (age 524.570s) + hex dump (first 32 bytes): + 01 00 00 00 00 00 00 00 00 00 00 00 ad 4e ad de .............N.. + ff ff ff ff 6b 6b 6b 6b ff ff ff ff ff ff ff ff ....kkkk........ + backtrace: + [] kmem_cache_alloc+0x5c6/0x9b0 + [] alloc_pid+0x72/0x570 + [] copy_process+0x1374/0x2470 + [] kernel_clone+0xb7/0x900 + [] __se_sys_clone+0x85/0xb0 + [] __x64_sys_clone+0x2b/0x30 + [] do_syscall_64+0x32/0x80 + [] entry_SYSCALL_64_after_hwframe+0x61/0xc6 + +It turns out that there is a race condition between disassociate_ctty() and +tty_signal_session_leader(), which caused this leakage. + +The pid memleak is triggered by the following race: +task[sshd] task[bash] +----------------------- ----------------------- + disassociate_ctty(); + spin_lock_irq(¤t->sighand->siglock); + put_pid(current->signal->tty_old_pgrp); + current->signal->tty_old_pgrp = NULL; + tty = tty_kref_get(current->signal->tty); + spin_unlock_irq(¤t->sighand->siglock); +tty_vhangup(); +tty_lock(tty); +... +tty_signal_session_leader(); +spin_lock_irq(&p->sighand->siglock); +... +if (tty->ctrl.pgrp) //tty->ctrl.pgrp is not NULL +p->signal->tty_old_pgrp = get_pid(tty->ctrl.pgrp); //An extra get +spin_unlock_irq(&p->sighand->siglock); +... +tty_unlock(tty); + if (tty) { + tty_lock(tty); + ... + put_pid(tty->ctrl.pgrp); + tty->ctrl.pgrp = NULL; //It's too late + ... + tty_unlock(tty); + } + +The issue is believed to be introduced by commit c8bcd9c5be24 ("tty: +Fix ->session locking") who moves the unlock of siglock in +disassociate_ctty() above "if (tty)", making a small window allowing +tty_signal_session_leader() to kick in. It can be easily reproduced by +adding a delay before "if (tty)" and at the entrance of +tty_signal_session_leader(). + +To fix this issue, we move "put_pid(current->signal->tty_old_pgrp)" after +"tty->ctrl.pgrp = NULL". + +Fixes: c8bcd9c5be24 ("tty: Fix ->session locking") +Signed-off-by: Yi Yang +Co-developed-by: GUO Zihua +Signed-off-by: GUO Zihua +Link: https://lore.kernel.org/r/20230831023329.165737-1-yiyang13@huawei.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/tty_jobctrl.c | 17 +++++++++++------ + 1 file changed, 11 insertions(+), 6 deletions(-) + +diff --git a/drivers/tty/tty_jobctrl.c b/drivers/tty/tty_jobctrl.c +index 95d67613b25b6..a27d021871748 100644 +--- a/drivers/tty/tty_jobctrl.c ++++ b/drivers/tty/tty_jobctrl.c +@@ -291,12 +291,7 @@ void disassociate_ctty(int on_exit) + return; + } + +- spin_lock_irq(¤t->sighand->siglock); +- put_pid(current->signal->tty_old_pgrp); +- current->signal->tty_old_pgrp = NULL; +- tty = tty_kref_get(current->signal->tty); +- spin_unlock_irq(¤t->sighand->siglock); +- ++ tty = get_current_tty(); + if (tty) { + unsigned long flags; + +@@ -311,6 +306,16 @@ void disassociate_ctty(int on_exit) + tty_kref_put(tty); + } + ++ /* If tty->ctrl.pgrp is not NULL, it may be assigned to ++ * current->signal->tty_old_pgrp in a race condition, and ++ * cause pid memleak. Release current->signal->tty_old_pgrp ++ * after tty->ctrl.pgrp set to NULL. ++ */ ++ spin_lock_irq(¤t->sighand->siglock); ++ put_pid(current->signal->tty_old_pgrp); ++ current->signal->tty_old_pgrp = NULL; ++ spin_unlock_irq(¤t->sighand->siglock); ++ + /* Now clear signal->tty under the lock */ + read_lock(&tasklist_lock); + session_clear_tty(task_session(current)); +-- +2.42.0 + diff --git a/queue-5.10/udp-add-missing-write_once-around-up-encap_rcv.patch b/queue-5.10/udp-add-missing-write_once-around-up-encap_rcv.patch new file mode 100644 index 00000000000..3485c03aa54 --- /dev/null +++ b/queue-5.10/udp-add-missing-write_once-around-up-encap_rcv.patch @@ -0,0 +1,43 @@ +From 006cbf68797753483135ac31ab467f5a6424a775 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Sep 2023 09:17:25 +0000 +Subject: udp: add missing WRITE_ONCE() around up->encap_rcv + +From: Eric Dumazet + +[ Upstream commit 6d5a12eb91224d707f8691dccb40a5719fe5466d ] + +UDP_ENCAP_ESPINUDP_NON_IKE setsockopt() writes over up->encap_rcv +while other cpus read it. + +Fixes: 067b207b281d ("[UDP]: Cleanup UDP encapsulation code") +Signed-off-by: Eric Dumazet +Reviewed-by: Willem de Bruijn +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + net/ipv4/udp.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c +index 913966e7703fc..476f79f1563a8 100644 +--- a/net/ipv4/udp.c ++++ b/net/ipv4/udp.c +@@ -2645,10 +2645,12 @@ int udp_lib_setsockopt(struct sock *sk, int level, int optname, + case UDP_ENCAP_ESPINUDP_NON_IKE: + #if IS_ENABLED(CONFIG_IPV6) + if (sk->sk_family == AF_INET6) +- up->encap_rcv = ipv6_stub->xfrm6_udp_encap_rcv; ++ WRITE_ONCE(up->encap_rcv, ++ ipv6_stub->xfrm6_udp_encap_rcv); + else + #endif +- up->encap_rcv = xfrm4_udp_encap_rcv; ++ WRITE_ONCE(up->encap_rcv, ++ xfrm4_udp_encap_rcv); + #endif + fallthrough; + case UDP_ENCAP_L2TPINUDP: +-- +2.42.0 + diff --git a/queue-5.10/usb-dwc2-fix-possible-null-pointer-dereference-cause.patch b/queue-5.10/usb-dwc2-fix-possible-null-pointer-dereference-cause.patch new file mode 100644 index 00000000000..39fa526b379 --- /dev/null +++ b/queue-5.10/usb-dwc2-fix-possible-null-pointer-dereference-cause.patch @@ -0,0 +1,69 @@ +From a0457255b324fa2f3f610b8d319bbbf8e67ee01f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 26 Sep 2023 10:44:04 +0800 +Subject: usb: dwc2: fix possible NULL pointer dereference caused by driver + concurrency + +From: Jia-Ju Bai + +[ Upstream commit ef307bc6ef04e8c1ea843231db58e3afaafa9fa6 ] + +In _dwc2_hcd_urb_enqueue(), "urb->hcpriv = NULL" is executed without +holding the lock "hsotg->lock". In _dwc2_hcd_urb_dequeue(): + + spin_lock_irqsave(&hsotg->lock, flags); + ... + if (!urb->hcpriv) { + dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); + goto out; + } + rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); // Use urb->hcpriv + ... +out: + spin_unlock_irqrestore(&hsotg->lock, flags); + +When _dwc2_hcd_urb_enqueue() and _dwc2_hcd_urb_dequeue() are +concurrently executed, the NULL check of "urb->hcpriv" can be executed +before "urb->hcpriv = NULL". After urb->hcpriv is NULL, it can be used +in the function call to dwc2_hcd_urb_dequeue(), which can cause a NULL +pointer dereference. + +This possible bug is found by an experimental static analysis tool +developed by myself. This tool analyzes the locking APIs to extract +function pairs that can be concurrently executed, and then analyzes the +instructions in the paired functions to identify possible concurrency +bugs including data races and atomicity violations. The above possible +bug is reported, when my tool analyzes the source code of Linux 6.5. + +To fix this possible bug, "urb->hcpriv = NULL" should be executed with +holding the lock "hsotg->lock". After using this patch, my tool never +reports the possible bug, with the kernelconfiguration allyesconfig for +x86_64. Because I have no associated hardware, I cannot test the patch +in runtime testing, and just verify it according to the code logic. + +Fixes: 33ad261aa62b ("usb: dwc2: host: spinlock urb_enqueue") +Signed-off-by: Jia-Ju Bai +Link: https://lore.kernel.org/r/20230926024404.832096-1-baijiaju@buaa.edu.cn +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/dwc2/hcd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 9279d3d3698c2..14925fedb01aa 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -4684,8 +4684,8 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, + if (qh_allocated && qh->channel && qh->channel->qh == qh) + qh->channel->qh = NULL; + fail2: +- spin_unlock_irqrestore(&hsotg->lock, flags); + urb->hcpriv = NULL; ++ spin_unlock_irqrestore(&hsotg->lock, flags); + kfree(qtd); + fail1: + if (qh_allocated) { +-- +2.42.0 + diff --git a/queue-5.10/usb-host-xhci-plat-fix-possible-kernel-oops-while-re.patch b/queue-5.10/usb-host-xhci-plat-fix-possible-kernel-oops-while-re.patch new file mode 100644 index 00000000000..38bbe34ee6e --- /dev/null +++ b/queue-5.10/usb-host-xhci-plat-fix-possible-kernel-oops-while-re.patch @@ -0,0 +1,80 @@ +From 0d087d2d3241fc86fde8c81b22b337120fa58212 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 19 Oct 2023 13:29:23 +0300 +Subject: usb: host: xhci-plat: fix possible kernel oops while resuming + +From: Sergey Shtylyov + +[ Upstream commit a5f928db59519a15e82ecba4ae3e7cbf5a44715a ] + +If this driver enables the xHC clocks while resuming from sleep, it calls +clk_prepare_enable() without checking for errors and blithely goes on to +read/write the xHC's registers -- which, with the xHC not being clocked, +at least on ARM32 usually causes an imprecise external abort exceptions +which cause kernel oops. Currently, the chips for which the driver does +the clock dance on suspend/resume seem to be the Broadcom STB SoCs, based +on ARM32 CPUs, as it seems... + +Found by Linux Verification Center (linuxtesting.org) with the Svace static +analysis tool. + +Fixes: 8bd954c56197 ("usb: host: xhci-plat: suspend and resume clocks") +Signed-off-by: Sergey Shtylyov +Signed-off-by: Mathias Nyman +Link: https://lore.kernel.org/r/20231019102924.2797346-19-mathias.nyman@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/host/xhci-plat.c | 23 +++++++++++++++++++---- + 1 file changed, 19 insertions(+), 4 deletions(-) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 972a44b2a7f12..e56a1fb9715a7 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -466,23 +466,38 @@ static int __maybe_unused xhci_plat_resume(struct device *dev) + int ret; + + if (!device_may_wakeup(dev) && (xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) { +- clk_prepare_enable(xhci->clk); +- clk_prepare_enable(xhci->reg_clk); ++ ret = clk_prepare_enable(xhci->clk); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(xhci->reg_clk); ++ if (ret) { ++ clk_disable_unprepare(xhci->clk); ++ return ret; ++ } + } + + ret = xhci_priv_resume_quirk(hcd); + if (ret) +- return ret; ++ goto disable_clks; + + ret = xhci_resume(xhci, 0); + if (ret) +- return ret; ++ goto disable_clks; + + pm_runtime_disable(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + return 0; ++ ++disable_clks: ++ if (!device_may_wakeup(dev) && (xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) { ++ clk_disable_unprepare(xhci->clk); ++ clk_disable_unprepare(xhci->reg_clk); ++ } ++ ++ return ret; + } + + static int __maybe_unused xhci_plat_runtime_suspend(struct device *dev) +-- +2.42.0 + diff --git a/queue-5.10/usb-usbip-fix-stub_dev-hub-disconnect.patch b/queue-5.10/usb-usbip-fix-stub_dev-hub-disconnect.patch new file mode 100644 index 00000000000..31d3274fa8b --- /dev/null +++ b/queue-5.10/usb-usbip-fix-stub_dev-hub-disconnect.patch @@ -0,0 +1,46 @@ +From 5813706346892d7174173730c6865c3adedac9de Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 15 Jun 2023 11:28:10 +0200 +Subject: USB: usbip: fix stub_dev hub disconnect + +From: Jonas Blixt + +[ Upstream commit 97475763484245916735a1aa9a3310a01d46b008 ] + +If a hub is disconnected that has device(s) that's attached to the usbip layer +the disconnect function might fail because it tries to release the port +on an already disconnected hub. + +Fixes: 6080cd0e9239 ("staging: usbip: claim ports used by shared devices") +Signed-off-by: Jonas Blixt +Acked-by: Shuah Khan +Link: https://lore.kernel.org/r/20230615092810.1215490-1-jonas.blixt@actia.se +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/usbip/stub_dev.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/usbip/stub_dev.c b/drivers/usb/usbip/stub_dev.c +index 3c6d452e3bf40..4104eea03e806 100644 +--- a/drivers/usb/usbip/stub_dev.c ++++ b/drivers/usb/usbip/stub_dev.c +@@ -462,8 +462,13 @@ static void stub_disconnect(struct usb_device *udev) + /* release port */ + rc = usb_hub_release_port(udev->parent, udev->portnum, + (struct usb_dev_state *) udev); +- if (rc) { +- dev_dbg(&udev->dev, "unable to release port\n"); ++ /* ++ * NOTE: If a HUB disconnect triggered disconnect of the down stream ++ * device usb_hub_release_port will return -ENODEV so we can safely ignore ++ * that error here. ++ */ ++ if (rc && (rc != -ENODEV)) { ++ dev_dbg(&udev->dev, "unable to release port (%i)\n", rc); + return; + } + +-- +2.42.0 + diff --git a/queue-5.10/vfs-fix-readahead-2-on-block-devices.patch b/queue-5.10/vfs-fix-readahead-2-on-block-devices.patch new file mode 100644 index 00000000000..2e96b76c5bb --- /dev/null +++ b/queue-5.10/vfs-fix-readahead-2-on-block-devices.patch @@ -0,0 +1,43 @@ +From 9718461c8cf61875007c8db26aea78bcd0b37a36 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 2 Oct 2023 20:57:04 -0500 +Subject: vfs: fix readahead(2) on block devices + +From: Reuben Hawkins + +[ Upstream commit 7116c0af4b8414b2f19fdb366eea213cbd9d91c2 ] + +Readahead was factored to call generic_fadvise. That refactor added an +S_ISREG restriction which broke readahead on block devices. + +In addition to S_ISREG, this change checks S_ISBLK to fix block device +readahead. There is no change in behavior with any file type besides block +devices in this change. + +Fixes: 3d8f7615319b ("vfs: implement readahead(2) using POSIX_FADV_WILLNEED") +Signed-off-by: Reuben Hawkins +Link: https://lore.kernel.org/r/20231003015704.2415-1-reubenhwk@gmail.com +Reviewed-by: Amir Goldstein +Signed-off-by: Christian Brauner +Signed-off-by: Sasha Levin +--- + mm/readahead.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/mm/readahead.c b/mm/readahead.c +index c5b0457415bef..d30bcf4bc63be 100644 +--- a/mm/readahead.c ++++ b/mm/readahead.c +@@ -625,7 +625,8 @@ ssize_t ksys_readahead(int fd, loff_t offset, size_t count) + */ + ret = -EINVAL; + if (!f.file->f_mapping || !f.file->f_mapping->a_ops || +- !S_ISREG(file_inode(f.file)->i_mode)) ++ (!S_ISREG(file_inode(f.file)->i_mode) && ++ !S_ISBLK(file_inode(f.file)->i_mode))) + goto out; + + ret = vfs_fadvise(f.file, offset, count, POSIX_FADV_WILLNEED); +-- +2.42.0 + diff --git a/queue-5.10/wifi-iwlwifi-use-fw-rate-for-non-data-frames.patch b/queue-5.10/wifi-iwlwifi-use-fw-rate-for-non-data-frames.patch new file mode 100644 index 00000000000..e34c7c5cdcc --- /dev/null +++ b/queue-5.10/wifi-iwlwifi-use-fw-rate-for-non-data-frames.patch @@ -0,0 +1,64 @@ +From 3c2f389e124ad826a72bed5008916b62f5d86108 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Sep 2023 14:56:45 +0300 +Subject: wifi: iwlwifi: Use FW rate for non-data frames + +From: Miri Korenblit + +[ Upstream commit 499d02790495958506a64f37ceda7e97345a50a8 ] + +Currently we are setting the rate in the tx cmd for +mgmt frames (e.g. during connection establishment). +This was problematic when sending mgmt frames in eSR mode, +as we don't know what link this frame will be sent on +(This is decided by the FW), so we don't know what is the +lowest rate. +Fix this by not setting the rate in tx cmd and rely +on FW to choose the right one. +Set rate only for injected frames with fixed rate, +or when no sta is given. +Also set for important frames (EAPOL etc.) the High Priority flag. + +Fixes: 055b22e770dd ("iwlwifi: mvm: Set Tx rate and flags when there is not station") +Signed-off-by: Miri Korenblit +Signed-off-by: Gregory Greenman +Link: https://lore.kernel.org/r/20230913145231.6c7e59620ee0.I6eaed3ccdd6dd62b9e664facc484081fc5275843@changeid +Signed-off-by: Johannes Berg +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/intel/iwlwifi/mvm/tx.c | 14 +++++++++----- + 1 file changed, 9 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c +index d310337b16251..99150fec151b8 100644 +--- a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c +@@ -532,16 +532,20 @@ iwl_mvm_set_tx_params(struct iwl_mvm *mvm, struct sk_buff *skb, + flags |= IWL_TX_FLAGS_ENCRYPT_DIS; + + /* +- * For data packets rate info comes from the fw. Only +- * set rate/antenna during connection establishment or in case +- * no station is given. ++ * For data and mgmt packets rate info comes from the fw. Only ++ * set rate/antenna for injected frames with fixed rate, or ++ * when no sta is given. + */ +- if (!sta || !ieee80211_is_data(hdr->frame_control) || +- mvmsta->sta_state < IEEE80211_STA_AUTHORIZED) { ++ if (unlikely(!sta || ++ info->control.flags & IEEE80211_TX_CTRL_RATE_INJECT)) { + flags |= IWL_TX_FLAGS_CMD_RATE; + rate_n_flags = + iwl_mvm_get_tx_rate_n_flags(mvm, info, sta, + hdr->frame_control); ++ } else if (!ieee80211_is_data(hdr->frame_control) || ++ mvmsta->sta_state < IEEE80211_STA_AUTHORIZED) { ++ /* These are important frames */ ++ flags |= IWL_TX_FLAGS_HIGH_PRI; + } + + if (mvm->trans->trans_cfg->device_family >= +-- +2.42.0 + diff --git a/queue-5.10/wifi-mt76-mt7603-rework-fix-rx-pse-hang-check.patch b/queue-5.10/wifi-mt76-mt7603-rework-fix-rx-pse-hang-check.patch new file mode 100644 index 00000000000..07daba3beee --- /dev/null +++ b/queue-5.10/wifi-mt76-mt7603-rework-fix-rx-pse-hang-check.patch @@ -0,0 +1,87 @@ +From 317443d0e5cd755366f5e827f775da2c05adf739 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 28 Jul 2023 09:51:01 +0200 +Subject: wifi: mt76: mt7603: rework/fix rx pse hang check + +From: Felix Fietkau + +[ Upstream commit baa19b2e4b7bbb509a7ca7939c8785477dcd40ee ] + +It turns out that the code in mt7603_rx_pse_busy() does not detect actual +hardware hangs, it only checks for busy conditions in PSE. +A reset should only be performed if these conditions are true and if there +is no rx activity as well. +Reset the counter whenever a rx interrupt occurs. In order to also deal with +a fully loaded CPU that leaves interrupts disabled with continuous NAPI +polling, also check for pending rx interrupts in the function itself. + +Fixes: c8846e101502 ("mt76: add driver for MT7603E and MT7628/7688") +Signed-off-by: Felix Fietkau +Signed-off-by: Sasha Levin +--- + .../net/wireless/mediatek/mt76/mt7603/core.c | 2 ++ + .../net/wireless/mediatek/mt76/mt7603/mac.c | 23 +++++++++++++------ + 2 files changed, 18 insertions(+), 7 deletions(-) + +diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/core.c b/drivers/net/wireless/mediatek/mt76/mt7603/core.c +index 60a996b63c0c0..915b8349146af 100644 +--- a/drivers/net/wireless/mediatek/mt76/mt7603/core.c ++++ b/drivers/net/wireless/mediatek/mt76/mt7603/core.c +@@ -42,11 +42,13 @@ irqreturn_t mt7603_irq_handler(int irq, void *dev_instance) + } + + if (intr & MT_INT_RX_DONE(0)) { ++ dev->rx_pse_check = 0; + mt7603_irq_disable(dev, MT_INT_RX_DONE(0)); + napi_schedule(&dev->mt76.napi[0]); + } + + if (intr & MT_INT_RX_DONE(1)) { ++ dev->rx_pse_check = 0; + mt7603_irq_disable(dev, MT_INT_RX_DONE(1)); + napi_schedule(&dev->mt76.napi[1]); + } +diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/mac.c b/drivers/net/wireless/mediatek/mt76/mt7603/mac.c +index f665a1c95eed2..9eb898ebbb445 100644 +--- a/drivers/net/wireless/mediatek/mt76/mt7603/mac.c ++++ b/drivers/net/wireless/mediatek/mt76/mt7603/mac.c +@@ -1535,20 +1535,29 @@ static bool mt7603_rx_pse_busy(struct mt7603_dev *dev) + { + u32 addr, val; + +- if (mt76_rr(dev, MT_MCU_DEBUG_RESET) & MT_MCU_DEBUG_RESET_QUEUES) +- return true; +- + if (mt7603_rx_fifo_busy(dev)) +- return false; ++ goto out; + + addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS); + mt76_wr(dev, addr, 3); + val = mt76_rr(dev, addr) >> 16; + +- if (is_mt7628(dev) && (val & 0x4001) == 0x4001) +- return true; ++ if (!(val & BIT(0))) ++ return false; ++ ++ if (is_mt7628(dev)) ++ val &= 0xa000; ++ else ++ val &= 0x8000; ++ if (!val) ++ return false; ++ ++out: ++ if (mt76_rr(dev, MT_INT_SOURCE_CSR) & ++ (MT_INT_RX_DONE(0) | MT_INT_RX_DONE(1))) ++ return false; + +- return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001; ++ return true; + } + + static bool +-- +2.42.0 + diff --git a/queue-5.10/wifi-rtlwifi-fix-edca-limit-set-by-bt-coexistence.patch b/queue-5.10/wifi-rtlwifi-fix-edca-limit-set-by-bt-coexistence.patch new file mode 100644 index 00000000000..c07c3dd6c51 --- /dev/null +++ b/queue-5.10/wifi-rtlwifi-fix-edca-limit-set-by-bt-coexistence.patch @@ -0,0 +1,70 @@ +From ca07a795335a958c3334bb78fda5227c74ca2bbd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Sep 2023 08:23:19 +0300 +Subject: wifi: rtlwifi: fix EDCA limit set by BT coexistence + +From: Dmitry Antipov + +[ Upstream commit 3391ee7f9ea508c375d443cd712c2e699be235b4 ] + +In 'rtl92c_dm_check_edca_turbo()', 'rtl88e_dm_check_edca_turbo()', +and 'rtl8723e_dm_check_edca_turbo()', the DL limit should be set +from the corresponding field of 'rtlpriv->btcoexist' rather than +UL. Compile tested only. + +Fixes: 0529c6b81761 ("rtlwifi: rtl8723ae: Update driver to match 06/28/14 Realtek version") +Fixes: c151aed6aa14 ("rtlwifi: rtl8188ee: Update driver to match Realtek release of 06282014") +Fixes: beb5bc402043 ("rtlwifi: rtl8192c-common: Convert common dynamic management routines for addition of rtl8192se and rtl8192de") +Signed-off-by: Dmitry Antipov +Acked-by: Ping-Ke Shih +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230928052327.120178-1-dmantipov@yandex.ru +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c | 2 +- + drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c | 2 +- + drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c +index d10c14c694da8..a1b920843b869 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c +@@ -799,7 +799,7 @@ static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw) + } + + if (rtlpriv->btcoexist.bt_edca_dl != 0) { +- edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; ++ edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; + bt_change_edca = true; + } + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c +index 265a1a336304e..c493e50b7bc58 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c +@@ -640,7 +640,7 @@ static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw) + } + + if (rtlpriv->btcoexist.bt_edca_dl != 0) { +- edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; ++ edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; + bt_change_edca = true; + } + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c +index 8ada31380efa4..0ff8e355c23a4 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c +@@ -466,7 +466,7 @@ static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw) + } + + if (rtlpriv->btcoexist.bt_edca_dl != 0) { +- edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; ++ edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; + bt_change_edca = true; + } + +-- +2.42.0 + diff --git a/queue-5.10/wifi-rtw88-debug-fix-the-null-vs-is_err-bug-for-debu.patch b/queue-5.10/wifi-rtw88-debug-fix-the-null-vs-is_err-bug-for-debu.patch new file mode 100644 index 00000000000..5fe9a86b966 --- /dev/null +++ b/queue-5.10/wifi-rtw88-debug-fix-the-null-vs-is_err-bug-for-debu.patch @@ -0,0 +1,42 @@ +From 5c52db36bbe526728e10e7e6d0ab5ea8e436a19e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Sep 2023 13:06:50 +0800 +Subject: wifi: rtw88: debug: Fix the NULL vs IS_ERR() bug for + debugfs_create_file() + +From: Jinjie Ruan + +[ Upstream commit 74f7957c9b1b95553faaf146a2553e023a9d1720 ] + +Since debugfs_create_file() return ERR_PTR and never return NULL, so use +IS_ERR() to check it instead of checking NULL. + +Fixes: e3037485c68e ("rtw88: new Realtek 802.11ac driver") +Signed-off-by: Jinjie Ruan +Acked-by: Ping-Ke Shih +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230919050651.962694-1-ruanjinjie@huawei.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/realtek/rtw88/debug.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw88/debug.c b/drivers/net/wireless/realtek/rtw88/debug.c +index 8bb6cc8ca74e5..83413cda9bc5e 100644 +--- a/drivers/net/wireless/realtek/rtw88/debug.c ++++ b/drivers/net/wireless/realtek/rtw88/debug.c +@@ -901,9 +901,9 @@ static struct rtw_debugfs_priv rtw_debug_priv_coex_info = { + #define rtw_debugfs_add_core(name, mode, fopname, parent) \ + do { \ + rtw_debug_priv_ ##name.rtwdev = rtwdev; \ +- if (!debugfs_create_file(#name, mode, \ ++ if (IS_ERR(debugfs_create_file(#name, mode, \ + parent, &rtw_debug_priv_ ##name,\ +- &file_ops_ ##fopname)) \ ++ &file_ops_ ##fopname))) \ + pr_debug("Unable to initialize debugfs:%s\n", \ + #name); \ + } while (0) +-- +2.42.0 + diff --git a/queue-5.10/x86-boot-fix-incorrect-startup_gdt_descr.size.patch b/queue-5.10/x86-boot-fix-incorrect-startup_gdt_descr.size.patch new file mode 100644 index 00000000000..14e58a9cdf1 --- /dev/null +++ b/queue-5.10/x86-boot-fix-incorrect-startup_gdt_descr.size.patch @@ -0,0 +1,42 @@ +From 8e80756a7e91e976f680b57a3c5237516dded319 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 7 Aug 2023 16:45:47 +0800 +Subject: x86/boot: Fix incorrect startup_gdt_descr.size + +From: Yuntao Wang + +[ Upstream commit 001470fed5959d01faecbd57fcf2f60294da0de1 ] + +Since the size value is added to the base address to yield the last valid +byte address of the GDT, the current size value of startup_gdt_descr is +incorrect (too large by one), fix it. + +[ mingo: This probably never mattered, because startup_gdt[] is only used + in a very controlled fashion - but make it consistent nevertheless. ] + +Fixes: 866b556efa12 ("x86/head/64: Install startup GDT") +Signed-off-by: Yuntao Wang +Signed-off-by: Ingo Molnar +Cc: "H. Peter Anvin" +Link: https://lore.kernel.org/r/20230807084547.217390-1-ytcoode@gmail.com +Signed-off-by: Sasha Levin +--- + arch/x86/kernel/head64.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c +index efe13ab366f47..8596b4dca9455 100644 +--- a/arch/x86/kernel/head64.c ++++ b/arch/x86/kernel/head64.c +@@ -80,7 +80,7 @@ static struct desc_struct startup_gdt[GDT_ENTRIES] = { + * while the kernel still uses a direct mapping. + */ + static struct desc_ptr startup_gdt_descr = { +- .size = sizeof(startup_gdt), ++ .size = sizeof(startup_gdt)-1, + .address = 0, + }; + +-- +2.42.0 + diff --git a/queue-5.10/x86-srso-fix-sbpb-enablement-for-possible-future-fix.patch b/queue-5.10/x86-srso-fix-sbpb-enablement-for-possible-future-fix.patch new file mode 100644 index 00000000000..a0358c90b80 --- /dev/null +++ b/queue-5.10/x86-srso-fix-sbpb-enablement-for-possible-future-fix.patch @@ -0,0 +1,39 @@ +From b6679b95fd0c349697be0f3df928c33cc2d4287a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Sep 2023 22:04:49 -0700 +Subject: x86/srso: Fix SBPB enablement for (possible) future fixed HW + +From: Josh Poimboeuf + +[ Upstream commit 1d1142ac51307145dbb256ac3535a1d43a1c9800 ] + +Make the SBPB check more robust against the (possible) case where future +HW has SRSO fixed but doesn't have the SRSO_NO bit set. + +Fixes: 1b5277c0ea0b ("x86/srso: Add SRSO_NO support") +Signed-off-by: Josh Poimboeuf +Signed-off-by: Ingo Molnar +Signed-off-by: Borislav Petkov (AMD) +Acked-by: Borislav Petkov (AMD) +Link: https://lore.kernel.org/r/cee5050db750b391c9f35f5334f8ff40e66c01b9.1693889988.git.jpoimboe@kernel.org +Signed-off-by: Sasha Levin +--- + arch/x86/kernel/cpu/bugs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c +index ec3ddb9a456ba..d9fda0b6eb19e 100644 +--- a/arch/x86/kernel/cpu/bugs.c ++++ b/arch/x86/kernel/cpu/bugs.c +@@ -2407,7 +2407,7 @@ static void __init srso_select_mitigation(void) + pr_info("%s%s\n", srso_strings[srso_mitigation], (has_microcode ? "" : ", no microcode")); + + pred_cmd: +- if ((boot_cpu_has(X86_FEATURE_SRSO_NO) || srso_cmd == SRSO_CMD_OFF) && ++ if ((!boot_cpu_has_bug(X86_BUG_SRSO) || srso_cmd == SRSO_CMD_OFF) && + boot_cpu_has(X86_FEATURE_SBPB)) + x86_pred_cmd = PRED_CMD_SBPB; + } +-- +2.42.0 + diff --git a/queue-5.10/xen-pciback-consider-intx-disabled-when-msi-msi-x-is.patch b/queue-5.10/xen-pciback-consider-intx-disabled-when-msi-msi-x-is.patch new file mode 100644 index 00000000000..eeaffa4256a --- /dev/null +++ b/queue-5.10/xen-pciback-consider-intx-disabled-when-msi-msi-x-is.patch @@ -0,0 +1,131 @@ +From caba343a4afb48e2255187096f4d223217791ef8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Oct 2023 15:13:25 +0200 +Subject: xen-pciback: Consider INTx disabled when MSI/MSI-X is enabled +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marek Marczykowski-Górecki + +[ Upstream commit 2c269f42d0f382743ab230308b836ffe5ae9b2ae ] + +Linux enables MSI-X before disabling INTx, but keeps MSI-X masked until +the table is filled. Then it disables INTx just before clearing MASKALL +bit. Currently this approach is rejected by xen-pciback. +According to the PCIe spec, device cannot use INTx when MSI/MSI-X is +enabled (in other words: enabling MSI/MSI-X implicitly disables INTx). + +Change the logic to consider INTx disabled if MSI/MSI-X is enabled. This +applies to three places: + - checking currently enabled interrupts type, + - transition to MSI/MSI-X - where INTx would be implicitly disabled, + - clearing INTx disable bit - which can be allowed even if MSI/MSI-X is + enabled, as device should consider INTx disabled anyway in that case + +Fixes: 5e29500eba2a ("xen-pciback: Allow setting PCI_MSIX_FLAGS_MASKALL too") +Signed-off-by: Marek Marczykowski-Górecki +Acked-by: Juergen Gross +Link: https://lore.kernel.org/r/20231016131348.1734721-1-marmarek@invisiblethingslab.com +Signed-off-by: Juergen Gross +Signed-off-by: Sasha Levin +--- + drivers/xen/xen-pciback/conf_space.c | 19 +++++++++++------ + .../xen/xen-pciback/conf_space_capability.c | 8 ++++++- + drivers/xen/xen-pciback/conf_space_header.c | 21 +++---------------- + 3 files changed, 23 insertions(+), 25 deletions(-) + +diff --git a/drivers/xen/xen-pciback/conf_space.c b/drivers/xen/xen-pciback/conf_space.c +index 059de92aea7d0..d47eee6c51435 100644 +--- a/drivers/xen/xen-pciback/conf_space.c ++++ b/drivers/xen/xen-pciback/conf_space.c +@@ -288,12 +288,6 @@ int xen_pcibk_get_interrupt_type(struct pci_dev *dev) + u16 val; + int ret = 0; + +- err = pci_read_config_word(dev, PCI_COMMAND, &val); +- if (err) +- return err; +- if (!(val & PCI_COMMAND_INTX_DISABLE)) +- ret |= INTERRUPT_TYPE_INTX; +- + /* + * Do not trust dev->msi(x)_enabled here, as enabling could be done + * bypassing the pci_*msi* functions, by the qemu. +@@ -316,6 +310,19 @@ int xen_pcibk_get_interrupt_type(struct pci_dev *dev) + if (val & PCI_MSIX_FLAGS_ENABLE) + ret |= INTERRUPT_TYPE_MSIX; + } ++ ++ /* ++ * PCIe spec says device cannot use INTx if MSI/MSI-X is enabled, ++ * so check for INTx only when both are disabled. ++ */ ++ if (!ret) { ++ err = pci_read_config_word(dev, PCI_COMMAND, &val); ++ if (err) ++ return err; ++ if (!(val & PCI_COMMAND_INTX_DISABLE)) ++ ret |= INTERRUPT_TYPE_INTX; ++ } ++ + return ret ?: INTERRUPT_TYPE_NONE; + } + +diff --git a/drivers/xen/xen-pciback/conf_space_capability.c b/drivers/xen/xen-pciback/conf_space_capability.c +index 097316a741268..1948a9700c8fa 100644 +--- a/drivers/xen/xen-pciback/conf_space_capability.c ++++ b/drivers/xen/xen-pciback/conf_space_capability.c +@@ -236,10 +236,16 @@ static int msi_msix_flags_write(struct pci_dev *dev, int offset, u16 new_value, + return PCIBIOS_SET_FAILED; + + if (new_value & field_config->enable_bit) { +- /* don't allow enabling together with other interrupt types */ ++ /* ++ * Don't allow enabling together with other interrupt type, but do ++ * allow enabling MSI(-X) while INTx is still active to please Linuxes ++ * MSI(-X) startup sequence. It is safe to do, as according to PCI ++ * spec, device with enabled MSI(-X) shouldn't use INTx. ++ */ + int int_type = xen_pcibk_get_interrupt_type(dev); + + if (int_type == INTERRUPT_TYPE_NONE || ++ int_type == INTERRUPT_TYPE_INTX || + int_type == field_config->int_type) + goto write; + return PCIBIOS_SET_FAILED; +diff --git a/drivers/xen/xen-pciback/conf_space_header.c b/drivers/xen/xen-pciback/conf_space_header.c +index ac45cdc38e859..fcaa050d692d2 100644 +--- a/drivers/xen/xen-pciback/conf_space_header.c ++++ b/drivers/xen/xen-pciback/conf_space_header.c +@@ -104,24 +104,9 @@ static int command_write(struct pci_dev *dev, int offset, u16 value, void *data) + pci_clear_mwi(dev); + } + +- if (dev_data && dev_data->allow_interrupt_control) { +- if ((cmd->val ^ value) & PCI_COMMAND_INTX_DISABLE) { +- if (value & PCI_COMMAND_INTX_DISABLE) { +- pci_intx(dev, 0); +- } else { +- /* Do not allow enabling INTx together with MSI or MSI-X. */ +- switch (xen_pcibk_get_interrupt_type(dev)) { +- case INTERRUPT_TYPE_NONE: +- pci_intx(dev, 1); +- break; +- case INTERRUPT_TYPE_INTX: +- break; +- default: +- return PCIBIOS_SET_FAILED; +- } +- } +- } +- } ++ if (dev_data && dev_data->allow_interrupt_control && ++ ((cmd->val ^ value) & PCI_COMMAND_INTX_DISABLE)) ++ pci_intx(dev, !(value & PCI_COMMAND_INTX_DISABLE)); + + cmd->val = value; + +-- +2.42.0 + diff --git a/queue-5.10/xhci-loosen-rpm-as-default-policy-to-cover-for-amd-x.patch b/queue-5.10/xhci-loosen-rpm-as-default-policy-to-cover-for-amd-x.patch new file mode 100644 index 00000000000..23fd0edbf55 --- /dev/null +++ b/queue-5.10/xhci-loosen-rpm-as-default-policy-to-cover-for-amd-x.patch @@ -0,0 +1,47 @@ +From be53d5b065169ec880b6a5063b124a4bd529df9e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 19 Oct 2023 13:29:19 +0300 +Subject: xhci: Loosen RPM as default policy to cover for AMD xHC 1.1 + +From: Basavaraj Natikar + +[ Upstream commit 4baf1218150985ee3ab0a27220456a1f027ea0ac ] + +The AMD USB host controller (1022:43f7) isn't going into PCI D3 by default +without anything connected. This is because the policy that was introduced +by commit a611bf473d1f ("xhci-pci: Set runtime PM as default policy on all +xHC 1.2 or later devices") only covered 1.2 or later. + +The 1.1 specification also has the same requirement as the 1.2 +specification for D3 support. So expand the runtime PM as default policy +to all AMD 1.1 devices as well. + +Fixes: a611bf473d1f ("xhci-pci: Set runtime PM as default policy on all xHC 1.2 or later devices") +Link: https://composter.com.ua/documents/xHCI_Specification_for_USB.pdf +Co-developed-by: Mario Limonciello +Signed-off-by: Mario Limonciello +Signed-off-by: Basavaraj Natikar +Signed-off-by: Mathias Nyman +Link: https://lore.kernel.org/r/20231019102924.2797346-15-mathias.nyman@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/host/xhci-pci.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c +index 8034e643a4afd..7d0c2cccbfc0f 100644 +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -345,6 +345,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) + /* xHC spec requires PCI devices to support D3hot and D3cold */ + if (xhci->hci_version >= 0x120) + xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; ++ else if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version >= 0x110) ++ xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; + + if (xhci->quirks & XHCI_RESET_ON_RESUME) + xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, +-- +2.42.0 +