From: Sasha Levin Date: Thu, 28 Sep 2023 20:55:25 +0000 (-0400) Subject: Fixes for 5.15 X-Git-Tag: v6.5.6~85 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=9cce57ddb8acf2f73216f658f1c32a9a42d2b3ad;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.15 Signed-off-by: Sasha Levin --- diff --git a/queue-5.15/arm64-dts-qcom-sdm845-db845c-mark-cont-splash-memory.patch b/queue-5.15/arm64-dts-qcom-sdm845-db845c-mark-cont-splash-memory.patch new file mode 100644 index 00000000000..93f975f3cf6 --- /dev/null +++ b/queue-5.15/arm64-dts-qcom-sdm845-db845c-mark-cont-splash-memory.patch @@ -0,0 +1,58 @@ +From c9add7fc549985de3b89a6b30d6458a107e66f96 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 26 Jul 2023 18:57:19 +0530 +Subject: arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as + reserved + +From: Amit Pundir + +[ Upstream commit 110e70fccce4f22b53986ae797d665ffb1950aa6 ] + +Adding a reserved memory region for the framebuffer memory +(the splash memory region set up by the bootloader). + +It fixes a kernel panic (arm-smmu: Unhandled context fault +at this particular memory region) reported on DB845c running +v5.10.y. + +Cc: stable@vger.kernel.org # v5.10+ +Reviewed-by: Caleb Connolly +Signed-off-by: Amit Pundir +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20230726132719.2117369-2-amit.pundir@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +index 5ce270f0b2ec1..c25d7328c6ccc 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts ++++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +@@ -85,6 +85,14 @@ + }; + }; + ++ reserved-memory { ++ /* Cont splash region set up by the bootloader */ ++ cont_splash_mem: framebuffer@9d400000 { ++ reg = <0x0 0x9d400000 0x0 0x2400000>; ++ no-map; ++ }; ++ }; ++ + lt9611_1v8: lt9611-vdd18-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V8"; +@@ -482,6 +490,7 @@ + }; + + &mdss { ++ memory-region = <&cont_splash_mem>; + status = "okay"; + }; + +-- +2.40.1 + diff --git a/queue-5.15/ata-ahci-add-elkhart-lake-ahci-controller.patch b/queue-5.15/ata-ahci-add-elkhart-lake-ahci-controller.patch new file mode 100644 index 00000000000..2e6130654de --- /dev/null +++ b/queue-5.15/ata-ahci-add-elkhart-lake-ahci-controller.patch @@ -0,0 +1,66 @@ +From 1f3d5748e591d13de71c0ae715fc83a8af4c3294 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 29 Aug 2023 13:33:58 +0200 +Subject: ata: ahci: Add Elkhart Lake AHCI controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Werner Fischer + +[ Upstream commit 2a2df98ec592667927b5c1351afa6493ea125c9f ] + +Elkhart Lake is the successor of Apollo Lake and Gemini Lake. These +CPUs and their PCHs are used in mobile and embedded environments. + +With this patch I suggest that Elkhart Lake SATA controllers [1] should +use the default LPM policy for mobile chipsets. +The disadvantage of missing hot-plug support with this setting should +not be an issue, as those CPUs are used in embedded environments and +not in servers with hot-plug backplanes. + +We discovered that the Elkhart Lake SATA controllers have been missing +in ahci.c after a customer reported the throttling of his SATA SSD +after a short period of higher I/O. We determined the high temperature +of the SSD controller in idle mode as the root cause for that. + +Depending on the used SSD, we have seen up to 1.8 Watt lower system +idle power usage and up to 30°C lower SSD controller temperatures in +our tests, when we set med_power_with_dipm manually. I have provided a +table showing seven different SATA SSDs from ATP, Intel/Solidigm and +Samsung [2]. + +Intel lists a total of 3 SATA controller IDs (4B60, 4B62, 4B63) in [1] +for those mobile PCHs. +This commit just adds 0x4b63 as I do not have test systems with 0x4b60 +and 0x4b62 SATA controllers. +I have tested this patch with a system which uses 0x4b63 as SATA +controller. + +[1] https://sata-io.org/product/8803 +[2] https://www.thomas-krenn.com/en/wiki/SATA_Link_Power_Management#Example_LES_v4 + +Signed-off-by: Werner Fischer +Cc: stable@vger.kernel.org +Signed-off-by: Damien Le Moal +Signed-off-by: Sasha Levin +--- + drivers/ata/ahci.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c +index 3679433108eca..3147b2e6cd8c9 100644 +--- a/drivers/ata/ahci.c ++++ b/drivers/ata/ahci.c +@@ -425,6 +425,8 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ + { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ + { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ ++ /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ ++ { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */ + + /* JMicron 360/1/3/5/6, match class to avoid IDE function */ + { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, +-- +2.40.1 + diff --git a/queue-5.15/ata-ahci-add-support-for-amd-a85-fch-hudson-d4.patch b/queue-5.15/ata-ahci-add-support-for-amd-a85-fch-hudson-d4.patch new file mode 100644 index 00000000000..dfd7bace9d3 --- /dev/null +++ b/queue-5.15/ata-ahci-add-support-for-amd-a85-fch-hudson-d4.patch @@ -0,0 +1,64 @@ +From 2c405deb18f1cb6ff06c2c7d9c9ef56d9a92b6b2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 5 Jan 2022 16:36:18 +0100 +Subject: ata: ahci: Add support for AMD A85 FCH (Hudson D4) + +From: Paul Menzel + +[ Upstream commit a17ab7aba5df4135ef77d7f6d7105e1ea414936f ] + +Add support for the AMD A85 FCH (Hudson D4) AHCI adapter. + +Since this adapter does not require the default 200 ms debounce delay +in sata_link_resume(), create a new board board_ahci_no_debounce_delay +with the link flag ATA_LFLAG_NO_DEBOUNCE_DELAY, and, for now, configure +the AMD A85 FCH (Hudson D4) to use it. On the ASUS F2A85-M PRO it +reduces the Linux kernel boot time by the expected 200 ms from 787 ms +to 585 ms. + +Signed-off-by: Paul Menzel +Cc: Tejun Heo +Signed-off-by: Damien Le Moal +Stable-dep-of: 2a2df98ec592 ("ata: ahci: Add Elkhart Lake AHCI controller") +Signed-off-by: Sasha Levin +--- + drivers/ata/ahci.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c +index 719fe2e2b36c2..44658ba331c6a 100644 +--- a/drivers/ata/ahci.c ++++ b/drivers/ata/ahci.c +@@ -51,6 +51,7 @@ enum board_ids { + board_ahci, + board_ahci_ign_iferr, + board_ahci_mobile, ++ board_ahci_no_debounce_delay, + board_ahci_nomsi, + board_ahci_noncq, + board_ahci_nosntf, +@@ -142,6 +143,13 @@ static const struct ata_port_info ahci_port_info[] = { + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, + }, ++ [board_ahci_no_debounce_delay] = { ++ .flags = AHCI_FLAG_COMMON, ++ .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, ++ .pio_mask = ATA_PIO4, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &ahci_ops, ++ }, + [board_ahci_nomsi] = { + AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), + .flags = AHCI_FLAG_COMMON, +@@ -442,6 +450,7 @@ static const struct pci_device_id ahci_pci_tbl[] = { + board_ahci_al }, + /* AMD */ + { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ ++ { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ + { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ + { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */ + /* AMD is using RAID class only for ahci controllers */ +-- +2.40.1 + diff --git a/queue-5.15/ata-ahci-rename-board_ahci_mobile.patch b/queue-5.15/ata-ahci-rename-board_ahci_mobile.patch new file mode 100644 index 00000000000..8d913ee66a1 --- /dev/null +++ b/queue-5.15/ata-ahci-rename-board_ahci_mobile.patch @@ -0,0 +1,211 @@ +From 1730510eb34a7db2f7f019d7ca5839c3662d5402 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 25 Feb 2022 11:23:17 -0600 +Subject: ata: ahci: Rename board_ahci_mobile + +From: Mario Limonciello + +[ Upstream commit 099849af27f74981c7e660dd93ff6a987307c1f2 ] + +This board definition was originally created for mobile devices to +designate default link power managmeent policy to influence runtime +power consumption. + +As this is interesting for more than just mobile designs, rename the +board to `board_ahci_low_power` to make it clear it is about default +policy. + +Reviewed-by: Hans de Goede +Reviewed-by: Paul Menzel +Signed-off-by: Mario Limonciello +Signed-off-by: Damien Le Moal +Stable-dep-of: 2a2df98ec592 ("ata: ahci: Add Elkhart Lake AHCI controller") +Signed-off-by: Sasha Levin +--- + drivers/ata/ahci.c | 96 +++++++++++++++++++++++----------------------- + 1 file changed, 48 insertions(+), 48 deletions(-) + +diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c +index 44658ba331c6a..3679433108eca 100644 +--- a/drivers/ata/ahci.c ++++ b/drivers/ata/ahci.c +@@ -50,7 +50,7 @@ enum board_ids { + /* board IDs by feature in alphabetical order */ + board_ahci, + board_ahci_ign_iferr, +- board_ahci_mobile, ++ board_ahci_low_power, + board_ahci_no_debounce_delay, + board_ahci_nomsi, + board_ahci_noncq, +@@ -136,7 +136,7 @@ static const struct ata_port_info ahci_port_info[] = { + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, + }, +- [board_ahci_mobile] = { ++ [board_ahci_low_power] = { + AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, +@@ -276,13 +276,13 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ + { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ + { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ +- { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ +- { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ +- { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ +- { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ +- { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ ++ { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */ ++ { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */ ++ { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */ ++ { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */ ++ { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ +- { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ ++ { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ + { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ + { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ +@@ -292,9 +292,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ + { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ + { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ +- { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ ++ { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */ + { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ +- { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ ++ { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */ + { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ + { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ + { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ +@@ -317,9 +317,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ + { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ + { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ +- { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ ++ { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */ + { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ +- { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ ++ { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */ + { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ + { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ + { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ +@@ -328,29 +328,29 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ + { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ + { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ +- { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ ++ { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */ + { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ + { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ + { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ +- { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ ++ { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */ + { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ + { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ +- { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ ++ { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */ + { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ +- { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ ++ { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */ + { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ +- { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ ++ { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */ + { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ +- { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ +- { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ +- { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ +- { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ ++ { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */ ++ { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */ ++ { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */ + { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ + { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ + { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ +@@ -382,26 +382,26 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ + { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ + { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ +- { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ +- { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */ ++ { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */ + { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ +- { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ ++ { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */ + { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ +- { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ ++ { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */ + { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ +- { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ ++ { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */ + { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ +- { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ +- { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ +- { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ +- { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */ ++ { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */ ++ { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */ ++ { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */ + { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ +- { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ ++ { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */ + { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ + { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ +- { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ ++ { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */ + { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ + { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ + { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ +@@ -418,13 +418,13 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ + { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ + { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ +- { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ +- { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ +- { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ +- { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ +- { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ +- { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */ +- { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */ ++ { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */ ++ { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */ ++ { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */ ++ { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */ ++ { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ ++ { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ ++ { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ + + /* JMicron 360/1/3/5/6, match class to avoid IDE function */ + { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, +@@ -452,7 +452,7 @@ static const struct pci_device_id ahci_pci_tbl[] = { + { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ + { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ + { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ +- { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */ ++ { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */ + /* AMD is using RAID class only for ahci controllers */ + { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, +-- +2.40.1 + diff --git a/queue-5.15/ata-libata-rename-link-flag-ata_lflag_no_db_delay.patch b/queue-5.15/ata-libata-rename-link-flag-ata_lflag_no_db_delay.patch new file mode 100644 index 00000000000..7521b464a16 --- /dev/null +++ b/queue-5.15/ata-libata-rename-link-flag-ata_lflag_no_db_delay.patch @@ -0,0 +1,64 @@ +From 2a5729be2055fe9d1457e0fb175fbba27add60bd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 5 Jan 2022 16:36:16 +0100 +Subject: ata: libata: Rename link flag ATA_LFLAG_NO_DB_DELAY + +From: Paul Menzel + +[ Upstream commit b9ba367c513dbc165dd6c01266a59db4be2a3564 ] + +Rename the link flag ATA_LFLAG_NO_DB_DELAY to +ATA_LFLAG_NO_DEBOUNCE_DELAY. The new name is longer, but clearer. + +Signed-off-by: Paul Menzel +Signed-off-by: Damien Le Moal +Stable-dep-of: 2a2df98ec592 ("ata: ahci: Add Elkhart Lake AHCI controller") +Signed-off-by: Sasha Levin +--- + drivers/ata/ahci_brcm.c | 2 +- + drivers/ata/libata-sata.c | 2 +- + include/linux/libata.h | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c +index 6e9c5ade4c2ea..649815c196ed0 100644 +--- a/drivers/ata/ahci_brcm.c ++++ b/drivers/ata/ahci_brcm.c +@@ -333,7 +333,7 @@ static struct ata_port_operations ahci_brcm_platform_ops = { + + static const struct ata_port_info ahci_brcm_port_info = { + .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, +- .link_flags = ATA_LFLAG_NO_DB_DELAY, ++ .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_brcm_platform_ops, +diff --git a/drivers/ata/libata-sata.c b/drivers/ata/libata-sata.c +index cb9395a3ad8e8..04bdd53abf20b 100644 +--- a/drivers/ata/libata-sata.c ++++ b/drivers/ata/libata-sata.c +@@ -317,7 +317,7 @@ int sata_link_resume(struct ata_link *link, const unsigned long *params, + * immediately after resuming. Delay 200ms before + * debouncing. + */ +- if (!(link->flags & ATA_LFLAG_NO_DB_DELAY)) ++ if (!(link->flags & ATA_LFLAG_NO_DEBOUNCE_DELAY)) + ata_msleep(link->ap, 200); + + /* is SControl restored correctly? */ +diff --git a/include/linux/libata.h b/include/linux/libata.h +index fa568d35bcbfa..7508c68756e95 100644 +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -191,7 +191,7 @@ enum { + ATA_LFLAG_NO_LPM = (1 << 8), /* disable LPM on this link */ + ATA_LFLAG_RST_ONCE = (1 << 9), /* limit recovery to one reset */ + ATA_LFLAG_CHANGED = (1 << 10), /* LPM state changed on this link */ +- ATA_LFLAG_NO_DB_DELAY = (1 << 11), /* no debounce delay on link resume */ ++ ATA_LFLAG_NO_DEBOUNCE_DELAY = (1 << 11), /* no debounce delay on link resume */ + + /* struct ata_port flags */ + ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */ +-- +2.40.1 + diff --git a/queue-5.15/bpf-fix-issue-in-verifying-allow_ptr_leaks.patch b/queue-5.15/bpf-fix-issue-in-verifying-allow_ptr_leaks.patch new file mode 100644 index 00000000000..91edf8df1c4 --- /dev/null +++ b/queue-5.15/bpf-fix-issue-in-verifying-allow_ptr_leaks.patch @@ -0,0 +1,95 @@ +From 686d9331b840b73d7bb5dba2bd6ff27b65390309 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 23 Aug 2023 02:07:02 +0000 +Subject: bpf: Fix issue in verifying allow_ptr_leaks + +From: Yafang Shao + +[ Upstream commit d75e30dddf73449bc2d10bb8e2f1a2c446bc67a2 ] + +After we converted the capabilities of our networking-bpf program from +cap_sys_admin to cap_net_admin+cap_bpf, our networking-bpf program +failed to start. Because it failed the bpf verifier, and the error log +is "R3 pointer comparison prohibited". + +A simple reproducer as follows, + +SEC("cls-ingress") +int ingress(struct __sk_buff *skb) +{ + struct iphdr *iph = (void *)(long)skb->data + sizeof(struct ethhdr); + + if ((long)(iph + 1) > (long)skb->data_end) + return TC_ACT_STOLEN; + return TC_ACT_OK; +} + +Per discussion with Yonghong and Alexei [1], comparison of two packet +pointers is not a pointer leak. This patch fixes it. + +Our local kernel is 6.1.y and we expect this fix to be backported to +6.1.y, so stable is CCed. + +[1]. https://lore.kernel.org/bpf/CAADnVQ+Nmspr7Si+pxWn8zkE7hX-7s93ugwC+94aXSy4uQ9vBg@mail.gmail.com/ + +Suggested-by: Yonghong Song +Suggested-by: Alexei Starovoitov +Signed-off-by: Yafang Shao +Acked-by: Eduard Zingerman +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20230823020703.3790-2-laoar.shao@gmail.com +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index ecf4332ff312f..41327deb8cbb0 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -9193,6 +9193,12 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, + return -EINVAL; + } + ++ /* check src2 operand */ ++ err = check_reg_arg(env, insn->dst_reg, SRC_OP); ++ if (err) ++ return err; ++ ++ dst_reg = ®s[insn->dst_reg]; + if (BPF_SRC(insn->code) == BPF_X) { + if (insn->imm != 0) { + verbose(env, "BPF_JMP/JMP32 uses reserved fields\n"); +@@ -9204,12 +9210,13 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, + if (err) + return err; + +- if (is_pointer_value(env, insn->src_reg)) { ++ src_reg = ®s[insn->src_reg]; ++ if (!(reg_is_pkt_pointer_any(dst_reg) && reg_is_pkt_pointer_any(src_reg)) && ++ is_pointer_value(env, insn->src_reg)) { + verbose(env, "R%d pointer comparison prohibited\n", + insn->src_reg); + return -EACCES; + } +- src_reg = ®s[insn->src_reg]; + } else { + if (insn->src_reg != BPF_REG_0) { + verbose(env, "BPF_JMP/JMP32 uses reserved fields\n"); +@@ -9217,12 +9224,6 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, + } + } + +- /* check src2 operand */ +- err = check_reg_arg(env, insn->dst_reg, SRC_OP); +- if (err) +- return err; +- +- dst_reg = ®s[insn->dst_reg]; + is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; + + if (BPF_SRC(insn->code) == BPF_K) { +-- +2.40.1 + diff --git a/queue-5.15/input-i8042-add-quirk-for-tuxedo-gemini-17-gen1-clev.patch b/queue-5.15/input-i8042-add-quirk-for-tuxedo-gemini-17-gen1-clev.patch new file mode 100644 index 00000000000..5f357b3d83e --- /dev/null +++ b/queue-5.15/input-i8042-add-quirk-for-tuxedo-gemini-17-gen1-clev.patch @@ -0,0 +1,50 @@ +From beb105e718a1101c0d73431c51b5c552ac1e8117 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 12 Jul 2023 11:56:51 -0700 +Subject: Input: i8042 - add quirk for TUXEDO Gemini 17 Gen1/Clevo PD70PN + +From: Werner Sembach + +[ Upstream commit eb09074bdb05ffd6bfe77f8b4a41b76ef78c997b ] + +The touchpad of this device is both connected via PS/2 and i2c. This causes +strange behavior when both driver fight for control. The easy fix is to +prevent the PS/2 driver from accessing the mouse port as the full feature +set of the touchpad is only supported in the i2c interface anyway. + +The strange behavior in this case is, that when an external screen is +connected and the notebook is closed, the pointer on the external screen is +moving to the lower right corner. When the notebook is opened again, this +movement stops, but the touchpad clicks are unresponsive afterwards until +reboot. + +Signed-off-by: Werner Sembach +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20230607173331.851192-1-wse@tuxedocomputers.com +Signed-off-by: Dmitry Torokhov +Signed-off-by: Sasha Levin +--- + drivers/input/serio/i8042-acpipnpio.h | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/input/serio/i8042-acpipnpio.h b/drivers/input/serio/i8042-acpipnpio.h +index ce8ec35e8e06d..a0d8528685fe3 100644 +--- a/drivers/input/serio/i8042-acpipnpio.h ++++ b/drivers/input/serio/i8042-acpipnpio.h +@@ -1244,6 +1244,13 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = { + .driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS | + SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP) + }, ++ /* See comment on TUXEDO InfinityBook S17 Gen6 / Clevo NS70MU above */ ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "PD5x_7xPNP_PNR_PNN_PNT"), ++ }, ++ .driver_data = (void *)(SERIO_QUIRK_NOAUX) ++ }, + { + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "X170SM"), +-- +2.40.1 + diff --git a/queue-5.15/input-i8042-rename-i8042-x86ia64io.h-to-i8042-acpipn.patch b/queue-5.15/input-i8042-rename-i8042-x86ia64io.h-to-i8042-acpipn.patch new file mode 100644 index 00000000000..558ca9a2fcc --- /dev/null +++ b/queue-5.15/input-i8042-rename-i8042-x86ia64io.h-to-i8042-acpipn.patch @@ -0,0 +1,64 @@ +From c005fa233294286a62357c90f29d23065a797725 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 1 Oct 2022 14:28:34 -0700 +Subject: Input: i8042 - rename i8042-x86ia64io.h to i8042-acpipnpio.h + +From: Huacai Chen + +[ Upstream commit 8761b9b580d53162cca7868385069c0d4354c9e0 ] + +Now i8042-x86ia64io.h is shared by X86 and IA64, but it can be shared +by more platforms (such as LoongArch) with ACPI firmware on which PNP +typed keyboard and mouse is configured in DSDT. So rename it to i8042- +acpipnpio.h. + +Signed-off-by: Huacai Chen +Reviewed-by: Mattijs Korpershoek +Link: https://lore.kernel.org/r/20220917064020.1639709-1-chenhuacai@loongson.cn +Signed-off-by: Dmitry Torokhov +Stable-dep-of: eb09074bdb05 ("Input: i8042 - add quirk for TUXEDO Gemini 17 Gen1/Clevo PD70PN") +Signed-off-by: Sasha Levin +--- + .../input/serio/{i8042-x86ia64io.h => i8042-acpipnpio.h} | 6 +++--- + drivers/input/serio/i8042.h | 2 +- + 2 files changed, 4 insertions(+), 4 deletions(-) + rename drivers/input/serio/{i8042-x86ia64io.h => i8042-acpipnpio.h} (99%) + +diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-acpipnpio.h +similarity index 99% +rename from drivers/input/serio/i8042-x86ia64io.h +rename to drivers/input/serio/i8042-acpipnpio.h +index 339e765bcf5ae..ce8ec35e8e06d 100644 +--- a/drivers/input/serio/i8042-x86ia64io.h ++++ b/drivers/input/serio/i8042-acpipnpio.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ +-#ifndef _I8042_X86IA64IO_H +-#define _I8042_X86IA64IO_H ++#ifndef _I8042_ACPIPNPIO_H ++#define _I8042_ACPIPNPIO_H + + + #ifdef CONFIG_X86 +@@ -1647,4 +1647,4 @@ static inline void i8042_platform_exit(void) + i8042_pnp_exit(); + } + +-#endif /* _I8042_X86IA64IO_H */ ++#endif /* _I8042_ACPIPNPIO_H */ +diff --git a/drivers/input/serio/i8042.h b/drivers/input/serio/i8042.h +index 55381783dc82d..bf2592fa9a783 100644 +--- a/drivers/input/serio/i8042.h ++++ b/drivers/input/serio/i8042.h +@@ -20,7 +20,7 @@ + #elif defined(CONFIG_SPARC) + #include "i8042-sparcio.h" + #elif defined(CONFIG_X86) || defined(CONFIG_IA64) +-#include "i8042-x86ia64io.h" ++#include "i8042-acpipnpio.h" + #else + #include "i8042-io.h" + #endif +-- +2.40.1 + diff --git a/queue-5.15/netfilter-exthdr-add-support-for-tcp-option-removal.patch b/queue-5.15/netfilter-exthdr-add-support-for-tcp-option-removal.patch new file mode 100644 index 00000000000..60d6a9b2ea3 --- /dev/null +++ b/queue-5.15/netfilter-exthdr-add-support-for-tcp-option-removal.patch @@ -0,0 +1,171 @@ +From 19bb554e03cdd1d93f56a189578ad13a005b5150 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 28 Jan 2022 13:00:36 +0100 +Subject: netfilter: exthdr: add support for tcp option removal + +From: Florian Westphal + +[ Upstream commit 7890cbea66e78a3a6037b2a12827118d7243270b ] + +This allows to replace a tcp option with nop padding to selectively disable +a particular tcp option. + +Optstrip mode is chosen when userspace passes the exthdr expression with +neither a source nor a destination register attribute. + +This is identical to xtables TCPOPTSTRIP extension. +The only difference is that TCPOPTSTRIP allows to pass in a bitmap +of options to remove rather than a single number. + +Unlike TCPOPTSTRIP this expression can be used multiple times +in the same rule to get the same effect. + +We could add a new nested attribute later on in case there is a +use case for single-expression-multi-remove. + +Signed-off-by: Florian Westphal +Signed-off-by: Pablo Neira Ayuso +Stable-dep-of: 28427f368f0e ("netfilter: nft_exthdr: Fix non-linear header modification") +Signed-off-by: Sasha Levin +--- + net/netfilter/nft_exthdr.c | 96 +++++++++++++++++++++++++++++++++++++- + 1 file changed, 95 insertions(+), 1 deletion(-) + +diff --git a/net/netfilter/nft_exthdr.c b/net/netfilter/nft_exthdr.c +index 3609680831a14..58f205531b961 100644 +--- a/net/netfilter/nft_exthdr.c ++++ b/net/netfilter/nft_exthdr.c +@@ -315,6 +315,63 @@ static void nft_exthdr_tcp_set_eval(const struct nft_expr *expr, + regs->verdict.code = NFT_BREAK; + } + ++static void nft_exthdr_tcp_strip_eval(const struct nft_expr *expr, ++ struct nft_regs *regs, ++ const struct nft_pktinfo *pkt) ++{ ++ u8 buff[sizeof(struct tcphdr) + MAX_TCP_OPTION_SPACE]; ++ struct nft_exthdr *priv = nft_expr_priv(expr); ++ unsigned int i, tcphdr_len, optl; ++ struct tcphdr *tcph; ++ u8 *opt; ++ ++ tcph = nft_tcp_header_pointer(pkt, sizeof(buff), buff, &tcphdr_len); ++ if (!tcph) ++ goto err; ++ ++ if (skb_ensure_writable(pkt->skb, nft_thoff(pkt) + tcphdr_len)) ++ goto drop; ++ ++ opt = (u8 *)nft_tcp_header_pointer(pkt, sizeof(buff), buff, &tcphdr_len); ++ if (!opt) ++ goto err; ++ for (i = sizeof(*tcph); i < tcphdr_len - 1; i += optl) { ++ unsigned int j; ++ ++ optl = optlen(opt, i); ++ if (priv->type != opt[i]) ++ continue; ++ ++ if (i + optl > tcphdr_len) ++ goto drop; ++ ++ for (j = 0; j < optl; ++j) { ++ u16 n = TCPOPT_NOP; ++ u16 o = opt[i+j]; ++ ++ if ((i + j) % 2 == 0) { ++ o <<= 8; ++ n <<= 8; ++ } ++ inet_proto_csum_replace2(&tcph->check, pkt->skb, htons(o), ++ htons(n), false); ++ } ++ memset(opt + i, TCPOPT_NOP, optl); ++ return; ++ } ++ ++ /* option not found, continue. This allows to do multiple ++ * option removals per rule. ++ */ ++ return; ++err: ++ regs->verdict.code = NFT_BREAK; ++ return; ++drop: ++ /* can't remove, no choice but to drop */ ++ regs->verdict.code = NF_DROP; ++} ++ + static void nft_exthdr_sctp_eval(const struct nft_expr *expr, + struct nft_regs *regs, + const struct nft_pktinfo *pkt) +@@ -463,6 +520,28 @@ static int nft_exthdr_tcp_set_init(const struct nft_ctx *ctx, + priv->len); + } + ++static int nft_exthdr_tcp_strip_init(const struct nft_ctx *ctx, ++ const struct nft_expr *expr, ++ const struct nlattr * const tb[]) ++{ ++ struct nft_exthdr *priv = nft_expr_priv(expr); ++ ++ if (tb[NFTA_EXTHDR_SREG] || ++ tb[NFTA_EXTHDR_DREG] || ++ tb[NFTA_EXTHDR_FLAGS] || ++ tb[NFTA_EXTHDR_OFFSET] || ++ tb[NFTA_EXTHDR_LEN]) ++ return -EINVAL; ++ ++ if (!tb[NFTA_EXTHDR_TYPE]) ++ return -EINVAL; ++ ++ priv->type = nla_get_u8(tb[NFTA_EXTHDR_TYPE]); ++ priv->op = NFT_EXTHDR_OP_TCPOPT; ++ ++ return 0; ++} ++ + static int nft_exthdr_ipv4_init(const struct nft_ctx *ctx, + const struct nft_expr *expr, + const struct nlattr * const tb[]) +@@ -523,6 +602,13 @@ static int nft_exthdr_dump_set(struct sk_buff *skb, const struct nft_expr *expr) + return nft_exthdr_dump_common(skb, priv); + } + ++static int nft_exthdr_dump_strip(struct sk_buff *skb, const struct nft_expr *expr) ++{ ++ const struct nft_exthdr *priv = nft_expr_priv(expr); ++ ++ return nft_exthdr_dump_common(skb, priv); ++} ++ + static const struct nft_expr_ops nft_exthdr_ipv6_ops = { + .type = &nft_exthdr_type, + .size = NFT_EXPR_SIZE(sizeof(struct nft_exthdr)), +@@ -555,6 +641,14 @@ static const struct nft_expr_ops nft_exthdr_tcp_set_ops = { + .dump = nft_exthdr_dump_set, + }; + ++static const struct nft_expr_ops nft_exthdr_tcp_strip_ops = { ++ .type = &nft_exthdr_type, ++ .size = NFT_EXPR_SIZE(sizeof(struct nft_exthdr)), ++ .eval = nft_exthdr_tcp_strip_eval, ++ .init = nft_exthdr_tcp_strip_init, ++ .dump = nft_exthdr_dump_strip, ++}; ++ + static const struct nft_expr_ops nft_exthdr_sctp_ops = { + .type = &nft_exthdr_type, + .size = NFT_EXPR_SIZE(sizeof(struct nft_exthdr)), +@@ -582,7 +676,7 @@ nft_exthdr_select_ops(const struct nft_ctx *ctx, + return &nft_exthdr_tcp_set_ops; + if (tb[NFTA_EXTHDR_DREG]) + return &nft_exthdr_tcp_ops; +- break; ++ return &nft_exthdr_tcp_strip_ops; + case NFT_EXTHDR_OP_IPV6: + if (tb[NFTA_EXTHDR_DREG]) + return &nft_exthdr_ipv6_ops; +-- +2.40.1 + diff --git a/queue-5.15/netfilter-nft_exthdr-fix-non-linear-header-modificat.patch b/queue-5.15/netfilter-nft_exthdr-fix-non-linear-header-modificat.patch new file mode 100644 index 00000000000..fba05e72089 --- /dev/null +++ b/queue-5.15/netfilter-nft_exthdr-fix-non-linear-header-modificat.patch @@ -0,0 +1,71 @@ +From ecbcc2849e795089457f8e60c38d63197f111ca7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 25 Aug 2023 13:33:27 +0800 +Subject: netfilter: nft_exthdr: Fix non-linear header modification + +From: Xiao Liang + +[ Upstream commit 28427f368f0e08d504ed06e74bc7cc79d6d06511 ] + +Fix skb_ensure_writable() size. Don't use nft_tcp_header_pointer() to +make it explicit that pointers point to the packet (not local buffer). + +Fixes: 99d1712bc41c ("netfilter: exthdr: tcp option set support") +Fixes: 7890cbea66e7 ("netfilter: exthdr: add support for tcp option removal") +Cc: stable@vger.kernel.org +Signed-off-by: Xiao Liang +Signed-off-by: Pablo Neira Ayuso +Signed-off-by: Sasha Levin +--- + net/netfilter/nft_exthdr.c | 20 ++++++++------------ + 1 file changed, 8 insertions(+), 12 deletions(-) + +diff --git a/net/netfilter/nft_exthdr.c b/net/netfilter/nft_exthdr.c +index 58f205531b961..daee46cf62abb 100644 +--- a/net/netfilter/nft_exthdr.c ++++ b/net/netfilter/nft_exthdr.c +@@ -245,7 +245,12 @@ static void nft_exthdr_tcp_set_eval(const struct nft_expr *expr, + if (!tcph) + goto err; + ++ if (skb_ensure_writable(pkt->skb, nft_thoff(pkt) + tcphdr_len)) ++ goto err; ++ ++ tcph = (struct tcphdr *)(pkt->skb->data + nft_thoff(pkt)); + opt = (u8 *)tcph; ++ + for (i = sizeof(*tcph); i < tcphdr_len - 1; i += optl) { + union { + __be16 v16; +@@ -260,15 +265,6 @@ static void nft_exthdr_tcp_set_eval(const struct nft_expr *expr, + if (i + optl > tcphdr_len || priv->len + priv->offset > optl) + goto err; + +- if (skb_ensure_writable(pkt->skb, +- nft_thoff(pkt) + i + priv->len)) +- goto err; +- +- tcph = nft_tcp_header_pointer(pkt, sizeof(buff), buff, +- &tcphdr_len); +- if (!tcph) +- goto err; +- + offset = i + priv->offset; + + switch (priv->len) { +@@ -332,9 +328,9 @@ static void nft_exthdr_tcp_strip_eval(const struct nft_expr *expr, + if (skb_ensure_writable(pkt->skb, nft_thoff(pkt) + tcphdr_len)) + goto drop; + +- opt = (u8 *)nft_tcp_header_pointer(pkt, sizeof(buff), buff, &tcphdr_len); +- if (!opt) +- goto err; ++ tcph = (struct tcphdr *)(pkt->skb->data + nft_thoff(pkt)); ++ opt = (u8 *)tcph; ++ + for (i = sizeof(*tcph); i < tcphdr_len - 1; i += optl) { + unsigned int j; + +-- +2.40.1 + diff --git a/queue-5.15/perf-build-update-build-rule-for-generated-files.patch b/queue-5.15/perf-build-update-build-rule-for-generated-files.patch new file mode 100644 index 00000000000..8f81491dfce --- /dev/null +++ b/queue-5.15/perf-build-update-build-rule-for-generated-files.patch @@ -0,0 +1,87 @@ +From 908dd1d20f942e3904a9ff00259d8b2c0084e642 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 27 Jul 2023 19:24:46 -0700 +Subject: perf build: Update build rule for generated files + +From: Namhyung Kim + +[ Upstream commit 7822a8913f4c51c7d1aff793b525d60c3384fb5b ] + +The bison and flex generate C files from the source (.y and .l) +files. When O= option is used, they are saved in a separate directory +but the default build rule assumes the .C files are in the source +directory. So it might read invalid file if there are generated files +from an old version. The same is true for the pmu-events files. + +For example, the following command would cause a build failure: + + $ git checkout v6.3 + $ make -C tools/perf # build in the same directory + + $ git checkout v6.5-rc2 + $ mkdir build # create a build directory + $ make -C tools/perf O=build # build in a different directory but it + # refers files in the source directory + +Let's update the build rule to specify those cases explicitly to depend +on the files in the output directory. + +Note that it's not a complete fix and it needs the next patch for the +include path too. + +Fixes: 80eeb67fe577aa76 ("perf jevents: Program to convert JSON file") +Signed-off-by: Namhyung Kim +Cc: Adrian Hunter +Cc: Andi Kleen +Cc: Anup Sharma +Cc: Ian Rogers +Cc: Ingo Molnar +Cc: Jiri Olsa +Cc: Peter Zijlstra +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20230728022447.1323563-1-namhyung@kernel.org +Signed-off-by: Arnaldo Carvalho de Melo +Signed-off-by: Sasha Levin +--- + tools/build/Makefile.build | 10 ++++++++++ + tools/perf/pmu-events/Build | 6 ++++++ + 2 files changed, 16 insertions(+) + +diff --git a/tools/build/Makefile.build b/tools/build/Makefile.build +index 715092fc6a239..0f0aba16bdee7 100644 +--- a/tools/build/Makefile.build ++++ b/tools/build/Makefile.build +@@ -116,6 +116,16 @@ $(OUTPUT)%.s: %.c FORCE + $(call rule_mkdir) + $(call if_changed_dep,cc_s_c) + ++# bison and flex files are generated in the OUTPUT directory ++# so it needs a separate rule to depend on them properly ++$(OUTPUT)%-bison.o: $(OUTPUT)%-bison.c FORCE ++ $(call rule_mkdir) ++ $(call if_changed_dep,$(host)cc_o_c) ++ ++$(OUTPUT)%-flex.o: $(OUTPUT)%-flex.c FORCE ++ $(call rule_mkdir) ++ $(call if_changed_dep,$(host)cc_o_c) ++ + # Gather build data: + # obj-y - list of build objects + # subdir-y - list of directories to nest +diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build +index 5ec5ce8c31bab..ea8c41f9c7398 100644 +--- a/tools/perf/pmu-events/Build ++++ b/tools/perf/pmu-events/Build +@@ -25,3 +25,9 @@ $(OUTPUT)pmu-events/pmu-events.c: $(JSON) $(JSON_TEST) $(JEVENTS_PY) + $(call rule_mkdir) + $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(SRCARCH) pmu-events/arch $@ + endif ++ ++# pmu-events.c file is generated in the OUTPUT directory so it needs a ++# separate rule to depend on it properly ++$(OUTPUT)pmu-events/pmu-events.o: $(PMU_EVENTS_C) ++ $(call rule_mkdir) ++ $(call if_changed_dep,cc_o_c) +-- +2.40.1 + diff --git a/queue-5.15/perf-jevents-switch-build-to-use-jevents.py.patch b/queue-5.15/perf-jevents-switch-build-to-use-jevents.py.patch new file mode 100644 index 00000000000..95fe8fe1af5 --- /dev/null +++ b/queue-5.15/perf-jevents-switch-build-to-use-jevents.py.patch @@ -0,0 +1,295 @@ +From aa5dcc880d8ea6677467f22dceabff5e45e1d2a2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Jun 2022 11:25:04 -0700 +Subject: perf jevents: Switch build to use jevents.py + +From: Ian Rogers + +[ Upstream commit 00facc760903be6675870c2749e2cd72140e396e ] + +Generate pmu-events.c using jevents.py rather than the binary built from +jevents.c. + +Add a new config variable NO_JEVENTS that is set when there is no +architecture json or an appropriate python interpreter isn't present. + +When NO_JEVENTS is defined the file pmu-events/empty-pmu-events.c is +copied and used as the pmu-events.c file. + +Signed-off-by: Ian Rogers +Tested-by: John Garry +Cc: Alexander Shishkin +Cc: Ananth Narayan +Cc: Andi Kleen +Cc: Andrew Kilroy +Cc: Caleb Biggers +Cc: Felix Fietkau +Cc: Ian Rogers +Cc: Ingo Molnar +Cc: James Clark +Cc: Jiri Olsa +Cc: Kajol Jain +Cc: Kan Liang +Cc: Kshipra Bopardikar +Cc: Like Xu +Cc: Mark Rutland +Cc: Mathieu Poirier +Cc: Namhyung Kim +Cc: Nick Forrington +Cc: Paul Clarke +Cc: Perry Taylor +Cc: Peter Zijlstra +Cc: Qi Liu +Cc: Ravi Bangoria +Cc: Sandipan Das +Cc: Santosh Shukla +Cc: Stephane Eranian +Cc: Will Deacon +Cc: Xing Zhengjun +Link: https://lore.kernel.org/r/20220629182505.406269-4-irogers@google.com +Signed-off-by: Arnaldo Carvalho de Melo +Stable-dep-of: 7822a8913f4c ("perf build: Update build rule for generated files") +Signed-off-by: Sasha Levin +--- + tools/perf/Makefile.config | 19 +++ + tools/perf/Makefile.perf | 1 + + tools/perf/pmu-events/Build | 13 +- + tools/perf/pmu-events/empty-pmu-events.c | 158 +++++++++++++++++++++++ + 4 files changed, 189 insertions(+), 2 deletions(-) + create mode 100644 tools/perf/pmu-events/empty-pmu-events.c + +diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config +index 973c0d5ed8d8b..e1077c4d30fff 100644 +--- a/tools/perf/Makefile.config ++++ b/tools/perf/Makefile.config +@@ -857,6 +857,25 @@ else + endif + endif + ++ifneq ($(NO_JEVENTS),1) ++ ifeq ($(wildcard pmu-events/arch/$(SRCARCH)/mapfile.csv),) ++ NO_JEVENTS := 1 ++ endif ++endif ++ifneq ($(NO_JEVENTS),1) ++ NO_JEVENTS := 0 ++ ifndef PYTHON ++ $(warning No python interpreter disabling jevent generation) ++ NO_JEVENTS := 1 ++ else ++ # jevents.py uses f-strings present in Python 3.6 released in Dec. 2016. ++ JEVENTS_PYTHON_GOOD := $(shell $(PYTHON) -c 'import sys;print("1" if(sys.version_info.major >= 3 and sys.version_info.minor >= 6) else "0")' 2> /dev/null) ++ ifneq ($(JEVENTS_PYTHON_GOOD), 1) ++ $(warning Python interpreter too old (older than 3.6) disabling jevent generation) ++ NO_JEVENTS := 1 ++ endif ++ endif ++endif + + ifndef NO_LIBBFD + ifeq ($(feature-libbfd), 1) +diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf +index b856afa6eb52e..b82f2d89d74c4 100644 +--- a/tools/perf/Makefile.perf ++++ b/tools/perf/Makefile.perf +@@ -649,6 +649,7 @@ JEVENTS := $(OUTPUT)pmu-events/jevents + JEVENTS_IN := $(OUTPUT)pmu-events/jevents-in.o + + PMU_EVENTS_IN := $(OUTPUT)pmu-events/pmu-events-in.o ++export NO_JEVENTS + + export JEVENTS + +diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build +index a055dee6a46af..5ec5ce8c31bab 100644 +--- a/tools/perf/pmu-events/Build ++++ b/tools/perf/pmu-events/Build +@@ -9,10 +9,19 @@ JSON = $(shell [ -d $(JDIR) ] && \ + JDIR_TEST = pmu-events/arch/test + JSON_TEST = $(shell [ -d $(JDIR_TEST) ] && \ + find $(JDIR_TEST) -name '*.json') ++JEVENTS_PY = pmu-events/jevents.py + + # + # Locate/process JSON files in pmu-events/arch/ + # directory and create tables in pmu-events.c. + # +-$(OUTPUT)pmu-events/pmu-events.c: $(JSON) $(JSON_TEST) $(JEVENTS) +- $(Q)$(call echo-cmd,gen)$(JEVENTS) $(SRCARCH) pmu-events/arch $(OUTPUT)pmu-events/pmu-events.c $(V) ++ ++ifeq ($(NO_JEVENTS),1) ++$(OUTPUT)pmu-events/pmu-events.c: pmu-events/empty-pmu-events.c ++ $(call rule_mkdir) ++ $(Q)$(call echo-cmd,gen)cp $< $@ ++else ++$(OUTPUT)pmu-events/pmu-events.c: $(JSON) $(JSON_TEST) $(JEVENTS_PY) ++ $(call rule_mkdir) ++ $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(SRCARCH) pmu-events/arch $@ ++endif +diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c +new file mode 100644 +index 0000000000000..77e655c6f1162 +--- /dev/null ++++ b/tools/perf/pmu-events/empty-pmu-events.c +@@ -0,0 +1,158 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * An empty pmu-events.c file used when there is no architecture json files in ++ * arch or when the jevents.py script cannot be run. ++ * ++ * The test cpu/soc is provided for testing. ++ */ ++#include "pmu-events/pmu-events.h" ++ ++static const struct pmu_event pme_test_soc_cpu[] = { ++ { ++ .name = "l3_cache_rd", ++ .event = "event=0x40", ++ .desc = "L3 cache access, read", ++ .topic = "cache", ++ .long_desc = "Attributable Level 3 cache access, read", ++ }, ++ { ++ .name = "segment_reg_loads.any", ++ .event = "event=0x6,period=200000,umask=0x80", ++ .desc = "Number of segment register loads", ++ .topic = "other", ++ }, ++ { ++ .name = "dispatch_blocked.any", ++ .event = "event=0x9,period=200000,umask=0x20", ++ .desc = "Memory cluster signals to block micro-op dispatch for any reason", ++ .topic = "other", ++ }, ++ { ++ .name = "eist_trans", ++ .event = "event=0x3a,period=200000,umask=0x0", ++ .desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions", ++ .topic = "other", ++ }, ++ { ++ .name = "uncore_hisi_ddrc.flux_wcmd", ++ .event = "event=0x2", ++ .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ", ++ .topic = "uncore", ++ .long_desc = "DDRC write commands", ++ .pmu = "hisi_sccl,ddrc", ++ }, ++ { ++ .name = "unc_cbo_xsnp_response.miss_eviction", ++ .event = "event=0x22,umask=0x81", ++ .desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox ", ++ .topic = "uncore", ++ .long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core", ++ .pmu = "uncore_cbox", ++ }, ++ { ++ .name = "event-hyphen", ++ .event = "event=0xe0,umask=0x00", ++ .desc = "UNC_CBO_HYPHEN. Unit: uncore_cbox ", ++ .topic = "uncore", ++ .long_desc = "UNC_CBO_HYPHEN", ++ .pmu = "uncore_cbox", ++ }, ++ { ++ .name = "event-two-hyph", ++ .event = "event=0xc0,umask=0x00", ++ .desc = "UNC_CBO_TWO_HYPH. Unit: uncore_cbox ", ++ .topic = "uncore", ++ .long_desc = "UNC_CBO_TWO_HYPH", ++ .pmu = "uncore_cbox", ++ }, ++ { ++ .name = "uncore_hisi_l3c.rd_hit_cpipe", ++ .event = "event=0x7", ++ .desc = "Total read hits. Unit: hisi_sccl,l3c ", ++ .topic = "uncore", ++ .long_desc = "Total read hits", ++ .pmu = "hisi_sccl,l3c", ++ }, ++ { ++ .name = "uncore_imc_free_running.cache_miss", ++ .event = "event=0x12", ++ .desc = "Total cache misses. Unit: uncore_imc_free_running ", ++ .topic = "uncore", ++ .long_desc = "Total cache misses", ++ .pmu = "uncore_imc_free_running", ++ }, ++ { ++ .name = "uncore_imc.cache_hits", ++ .event = "event=0x34", ++ .desc = "Total cache hits. Unit: uncore_imc ", ++ .topic = "uncore", ++ .long_desc = "Total cache hits", ++ .pmu = "uncore_imc", ++ }, ++ { ++ .name = "bp_l1_btb_correct", ++ .event = "event=0x8a", ++ .desc = "L1 BTB Correction", ++ .topic = "branch", ++ }, ++ { ++ .name = "bp_l2_btb_correct", ++ .event = "event=0x8b", ++ .desc = "L2 BTB Correction", ++ .topic = "branch", ++ }, ++ { ++ .name = 0, ++ .event = 0, ++ .desc = 0, ++ }, ++}; ++ ++const struct pmu_events_map pmu_events_map[] = { ++ { ++ .cpuid = "testcpu", ++ .version = "v1", ++ .type = "core", ++ .table = pme_test_soc_cpu, ++ }, ++ { ++ .cpuid = 0, ++ .version = 0, ++ .type = 0, ++ .table = 0, ++ }, ++}; ++ ++static const struct pmu_event pme_test_soc_sys[] = { ++ { ++ .name = "sys_ddr_pmu.write_cycles", ++ .event = "event=0x2b", ++ .desc = "ddr write-cycles event. Unit: uncore_sys_ddr_pmu ", ++ .compat = "v8", ++ .topic = "uncore", ++ .pmu = "uncore_sys_ddr_pmu", ++ }, ++ { ++ .name = "sys_ccn_pmu.read_cycles", ++ .event = "config=0x2c", ++ .desc = "ccn read-cycles event. Unit: uncore_sys_ccn_pmu ", ++ .compat = "0x01", ++ .topic = "uncore", ++ .pmu = "uncore_sys_ccn_pmu", ++ }, ++ { ++ .name = 0, ++ .event = 0, ++ .desc = 0, ++ }, ++}; ++ ++const struct pmu_sys_events pmu_sys_event_tables[] = { ++ { ++ .table = pme_test_soc_sys, ++ .name = "pme_test_soc_sys", ++ }, ++ { ++ .table = 0 ++ }, ++}; +-- +2.40.1 + diff --git a/queue-5.15/scsi-qla2xxx-select-qpair-depending-on-which-cpu-pos.patch b/queue-5.15/scsi-qla2xxx-select-qpair-depending-on-which-cpu-pos.patch new file mode 100644 index 00000000000..e2f05d80c6c --- /dev/null +++ b/queue-5.15/scsi-qla2xxx-select-qpair-depending-on-which-cpu-pos.patch @@ -0,0 +1,208 @@ +From 08520f436caae3757378c630a64d13cdca879d65 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Dec 2022 20:39:32 -0800 +Subject: scsi: qla2xxx: Select qpair depending on which CPU post_cmd() gets + called + +From: Shreyas Deodhar + +[ Upstream commit 1d201c81d4cc6840735bbcc99e6031503e5cf3b8 ] + +In current I/O path, Tx and Rx may not be processed on same CPU. This may +lead to thrashing and optimum performance may not be achieved. + +Pick qpair such that Tx and Rx are processed on same CPU. + +Signed-off-by: Shreyas Deodhar +Signed-off-by: Nilesh Javali +Signed-off-by: Martin K. Petersen +Stable-dep-of: 59f10a05b5c7 ("scsi: qla2xxx: Use raw_smp_processor_id() instead of smp_processor_id()") +Signed-off-by: Sasha Levin +--- + drivers/scsi/qla2xxx/qla_def.h | 2 ++ + drivers/scsi/qla2xxx/qla_init.c | 2 -- + drivers/scsi/qla2xxx/qla_inline.h | 55 +++++++++++++++++++++++++++++++ + drivers/scsi/qla2xxx/qla_isr.c | 3 +- + drivers/scsi/qla2xxx/qla_nvme.c | 4 +++ + drivers/scsi/qla2xxx/qla_os.c | 6 ++++ + 6 files changed, 69 insertions(+), 3 deletions(-) + +diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h +index d70c2f4ba718e..723f9953ad701 100644 +--- a/drivers/scsi/qla2xxx/qla_def.h ++++ b/drivers/scsi/qla2xxx/qla_def.h +@@ -3461,6 +3461,7 @@ struct qla_msix_entry { + int have_irq; + int in_use; + uint32_t vector; ++ uint32_t vector_base0; + uint16_t entry; + char name[30]; + void *handle; +@@ -4119,6 +4120,7 @@ struct qla_hw_data { + struct req_que **req_q_map; + struct rsp_que **rsp_q_map; + struct qla_qpair **queue_pair_map; ++ struct qla_qpair **qp_cpu_map; + unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; + unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; + unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) +diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c +index 1a2ceef92bf07..d259f6727cf74 100644 +--- a/drivers/scsi/qla2xxx/qla_init.c ++++ b/drivers/scsi/qla2xxx/qla_init.c +@@ -9779,8 +9779,6 @@ struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, + qpair->req = ha->req_q_map[req_id]; + qpair->rsp->req = qpair->req; + qpair->rsp->qpair = qpair; +- /* init qpair to this cpu. Will adjust at run time. */ +- qla_cpu_update(qpair, raw_smp_processor_id()); + + if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { + if (ha->fw_attributes & BIT_4) +diff --git a/drivers/scsi/qla2xxx/qla_inline.h b/drivers/scsi/qla2xxx/qla_inline.h +index a7b5d11146827..d5cf9db2a8ea3 100644 +--- a/drivers/scsi/qla2xxx/qla_inline.h ++++ b/drivers/scsi/qla2xxx/qla_inline.h +@@ -573,3 +573,58 @@ fcport_is_bigger(fc_port_t *fcport) + { + return !fcport_is_smaller(fcport); + } ++ ++static inline struct qla_qpair * ++qla_mapq_nvme_select_qpair(struct qla_hw_data *ha, struct qla_qpair *qpair) ++{ ++ int cpuid = smp_processor_id(); ++ ++ if (qpair->cpuid != cpuid && ++ ha->qp_cpu_map[cpuid]) { ++ qpair = ha->qp_cpu_map[cpuid]; ++ } ++ return qpair; ++} ++ ++static inline void ++qla_mapq_init_qp_cpu_map(struct qla_hw_data *ha, ++ struct qla_msix_entry *msix, ++ struct qla_qpair *qpair) ++{ ++ const struct cpumask *mask; ++ unsigned int cpu; ++ ++ if (!ha->qp_cpu_map) ++ return; ++ mask = pci_irq_get_affinity(ha->pdev, msix->vector_base0); ++ qpair->cpuid = cpumask_first(mask); ++ for_each_cpu(cpu, mask) { ++ ha->qp_cpu_map[cpu] = qpair; ++ } ++ msix->cpuid = qpair->cpuid; ++} ++ ++static inline void ++qla_mapq_free_qp_cpu_map(struct qla_hw_data *ha) ++{ ++ if (ha->qp_cpu_map) { ++ kfree(ha->qp_cpu_map); ++ ha->qp_cpu_map = NULL; ++ } ++} ++ ++static inline int qla_mapq_alloc_qp_cpu_map(struct qla_hw_data *ha) ++{ ++ scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); ++ ++ if (!ha->qp_cpu_map) { ++ ha->qp_cpu_map = kcalloc(NR_CPUS, sizeof(struct qla_qpair *), ++ GFP_KERNEL); ++ if (!ha->qp_cpu_map) { ++ ql_log(ql_log_fatal, vha, 0x0180, ++ "Unable to allocate memory for qp_cpu_map ptrs.\n"); ++ return -1; ++ } ++ } ++ return 0; ++} +diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c +index 80c2dcf567b0c..a13732921b5c0 100644 +--- a/drivers/scsi/qla2xxx/qla_isr.c ++++ b/drivers/scsi/qla2xxx/qla_isr.c +@@ -3782,7 +3782,6 @@ void qla24xx_process_response_queue(struct scsi_qla_host *vha, + + if (rsp->qpair->cpuid != smp_processor_id() || !rsp->qpair->rcv_intr) { + rsp->qpair->rcv_intr = 1; +- qla_cpu_update(rsp->qpair, smp_processor_id()); + } + + #define __update_rsp_in(_update, _is_shadow_hba, _rsp, _rsp_in) \ +@@ -4396,6 +4395,7 @@ qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp) + for (i = 0; i < ha->msix_count; i++) { + qentry = &ha->msix_entries[i]; + qentry->vector = pci_irq_vector(ha->pdev, i); ++ qentry->vector_base0 = i; + qentry->entry = i; + qentry->have_irq = 0; + qentry->in_use = 0; +@@ -4623,5 +4623,6 @@ int qla25xx_request_irq(struct qla_hw_data *ha, struct qla_qpair *qpair, + } + msix->have_irq = 1; + msix->handle = qpair; ++ qla_mapq_init_qp_cpu_map(ha, msix, qpair); + return ret; + } +diff --git a/drivers/scsi/qla2xxx/qla_nvme.c b/drivers/scsi/qla2xxx/qla_nvme.c +index f535f478e37c8..088e84042efc7 100644 +--- a/drivers/scsi/qla2xxx/qla_nvme.c ++++ b/drivers/scsi/qla2xxx/qla_nvme.c +@@ -598,6 +598,7 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport, + fc_port_t *fcport; + struct srb_iocb *nvme; + struct scsi_qla_host *vha; ++ struct qla_hw_data *ha; + int rval; + srb_t *sp; + struct qla_qpair *qpair = hw_queue_handle; +@@ -618,6 +619,7 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport, + return -ENODEV; + + vha = fcport->vha; ++ ha = vha->hw; + + if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) + return -EBUSY; +@@ -632,6 +634,8 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport, + if (fcport->nvme_flag & NVME_FLAG_RESETTING) + return -EBUSY; + ++ qpair = qla_mapq_nvme_select_qpair(ha, qpair); ++ + /* Alloc SRB structure */ + sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC); + if (!sp) +diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c +index a40af9b832ab4..1b175e5c0cfcc 100644 +--- a/drivers/scsi/qla2xxx/qla_os.c ++++ b/drivers/scsi/qla2xxx/qla_os.c +@@ -467,6 +467,11 @@ static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, + "Unable to allocate memory for queue pair ptrs.\n"); + goto fail_qpair_map; + } ++ if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { ++ kfree(ha->queue_pair_map); ++ ha->queue_pair_map = NULL; ++ goto fail_qpair_map; ++ } + } + + /* +@@ -541,6 +546,7 @@ static void qla2x00_free_queues(struct qla_hw_data *ha) + ha->base_qpair = NULL; + } + ++ qla_mapq_free_qp_cpu_map(ha); + spin_lock_irqsave(&ha->hardware_lock, flags); + for (cnt = 0; cnt < ha->max_req_queues; cnt++) { + if (!test_bit(cnt, ha->req_qid_map)) +-- +2.40.1 + diff --git a/queue-5.15/scsi-qla2xxx-use-raw_smp_processor_id-instead-of-smp.patch b/queue-5.15/scsi-qla2xxx-use-raw_smp_processor_id-instead-of-smp.patch new file mode 100644 index 00000000000..73878c66888 --- /dev/null +++ b/queue-5.15/scsi-qla2xxx-use-raw_smp_processor_id-instead-of-smp.patch @@ -0,0 +1,125 @@ +From 8d2bb875f6c9af2132f9e4c91f758c81a95ea0c6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 31 Aug 2023 16:51:46 +0530 +Subject: scsi: qla2xxx: Use raw_smp_processor_id() instead of + smp_processor_id() + +From: Nilesh Javali + +[ Upstream commit 59f10a05b5c7b675256a66e3161741239889ff80 ] + +The following call trace was observed: + +localhost kernel: nvme nvme0: NVME-FC{0}: controller connect complete +localhost kernel: BUG: using smp_processor_id() in preemptible [00000000] code: kworker/u129:4/75092 +localhost kernel: nvme nvme0: NVME-FC{0}: new ctrl: NQN "nqn.1992-08.com.netapp:sn.b42d198afb4d11ecad6d00a098d6abfa:subsystem.PR_Channel2022_RH84_subsystem_291" +localhost kernel: caller is qla_nvme_post_cmd+0x216/0x1380 [qla2xxx] +localhost kernel: CPU: 6 PID: 75092 Comm: kworker/u129:4 Kdump: loaded Tainted: G B W OE --------- --- 5.14.0-70.22.1.el9_0.x86_64+debug #1 +localhost kernel: Hardware name: HPE ProLiant XL420 Gen10/ProLiant XL420 Gen10, BIOS U39 01/13/2022 +localhost kernel: Workqueue: nvme-wq nvme_async_event_work [nvme_core] +localhost kernel: Call Trace: +localhost kernel: dump_stack_lvl+0x57/0x7d +localhost kernel: check_preemption_disabled+0xc8/0xd0 +localhost kernel: qla_nvme_post_cmd+0x216/0x1380 [qla2xxx] + +Use raw_smp_processor_id() instead of smp_processor_id(). + +Also use queue_work() across the driver instead of queue_work_on() thus +avoiding usage of smp_processor_id() when CONFIG_DEBUG_PREEMPT is enabled. + +Cc: stable@vger.kernel.org +Suggested-by: John Garry +Signed-off-by: Nilesh Javali +Link: https://lore.kernel.org/r/20230831112146.32595-2-njavali@marvell.com +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/qla2xxx/qla_inline.h | 2 +- + drivers/scsi/qla2xxx/qla_isr.c | 6 +++--- + drivers/scsi/qla2xxx/qla_target.c | 3 +-- + drivers/scsi/qla2xxx/tcm_qla2xxx.c | 4 ++-- + 4 files changed, 7 insertions(+), 8 deletions(-) + +diff --git a/drivers/scsi/qla2xxx/qla_inline.h b/drivers/scsi/qla2xxx/qla_inline.h +index d5cf9db2a8ea3..e66441355f7ae 100644 +--- a/drivers/scsi/qla2xxx/qla_inline.h ++++ b/drivers/scsi/qla2xxx/qla_inline.h +@@ -577,7 +577,7 @@ fcport_is_bigger(fc_port_t *fcport) + static inline struct qla_qpair * + qla_mapq_nvme_select_qpair(struct qla_hw_data *ha, struct qla_qpair *qpair) + { +- int cpuid = smp_processor_id(); ++ int cpuid = raw_smp_processor_id(); + + if (qpair->cpuid != cpuid && + ha->qp_cpu_map[cpuid]) { +diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c +index a13732921b5c0..4f6aab2599350 100644 +--- a/drivers/scsi/qla2xxx/qla_isr.c ++++ b/drivers/scsi/qla2xxx/qla_isr.c +@@ -3780,7 +3780,7 @@ void qla24xx_process_response_queue(struct scsi_qla_host *vha, + if (!ha->flags.fw_started) + return; + +- if (rsp->qpair->cpuid != smp_processor_id() || !rsp->qpair->rcv_intr) { ++ if (rsp->qpair->cpuid != raw_smp_processor_id() || !rsp->qpair->rcv_intr) { + rsp->qpair->rcv_intr = 1; + } + +@@ -4276,7 +4276,7 @@ qla2xxx_msix_rsp_q(int irq, void *dev_id) + } + ha = qpair->hw; + +- queue_work_on(smp_processor_id(), ha->wq, &qpair->q_work); ++ queue_work(ha->wq, &qpair->q_work); + + return IRQ_HANDLED; + } +@@ -4302,7 +4302,7 @@ qla2xxx_msix_rsp_q_hs(int irq, void *dev_id) + wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); + spin_unlock_irqrestore(&ha->hardware_lock, flags); + +- queue_work_on(smp_processor_id(), ha->wq, &qpair->q_work); ++ queue_work(ha->wq, &qpair->q_work); + + return IRQ_HANDLED; + } +diff --git a/drivers/scsi/qla2xxx/qla_target.c b/drivers/scsi/qla2xxx/qla_target.c +index 2ce041fdec755..ef46dce73978a 100644 +--- a/drivers/scsi/qla2xxx/qla_target.c ++++ b/drivers/scsi/qla2xxx/qla_target.c +@@ -4459,8 +4459,7 @@ static int qlt_handle_cmd_for_atio(struct scsi_qla_host *vha, + queue_work_on(cmd->se_cmd.cpuid, qla_tgt_wq, &cmd->work); + } else if (ha->msix_count) { + if (cmd->atio.u.isp24.fcp_cmnd.rddata) +- queue_work_on(smp_processor_id(), qla_tgt_wq, +- &cmd->work); ++ queue_work(qla_tgt_wq, &cmd->work); + else + queue_work_on(cmd->se_cmd.cpuid, qla_tgt_wq, + &cmd->work); +diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c +index 03de1bcf1461d..b3852be971e46 100644 +--- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c ++++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c +@@ -310,7 +310,7 @@ static void tcm_qla2xxx_free_cmd(struct qla_tgt_cmd *cmd) + cmd->trc_flags |= TRC_CMD_DONE; + + INIT_WORK(&cmd->work, tcm_qla2xxx_complete_free); +- queue_work_on(smp_processor_id(), tcm_qla2xxx_free_wq, &cmd->work); ++ queue_work(tcm_qla2xxx_free_wq, &cmd->work); + } + + /* +@@ -557,7 +557,7 @@ static void tcm_qla2xxx_handle_data(struct qla_tgt_cmd *cmd) + cmd->trc_flags |= TRC_DATA_IN; + cmd->cmd_in_wq = 1; + INIT_WORK(&cmd->work, tcm_qla2xxx_handle_data_work); +- queue_work_on(smp_processor_id(), tcm_qla2xxx_free_wq, &cmd->work); ++ queue_work(tcm_qla2xxx_free_wq, &cmd->work); + } + + static int tcm_qla2xxx_chk_dif_tags(uint32_t tag) +-- +2.40.1 + diff --git a/queue-5.15/series b/queue-5.15/series index 0671f8a25dd..75b48de1f19 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -75,3 +75,17 @@ xfs-explicitly-specify-cpu-when-forcing-inodegc-dela.patch xfs-check-that-per-cpu-inodegc-workers-actually-run-.patch xfs-disable-reaping-in-fscounters-scrub.patch xfs-fix-xfs_inodegc_stop-racing-with-mod_delayed_wor.patch +input-i8042-rename-i8042-x86ia64io.h-to-i8042-acpipn.patch +input-i8042-add-quirk-for-tuxedo-gemini-17-gen1-clev.patch +perf-jevents-switch-build-to-use-jevents.py.patch +perf-build-update-build-rule-for-generated-files.patch +arm64-dts-qcom-sdm845-db845c-mark-cont-splash-memory.patch +bpf-fix-issue-in-verifying-allow_ptr_leaks.patch +netfilter-exthdr-add-support-for-tcp-option-removal.patch +netfilter-nft_exthdr-fix-non-linear-header-modificat.patch +ata-libata-rename-link-flag-ata_lflag_no_db_delay.patch +ata-ahci-add-support-for-amd-a85-fch-hudson-d4.patch +ata-ahci-rename-board_ahci_mobile.patch +ata-ahci-add-elkhart-lake-ahci-controller.patch +scsi-qla2xxx-select-qpair-depending-on-which-cpu-pos.patch +scsi-qla2xxx-use-raw_smp_processor_id-instead-of-smp.patch