From: Niravkumar L Rabara Date: Tue, 27 May 2025 14:57:07 +0000 (-0700) Subject: EDAC/altera: Use correct write width with the INTTEST register X-Git-Tag: v5.10.239~162 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=9d052a1165cef79c964b6d5f49c1fffb187a6fe1;p=thirdparty%2Fkernel%2Fstable.git EDAC/altera: Use correct write width with the INTTEST register commit e5ef4cd2a47f27c0c9d8ff6c0f63a18937c071a3 upstream. On the SoCFPGA platform, the INTTEST register supports only 16-bit writes. A 32-bit write triggers an SError to the CPU so do 16-bit accesses only. [ bp: AI-massage the commit message. ] Fixes: c7b4be8db8bc ("EDAC, altera: Add Arria10 OCRAM ECC support") Signed-off-by: Niravkumar L Rabara Signed-off-by: Matthew Gerlach Signed-off-by: Borislav Petkov (AMD) Acked-by: Dinh Nguyen Cc: stable@kernel.org Link: https://lore.kernel.org/20250527145707.25458-1-matthew.gerlach@altera.com Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 99aaada3a2d96..61de8b1ed75ec 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1704,9 +1704,9 @@ static ssize_t altr_edac_a10_device_trig(struct file *file, local_irq_save(flags); if (trig_type == ALTR_UE_TRIGGER_CHAR) - writel(priv->ue_set_mask, set_addr); + writew(priv->ue_set_mask, set_addr); else - writel(priv->ce_set_mask, set_addr); + writew(priv->ce_set_mask, set_addr); /* Ensure the interrupt test bits are set */ wmb(); @@ -1736,7 +1736,7 @@ static ssize_t altr_edac_a10_device_trig2(struct file *file, local_irq_save(flags); if (trig_type == ALTR_UE_TRIGGER_CHAR) { - writel(priv->ue_set_mask, set_addr); + writew(priv->ue_set_mask, set_addr); } else { /* Setup read/write of 4 bytes */ writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);