From: John Linn <john.linn@xilinx.com>
Date: Tue, 13 Dec 2011 16:20:36 +0000 (-0800)
Subject: Xilinx: ARM: SD: speed up SD by removing the clock divide
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a0d4d7e736ac3fc721ea59a54e3d4c94c3853a2a;p=thirdparty%2Fu-boot.git

Xilinx: ARM: SD: speed up SD by removing the clock divide

It's not clear why it was was running so slow, but maybe
it was needed for EP107. Speed it up now.
---

diff --git a/board/xilinx/dfe/mmc.c b/board/xilinx/dfe/mmc.c
index 91b21db0112..dd952fc5840 100755
--- a/board/xilinx/dfe/mmc.c
+++ b/board/xilinx/dfe/mmc.c
@@ -73,7 +73,7 @@ static void init_port(void)
 	sd_out8(SD_PWR_CTRL_R, SD_POWER_33|SD_POWER_ON);
 
 	/* Enable Internal clock and wait for it to stablilize */
-	clk = (0x40 << SD_DIV_SHIFT) | SD_CLK_INT_EN;
+	clk = SD_CLK_INT_EN;
 	sd_out16(SD_CLK_CTL_R, clk);
 	do {
 		clk = sd_in16(SD_CLK_CTL_R);