From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Thu, 9 Apr 2026 16:24:38 +0000 (+0200)
Subject: realtek: dts: fix TP-Link SG2452P mdio bus
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a2540f566f4b5e69bb8a7d4d48904295fcd45aca;p=thirdparty%2Fopenwrt.git

realtek: dts: fix TP-Link SG2452P mdio bus

For some unknown reason carving out the mdio bus from the ethernet
node forgot the TP-Link SG2452P. The notation still reads

&ethernet0 {
  mdio: mdio-bus {
    compatible = "realtek,rtl838x-mdio";
    ...

Like everywhere else it should be

&mdio_bus0 {
  PHY_C22(0, 0)
  ...

Fix that.

Fixes: 57b270684 ("rearrange mdio-bus below mdio-controller")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22866
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---

diff --git a/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts b/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
index 515c63f6071..10526efc5c8 100644
--- a/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
+++ b/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
@@ -277,72 +277,68 @@
 &ethernet0 {
 	nvmem-cells = <&factory_macaddr>;
 	nvmem-cell-names = "mac-address";
+};
 
-	mdio: mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* External phy RTL8218B #1 */
-		PHY_C22(0, 0)
-		PHY_C22(1, 1)
-		PHY_C22(2, 2)
-		PHY_C22(3, 3)
-		PHY_C22(4, 4)
-		PHY_C22(5, 5)
-		PHY_C22(6, 6)
-		PHY_C22(7, 7)
-
-		/* External phy RTL8218B #2 */
-		PHY_C22(8, 8)
-		PHY_C22(9, 9)
-		PHY_C22(10, 10)
-		PHY_C22(11, 11)
-		PHY_C22(12, 12)
-		PHY_C22(13, 13)
-		PHY_C22(14, 14)
-		PHY_C22(15, 15)
-
-		/* External phy RTL8218B #3 */
-		PHY_C22(16, 16)
-		PHY_C22(17, 17)
-		PHY_C22(18, 18)
-		PHY_C22(19, 19)
-		PHY_C22(20, 20)
-		PHY_C22(21, 21)
-		PHY_C22(22, 22)
-		PHY_C22(23, 23)
-
-		/* External phy RTL8218B #4 */
-		PHY_C22(24, 24)
-		PHY_C22(25, 25)
-		PHY_C22(26, 26)
-		PHY_C22(27, 27)
-		PHY_C22(28, 28)
-		PHY_C22(29, 29)
-		PHY_C22(30, 30)
-		PHY_C22(31, 31)
-
-		/* External phy RTL8218B #5 */
-		PHY_C22(32, 32)
-		PHY_C22(33, 33)
-		PHY_C22(34, 34)
-		PHY_C22(35, 35)
-		PHY_C22(36, 36)
-		PHY_C22(37, 37)
-		PHY_C22(38, 38)
-		PHY_C22(39, 39)
-
-		/* External phy RTL8218B #6 */
-		PHY_C22(40, 40)
-		PHY_C22(41, 41)
-		PHY_C22(42, 42)
-		PHY_C22(43, 43)
-		PHY_C22(44, 44)
-		PHY_C22(45, 45)
-		PHY_C22(46, 46)
-		PHY_C22(47, 47)
-	};
+&mdio_bus0 {
+	/* External phy RTL8218B #1 */
+	PHY_C22(0, 0)
+	PHY_C22(1, 1)
+	PHY_C22(2, 2)
+	PHY_C22(3, 3)
+	PHY_C22(4, 4)
+	PHY_C22(5, 5)
+	PHY_C22(6, 6)
+	PHY_C22(7, 7)
+
+	/* External phy RTL8218B #2 */
+	PHY_C22(8, 8)
+	PHY_C22(9, 9)
+	PHY_C22(10, 10)
+	PHY_C22(11, 11)
+	PHY_C22(12, 12)
+	PHY_C22(13, 13)
+	PHY_C22(14, 14)
+	PHY_C22(15, 15)
+
+	/* External phy RTL8218B #3 */
+	PHY_C22(16, 16)
+	PHY_C22(17, 17)
+	PHY_C22(18, 18)
+	PHY_C22(19, 19)
+	PHY_C22(20, 20)
+	PHY_C22(21, 21)
+	PHY_C22(22, 22)
+	PHY_C22(23, 23)
+
+	/* External phy RTL8218B #4 */
+	PHY_C22(24, 24)
+	PHY_C22(25, 25)
+	PHY_C22(26, 26)
+	PHY_C22(27, 27)
+	PHY_C22(28, 28)
+	PHY_C22(29, 29)
+	PHY_C22(30, 30)
+	PHY_C22(31, 31)
+
+	/* External phy RTL8218B #5 */
+	PHY_C22(32, 32)
+	PHY_C22(33, 33)
+	PHY_C22(34, 34)
+	PHY_C22(35, 35)
+	PHY_C22(36, 36)
+	PHY_C22(37, 37)
+	PHY_C22(38, 38)
+	PHY_C22(39, 39)
+
+	/* External phy RTL8218B #6 */
+	PHY_C22(40, 40)
+	PHY_C22(41, 41)
+	PHY_C22(42, 42)
+	PHY_C22(43, 43)
+	PHY_C22(44, 44)
+	PHY_C22(45, 45)
+	PHY_C22(46, 46)
+	PHY_C22(47, 47)
 };
 
 &switch0 {