From: Shiji Yang Date: Sat, 31 May 2025 15:13:10 +0000 (+0800) Subject: ipq806x: restore kernel 6.6 config files and patches X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a33d59f7af8f;p=thirdparty%2Fopenwrt.git ipq806x: restore kernel 6.6 config files and patches Copy patches and kernel configs from 6.12 kernel to restore the default 6.6 kernel support files. Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/18989 Signed-off-by: Christian Marangi --- diff --git a/target/linux/ipq806x/config-6.6 b/target/linux/ipq806x/config-6.6 new file mode 100644 index 00000000000..cd0870f103b --- /dev/null +++ b/target/linux/ipq806x/config-6.6 @@ -0,0 +1,534 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_APQ_GCC_8084 is not set +# CONFIG_APQ_MMCC_8084 is not set +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# CONFIG_ARCH_IPQ40XX is not set +CONFIG_ARCH_KEEP_MEMBLOCK=y +# CONFIG_ARCH_MDM9615 is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_ARCH_MSM8909 is not set +# CONFIG_ARCH_MSM8916 is not set +CONFIG_ARCH_MSM8960=y +CONFIG_ARCH_MSM8974=y +CONFIG_ARCH_MSM8X60=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y +CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_CPU_SUSPEND=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y +CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_QCOM_CPUFREQ_HW is not set +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_ARM_QCOM_SPM_CPUIDLE=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT803X_PHY=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLKSRC_QCOM=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE_OVERRIDE=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRC8=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEV_QCOM_RNG=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEVFREQ_GOV_PASSIVE=y +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +# CONFIG_DWMAC_GENERIC is not set +CONFIG_DWMAC_IPQ806X=y +# CONFIG_DWMAC_QCOM_ETHQOS is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +# CONFIG_I2C_QCOM_CCI is not set +CONFIG_I2C_QUP=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IOMMUFD is not set +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IPQ_APSS_PLL is not set +# CONFIG_IPQ_GCC_4019 is not set +# CONFIG_IPQ_GCC_5018 is not set +# CONFIG_IPQ_GCC_6018 is not set +CONFIG_IPQ_GCC_806X=y +# CONFIG_IPQ_GCC_8074 is not set +# CONFIG_IPQ_GCC_9574 is not set +# CONFIG_IPQ_LCC_806X is not set +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +CONFIG_KPSS_XCC=y +CONFIG_KRAITCC=y +CONFIG_KRAIT_CLOCKS=y +CONFIG_KRAIT_L2_ACCESSORS=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_GPIO=y +CONFIG_MDIO_IPQ8064=y +# CONFIG_MDM_GCC_9615 is not set +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_QCOM_RPM=y +# CONFIG_MFD_SPMI_PMIC is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=16 +CONFIG_MMC_CQHCI=y +CONFIG_MMC_QCOM_DML=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_MSM=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MSM_GCC_8660=y +# CONFIG_MSM_GCC_8909 is not set +# CONFIG_MSM_GCC_8916 is not set +# CONFIG_MSM_GCC_8939 is not set +# CONFIG_MSM_GCC_8960 is not set +# CONFIG_MSM_GCC_8974 is not set +# CONFIG_MSM_GCC_8976 is not set +# CONFIG_MSM_GCC_8994 is not set +# CONFIG_MSM_GCC_8996 is not set +# CONFIG_MSM_GCC_8998 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_IOMMU is not set +# CONFIG_MSM_LCC_8960 is not set +# CONFIG_MSM_MMCC_8960 is not set +# CONFIG_MSM_MMCC_8974 is not set +# CONFIG_MSM_MMCC_8996 is not set +# CONFIG_MSM_MMCC_8998 is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_QCOMSMEM_PARTS=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NEON=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_QCA8K=y +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_TAG_QCA=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_ASCII_ENV=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_NVMEM_QCOM_QFPROM=y +# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_QCOM=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCS_XPCS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +# CONFIG_PHY_QCOM_EDP is not set +# CONFIG_PHY_QCOM_EUSB2_REPEATER is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set +CONFIG_PHY_QCOM_IPQ806X_SATA=y +# CONFIG_PHY_QCOM_IPQ806X_USB is not set +# CONFIG_PHY_QCOM_M31_USB is not set +# CONFIG_PHY_QCOM_PCIE2 is not set +# CONFIG_PHY_QCOM_QMP is not set +# CONFIG_PHY_QCOM_QUSB2 is not set +# CONFIG_PHY_QCOM_SGMII_ETH is not set +# CONFIG_PHY_QCOM_SNPS_EUSB2 is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_SS is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_APQ8064 is not set +# CONFIG_PINCTRL_APQ8084 is not set +# CONFIG_PINCTRL_IPQ4019 is not set +CONFIG_PINCTRL_IPQ8064=y +# CONFIG_PINCTRL_MDM9615 is not set +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8226 is not set +# CONFIG_PINCTRL_MSM8660 is not set +# CONFIG_PINCTRL_MSM8909 is not set +# CONFIG_PINCTRL_MSM8916 is not set +# CONFIG_PINCTRL_MSM8960 is not set +# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set +# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +# CONFIG_PINCTRL_SDX65 is not set +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QCA83XX_PHY=y +# CONFIG_QCM_DISPCC_2290 is not set +# CONFIG_QCM_GCC_2290 is not set +# CONFIG_QCOM_A53PLL is not set +CONFIG_QCOM_ADM=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_CLK_RPM=y +# CONFIG_QCOM_COMMAND_DB is not set +# CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_EBI2 is not set +# CONFIG_QCOM_GENI_SE is not set +CONFIG_QCOM_GSBI=y +CONFIG_QCOM_HFPLL=y +# CONFIG_QCOM_ICC_BWMON is not set +# CONFIG_QCOM_IOMMU is not set +# CONFIG_QCOM_LLCC is not set +CONFIG_QCOM_NET_PHYLIB=y +# CONFIG_QCOM_OCMEM is not set +# CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_RAMP_CTRL is not set +# CONFIG_QCOM_RMTFS_MEM is not set +CONFIG_QCOM_RPMCC=y +# CONFIG_QCOM_RPMH is not set +CONFIG_QCOM_RPM_MASTER_STATS=y +CONFIG_QCOM_SCM=y +# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +CONFIG_QCOM_SMEM=y +# CONFIG_QCOM_SMSM is not set +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_SPM=y +# CONFIG_QCOM_STATS is not set +CONFIG_QCOM_TCSR=y +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_WDT=y +# CONFIG_QCS_GCC_404 is not set +# CONFIG_QCS_Q6SSTOP_404 is not set +# CONFIG_QCS_TURING_404 is not set +# CONFIG_QDU_GCC_1000 is not set +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_QCOM_LABIBB is not set +CONFIG_REGULATOR_QCOM_RPM=y +# CONFIG_REGULATOR_QCOM_SPMI is not set +# CONFIG_REGULATOR_QCOM_USB_VBUS is not set +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_QCOM_AOSS is not set +# CONFIG_RESET_QCOM_PDC is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_SA_GCC_8775P is not set +# CONFIG_SA_GPUCC_8775P is not set +# CONFIG_SDX_GCC_65 is not set +# CONFIG_SDX_GCC_75 is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +# CONFIG_SM_GCC_7150 is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_QPIC_SNAND is not set +CONFIG_SPI_QUP=y +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +CONFIG_SPMI_MSM_PMIC_ARB=y +# CONFIG_SPMI_PMIC_CLKDIV is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8062-wg2600hp3.dts new file mode 100644 index 00000000000..76751910e01 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8062-wg2600hp3.dts @@ -0,0 +1,743 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8062-smb208.dtsi" +#include +#include + +/ { + model = "NEC Platforms Aterm WG2600HP3"; + compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064"; + + memory { + device_type = "memory"; + reg = <0x42000000 0x1e000000>; + }; + + aliases { + label-mac-device = &gmac2; + + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_red; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + mode0 { + label = "mode0"; + gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + mode1 { + label = "mode1"; + gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; + }; + + led_power_red: power_red { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>; + }; + + active_green { + label = "green:active"; + gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>; + }; + + active_red { + label = "red:active"; + gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + + wlan2g_red { + label = "red:wlan2g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + wlan5g_red { + label = "red:wlan5g"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; + }; + + tv_green { + label = "green:tv"; + gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>; + }; + + tv_red { + label = "red:tv"; + gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>; + }; + + converter_green { + label = "green:converter"; + gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>; + }; + + converter_red { + label = "red:converter"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* nand_pins are used for leds_pins, empty the node + * from ipq8064.dtsi + */ +&nand_pins { + /delete-property/ disable; + /delete-property/ pullups; + /delete-property/ hold; +}; + +&qcom_pinmux { + pinctrl-0 = <&akro_pins>; + pinctrl-names = "default"; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + buttons_pins: buttons_pins { + mux { + pins = "gpio22", "gpio24", "gpio40", + "gpio41"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio14", "gpio15", "gpio35", + "gpio36", "gpio38", "gpio42", + "gpio43", "gpio46", "gpio55", + "gpio56", "gpio57", "gpio58"; + function = "gpio"; + bias-pull-down; + }; + + akro2 { + pins = "gpio15", "gpio35", "gpio38", + "gpio42", "gpio43", "gpio46", + "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <2>; + }; + + akro4 { + pins = "gpio14", "gpio36"; + drive-strength = <4>; + }; + }; + + /* + * Stock firmware has the following settings, so let's do the same. + * I don't sure why these are required. + */ + akro_pins: akro_pinmux { + akro { + pins = "gpio17", "gpio26", "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset { + pins = "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + gmac0_rgmii { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0000000 0x0020000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x0020000 0x0020000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x0040000 0x0040000>; + read-only; + }; + + partition@80000 { + label = "SBL3"; + reg = <0x0080000 0x0080000>; + read-only; + }; + + partition@100000 { + label = "DDRCONFIG"; + reg = <0x0100000 0x0010000>; + read-only; + }; + + partition@110000 { + label = "SSD"; + reg = <0x0110000 0x0010000>; + read-only; + }; + + partition@120000 { + label = "TZ"; + reg = <0x0120000 0x0080000>; + read-only; + }; + + partition@1a0000 { + label = "RPM"; + reg = <0x01a0000 0x0080000>; + read-only; + }; + + partition@220000 { + label = "APPSBL"; + reg = <0x0220000 0x0080000>; + read-only; + }; + + partition@2a0000 { + label = "APPSBLENV"; + reg = <0x02a0000 0x0010000>; + read-only; + }; + + factory: partition@2b0000 { + label = "PRODUCTDATA"; + reg = <0x02b0000 0x0030000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_factory_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_PRODUCTDATA_c: macaddr@c { + reg = <0xc 0x6>; + }; + + macaddr_PRODUCTDATA_12: macaddr@12 { + reg = <0x12 0x6>; + }; + }; + }; + + partition@2e0000 { + label = "ART"; + reg = <0x02e0000 0x0040000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + partition@320000 { + label = "TP"; + reg = <0x0320000 0x0040000>; + read-only; + }; + + partition@360000 { + label = "TINY"; + reg = <0x0360000 0x0500000>; + read-only; + }; + + partition@860000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x0860000 0x17a0000>; + }; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; + + nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + force_gen1 = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + ieee80211-freq-limit = <2400000 2483000>; + qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; + + nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + function-enumerator = <1>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + function-enumerator = <2>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_WAN; + function-enumerator = <3>; + default-state = "keep"; + }; + }; + }; + + port@2 { + reg = <2>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + default-state = "keep"; + }; + }; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + default-state = "keep"; + }; + }; + }; + + port@4 { + reg = <4>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + default-state = "keep"; + }; + }; + }; + + port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + default-state = "keep"; + }; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-rxclk-falling-edge; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + mdiobus = <&mdio0>; + nvmem-cells = <&macaddr_factory_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + mdiobus = <&mdio0>; + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200-c2600.dtsi new file mode 100644 index 00000000000..d8e018367eb --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200-c2600.dtsi @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include + +/ { + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + ramoops@42100000 { + compatible = "ramoops"; + reg = <0x42100000 0x40000>; + record-size = <0x4000>; + console-size = <0x4000>; + ftrace-size = <0x4000>; + pmsg-size = <0x4000>; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + label-mac-device = &gmac2; + }; +}; + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb0_pwr_en_pin: usb0_pwr_en_pin { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + output-high; + }; + }; + + usb1_pwr_en_pin: usb1_pwr_en_pin { + mux { + pins = "gpio23"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + output-high; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "SBL3"; + reg = <0x60000 0x30000>; + read-only; + }; + + partition@90000 { + label = "DDRCONFIG"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "SSD"; + reg = <0xa0000 0x10000>; + read-only; + }; + + partition@b0000 { + label = "TZ"; + reg = <0xb0000 0x30000>; + read-only; + }; + + partition@e0000 { + label = "RPM"; + reg = <0xe0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "fs-uboot"; + reg = <0x100000 0x70000>; + read-only; + }; + + partition@170000 { + label = "uboot-env"; + reg = <0x170000 0x40000>; + read-only; + }; + + partition@1b0000 { + label = "radio"; + reg = <0x1b0000 0x40000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_radio_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_radio_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + partition@1f0000 { + label = "os-image"; + reg = <0x1f0000 0x400000>; + }; + + partition@5f0000 { + label = "rootfs"; + reg = <0x5f0000 0x1900000>; + }; + + defaultmac: partition@1ef0000 { + label = "default-mac"; + reg = <0x1ef0000 0x00200>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_defaultmac_8: macaddr@8 { + compatible = "mac-base"; + reg = <0x8 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@1ef0200 { + label = "pin"; + reg = <0x1ef0200 0x00200>; + read-only; + }; + + partition@1ef0400 { + label = "product-info"; + reg = <0x1ef0400 0x0fc00>; + read-only; + }; + + partition@1f00000 { + label = "partition-table"; + reg = <0x1f00000 0x10000>; + read-only; + }; + + partition@1f10000 { + label = "soft-version"; + reg = <0x1f10000 0x10000>; + read-only; + }; + + partition@1f20000 { + label = "support-list"; + reg = <0x1f20000 0x10000>; + read-only; + }; + + partition@1f30000 { + label = "profile"; + reg = <0x1f30000 0x10000>; + read-only; + }; + + partition@1f40000 { + label = "default-config"; + reg = <0x1f40000 0x10000>; + read-only; + }; + + partition@1f50000 { + label = "user-config"; + reg = <0x1f50000 0x40000>; + read-only; + }; + + partition@1f90000 { + label = "qos-db"; + reg = <0x1f90000 0x40000>; + read-only; + }; + + partition@1fd0000 { + label = "usb-config"; + reg = <0x1fd0000 0x10000>; + read-only; + }; + + partition@1fe0000 { + label = "log"; + reg = <0x1fe0000 0x20000>; + read-only; + }; + }; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pin>; + pinctrl-names = "default"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pin>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_8 (-1)>, <&precal_radio_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_8 0>, <&precal_radio_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_defaultmac_8 1>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_defaultmac_8 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200.dts new file mode 100644 index 00000000000..6e4c9bc773c --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include + +#include "qcom-ipq8064-ad7200-c2600.dtsi" + +/ { + model = "TP-Link Talon AD7200"; + compatible = "tplink,ad7200", "qcom,ipq8064"; + + aliases { + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + led_enable { + label = "led-enable"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>; + }; + + usb1 { + label = "blue:usb1"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + wlan5g { + label = "blue:wlan5g"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + + usb3 { + label = "blue:usb3"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan2g { + label = "blue:wlan2g"; + gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; + }; + + wan_orange { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + wan_blue { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; + }; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; + + wlan60g { + label = "blue:wlan60g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + led_status: status { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio53", "gpio54", "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26", + "gpio33", "gpio55", "gpio56", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&mdio0 { + switch@10 { + ports { + port@1 { + label = "wan"; + }; + + port@2 { + label = "lan1"; + }; + + port@3 { + label = "lan2"; + }; + + port@4 { + label = "lan3"; + }; + + port@5 { + label = "lan4"; + }; + }; + }; +}; + +&pcie2 { + status = "okay"; + max-link-speed = <1>; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts new file mode 100644 index 00000000000..bd8f0d60192 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts @@ -0,0 +1,219 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&flash { + partitions { + compatible = "qcom,smem-part"; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + /* + port@6 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + asym-pause; + }; + }; + */ + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap161.dts new file mode 100644 index 00000000000..9d0b451f436 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap161.dts @@ -0,0 +1,254 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/AP161"; + compatible = "qcom,ipq8064-ap161", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; +}; + +&qcom_pinmux { + rgmii2_pins: rgmii2-pins { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62", + "gpio2", "gpio66"; + }; + }; +}; + +&flash { + partitions { + compatible = "qcom,smem-part"; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&pcie2 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + /* + port@6 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + asym-pause; + }; + }; + */ + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; + + phy3: ethernet-phy@3 { + device_type = "ethernet-phy"; + reg = <3>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-asus-onhub.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-asus-onhub.dts new file mode 100644 index 00000000000..442bcf19a67 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-asus-onhub.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2014 The ChromiumOS Authors + */ + +#include "qcom-ipq8064-onhub.dtsi" +#include +#include +#include + +/ { + model = "ASUS OnHub"; + compatible = "asus,onhub", "google,arkham", "qcom,ipq8064"; +}; + +&qcom_pinmux { + ap3223_pins: ap3223_pinmux { + pins = "gpio22"; + function = "gpio"; + bias-none; + }; + + i2c7_pins: i2c7_pinmux { + mux { + pins = "gpio8", "gpio9"; + function = "gsbi7"; + }; + data { + pins = "gpio8"; + bias-disable; + }; + clk { + pins = "gpio9"; + bias-disable; + }; + }; +}; + +&gsbi7 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi7_i2c { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + + ap3223@1c { + compatible = "dynaimage,ap3223"; + reg = <0x1c>; + + pinctrl-0 = <&ap3223_pins>; + pinctrl-names = "default"; + + int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; + }; + + led-controller@32 { + compatible = "national,lp5523"; + reg = <0x32>; + clock-mode = /bits/ 8 <1>; + #address-cells = <1>; + #size-cells = <0>; + + led@4 { + reg = <4>; + color = ; + chan-name = "green:status"; + linux,default-trigger = "default-on"; + led-cur = /bits/ 8 <0xfa>; + max-cur = /bits/ 8 <0xff>; + }; + + led@5 { + reg = <5>; + color = ; + chan-name = "blue:status"; + led-cur = /bits/ 8 <0xfa>; + max-cur = /bits/ 8 <0xff>; + }; + + led@8 { + reg = <8>; + color = ; + chan-name = "red:status"; + led-cur = /bits/ 8 <0xfa>; + max-cur = /bits/ 8 <0xff>; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-c2600.dts new file mode 100644 index 00000000000..b8cb25ede0c --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-c2600.dts @@ -0,0 +1,126 @@ +#include + +#include "qcom-ipq8064-ad7200-c2600.dtsi" + +/ { + model = "TP-Link Archer C2600"; + compatible = "tplink,c2600", "qcom,ipq8064"; + + aliases { + led-boot = &power; + led-failsafe = &general; + led-running = &power; + led-upgrade = &general; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ledswitch { + label = "ledswitch"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; + }; + + usb4 { + label = "white:usb_4"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb_2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + wan_white { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; + }; + + power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + general: general { + label = "white:general"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio16", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33", + "gpio53", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-d7800.dts new file mode 100644 index 00000000000..24a7d2ca156 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-d7800.dts @@ -0,0 +1,485 @@ +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include + +/ { + model = "Netgear Nighthawk X4 D7800"; + compatible = "netgear,d7800", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + power_amber: power_amber { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power_white: power_white { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie2 { + status = "okay"; + reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + compatible = "mac-base"; + reg = <0x6 0x6>; + #nvmem-cell-cells = <1>; + }; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + artbak: art@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + kernel@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + + ubi@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + reserve@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-db149.dts new file mode 100644 index 00000000000..063f27c6d2d --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-db149.dts @@ -0,0 +1,263 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/DB149"; + compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi2_serial; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&qcom_pinmux { + rgmii0_pins: rgmii0_pins { + mux { + pins = "gpio2", "gpio66"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&gsbi2 { + qcom,mode = ; + status = "okay"; + + gsbi2_serial: serial@12490000 { + status = "okay"; + }; +}; + +&gsbi4 { + status = "disabled"; +}; + +&gsbi4_serial { + status = "disabled"; +}; + +&flash { + m25p,fast-read; + + partition@0 { + label = "lowlevel_init"; + reg = <0x0 0x1b0000>; + }; + + partition@1 { + label = "u-boot"; + reg = <0x1b0000 0x80000>; + }; + + partition@2 { + label = "u-boot-env"; + reg = <0x230000 0x40000>; + }; + + partition@3 { + label = "caldata"; + reg = <0x270000 0x40000>; + }; + + partition@4 { + label = "firmware"; + reg = <0x2b0000 0x1d50000>; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + /* + port@6 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + asym-pause; + }; + }; + */ + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + }; + + phy7: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + pinctrl-0 = <&rgmii0_pins>; + pinctrl-names = "default"; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + phy-handle = <&phy6>; +}; + +&gmac3 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <3>; + phy-handle = <&phy7>; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-e8350-v1.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-e8350-v1.dts new file mode 100644 index 00000000000..52d6b77b492 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-e8350-v1.dts @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include + +/ { + model = "Linksys E8350 V1 WiFi Router"; + compatible = "linksys,e8350-v1", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + serial0 = &gsbi4_serial; + + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "green:power"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wps { + label = "green:wps"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + wifi { + label = "green:wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ubi"; + reg = <0 0x4000000>; + }; + partition@4000000 { + label = "extra"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio68","gpio65", "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio26","gpio53", "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + switch_reset: switch_reset_pins { + mux { + pins = "gpio63"; + function = "gpio"; + drive-strength = <12>; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi5: spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <51200000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:sbl1"; + reg = <0x0000000 0x0010000>; + read-only; + }; + + partition@10000 { + label = "0:mibib"; + reg = <0x0010000 0x0020000>; + read-only; + }; + + partition@30000 { + label = "0:sbl2"; + reg = <0x0030000 0x0020000>; + read-only; + }; + + partition@50000 { + label = "0:sbl3"; + reg = <0x0050000 0x0030000>; + read-only; + }; + + partition@80000 { + label = "0:ddrconfig"; + reg = <0x0080000 0x0010000>; + read-only; + }; + + partition@90000 { + label = "0:ssd"; + reg = <0x0090000 0x0010000>; + read-only; + }; + + partition@a0000 { + label = "0:tz"; + reg = <0x00a0000 0x0030000>; + read-only; + }; + + partition@d0000 { + label = "0:rpm"; + reg = <0x00d0000 0x0020000>; + read-only; + }; + + partition@f0000 { + label = "0:oldappsbl"; + reg = <0x00f0000 0x0040000>; + read-only; + }; + + partition@130000 { + label = "0:appsblenv"; + reg = <0x0130000 0x0040000>; + read-only; + }; + + art: partition@170000 { + label = "0:ART"; + reg = <0x0170000 0x0020000>; + read-only; + }; + + partition@190000 { + label = "0:uboot"; + reg = <0x0190000 0x0050000>; + read-only; + }; + + partition@1e0000 { + label = "0:oldnss1"; + reg = <0x01e0000 0x0020000>; + read-only; + }; + + partition@200000 { + label = "0:nvram"; + reg = <0x0200000 0x0020000>; + read-only; + }; + + partition@220000 { + label = "0:oldkernel"; + reg = <0x0220000 0x01e0000>; + read-only; + }; + }; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + max-link-speed = <1>; +}; + +&pcie1 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + /* Switch from documentation require at least 12ms for reset */ + reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; + reset-post-delay-us = <12000>; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&tcsr { + qcom,usb-ctrl-select = ; + compatible = "qcom,tcsr", "syscon"; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea7500-v1.dts new file mode 100644 index 00000000000..2a565cc2db2 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea7500-v1.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include + +#include "qcom-ipq8064-eax500.dtsi" + +/ { + model = "Linksys EA7500 V1 WiFi Router"; + compatible = "linksys,ea7500-v1", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0xe000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + chosen { + /* look for root deviceblock nbr in this bootarg */ + find-rootblock = "ubi.mtd="; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio65", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&partitions { + partition@5f80000 { + label = "sysdiag"; + reg = <0x5f80000 0x100000>; + }; + + partition@6080000 { + label = "syscfg"; + reg = <0x6080000 0x1f80000>; + }; +}; + +&mdio0 { + switch@10 { + ports { + port@1 { + label = "wan"; + }; + + port@2 { + label = "lan1"; + }; + + port@3 { + label = "lan2"; + }; + + port@4 { + label = "lan3"; + }; + + port@5 { + label = "lan4"; + }; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea8500.dts new file mode 100644 index 00000000000..d9155081a58 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea8500.dts @@ -0,0 +1,126 @@ +#include + +#include "qcom-ipq8064-eax500.dtsi" + +/ { + model = "Linksys EA8500 WiFi Router"; + compatible = "linksys,ea8500", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + led_power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + wifi { + label = "green:wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio65", "gpio67", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio53", "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&partitions { + partition@5f80000 { + label = "syscfg"; + reg = <0x5f80000 0x2080000>; + }; +}; + +&gmac1 { + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <1>; + qcom,rgmii_delay = <0>; + qcom,emulation = <0>; +}; + +/* LAN */ +&gmac2 { + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,emulation = <0>; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-eax500.dtsi new file mode 100644 index 00000000000..59f6dc8698e --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-eax500.dtsi @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include + +/ { + chosen { + bootargs = "console=ttyMSM0,115200n8"; + /* append to bootargs adding the root deviceblock nbr from bootloader */ + append-rootblock = "ubi.mtd="; + }; +}; + +&qcom_pinmux { + /* eax500 routers reuse the pcie2 reset pin for switch reset pin */ + switch_reset: switch_reset_pins { + mux { + pins = "gpio63"; + function = "gpio"; + drive-strength = <12>; + bias-pull-up; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + max-link-speed = <1>; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_1000>; + nvmem-cell-names = "pre-calibration"; + }; +}; + +&pcie1 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x0c80000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + partition@180000 { + label = "SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + partition@2c0000 { + label = "SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + partition@540000 { + label = "DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + partition@660000 { + label = "SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + partition@780000 { + label = "TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + partition@a00000 { + label = "RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + art: partition@c80000 { + label = "art"; + reg = <0x0c80000 0x0140000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_1000: pre-calibration@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: pre-calibration@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + partition@dc0000 { + label = "APPSBL"; + reg = <0x0dc0000 0x0100000>; + read-only; + }; + + partition@ec0000 { + label = "u_env"; + reg = <0x0ec0000 0x0040000>; + }; + + partition@f00000 { + label = "s_env"; + reg = <0x0f00000 0x0040000>; + }; + + partition@f40000 { + label = "devinfo"; + reg = <0x0f40000 0x0040000>; + + nvmem-layout { + compatible = "ascii-eq-delim-env"; + #address-cells = <1>; + #size-cells = <1>; + + hw_mac_addr: hw_mac_addr { + compatible = "mac-base"; + + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@f80000 { + label = "kernel1"; + reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */ + }; + + partition@1380000 { + label = "rootfs1"; + reg = <0x1380000 0x2400000>; + }; + + partition@3780000 { + label = "kernel2"; + reg = <0x3780000 0x2800000>; + }; + + partition@3b80000 { + label = "rootfs2"; + reg = <0x3b80000 0x2400000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + /* Switch from documentation require at least 10ms for reset */ + reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; + reset-post-delay-us = <12000>; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&hw_mac_addr 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&hw_mac_addr 1>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts new file mode 100644 index 00000000000..813eb050b45 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-smb208.dtsi" +#include +#include + +/ { + model = "Fortinet FAP-421E"; + compatible = "fortinet,fap-421e", "qcom,ipq8064"; + + memory@42000000 { + device_type = "memory"; + reg = <0x42000000 0xe000000>; + }; + + reserved-memory { + rsvd@41200000 { + no-map; + reg = <0x41200000 0x300000>; + }; + wifi_dump@44000000 { + no-map; + reg = <0x44000000 0x600000>; + }; + }; + + aliases { + led-boot = &led_power_yellow; + led-failsafe = &led_power_yellow; + led-running = &led_power_yellow; + led-upgrade = &led_power_yellow; + label-mac-device = &gmac0; + }; + + chosen { + bootargs-override = "console=ttyMSM0,9600n8"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + eth1-amber { + label = "amber:eth1"; + gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>; + }; + + eth1-yellow { + label = "yellow:eth1"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + eth2-amber { + label = "amber:eth2"; + gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>; + }; + + eth2-yellow { + label = "yellow:eth2"; + gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; + }; + + power-amber { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; + }; + + led_power_yellow: power-yellow { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; + }; + + 2g-yellow { + label = "yellow:2g"; + gpios = <&qcom_pinmux 30 GPIO_ACTIVE_LOW>; + }; + + 5g-yellow { + label = "yellow:5g"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + bias-pull-up; + drive-strength = <2>; + pins = "gpio56"; + }; + }; + + led_pins: led_pins { + mux { + bias-pull-down; + drive-strength = <2>; + function = "gpio"; + output-low; + pins = "gpio23"; + }; + }; + + rgmii2_pins: rgmii2-pins { + mux { + bias-disable; + drive-strength = <16>; + function = "rgmii2"; + pins = "gpio66"; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + uart0_pins: uart0_pins { + mux { + bias-disable; + drive-strength = <12>; + function = "gsbi7"; + pins = "gpio6", "gpio7"; + }; + }; + + usb_pwr_en_pins: usb_pwr_en_pins { + mux { + pins = "gpio22"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-low; + }; + }; +}; + +&gsbi7 { + qcom,mode = ; + + status = "okay"; +}; + +&gsbi7_serial{ + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&gsbi5 { + qcom,mode = ; + + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + m25p,fast-read; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x40000 0x40000>; + read-only; + }; + + partition@80000 { + label = "SBL3"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "DDRCONFIG"; + reg = <0x100000 0x10000>; + read-only; + }; + + partition@110000 { + label = "SSD"; + reg = <0x110000 0x10000>; + read-only; + }; + + partition@120000 { + label = "TZ"; + reg = <0x120000 0x80000>; + read-only; + }; + + partition@1a0000 { + label = "RPM"; + reg = <0x1a0000 0x80000>; + read-only; + }; + + partition@220000 { + label = "APPSBL"; + reg = <0x220000 0x80000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_appsbl_7ff80: mac-address@7ff80 { + compatible = "mac-base"; + reg = <0x7ff80 0xc>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@2a0000 { + label = "APPSBLENV"; + reg = <0x2a0000 0x40000>; + }; + + partition@2e0000 { + label = "ART"; + reg = <0x2e0000 0x40000>; + read-only; + }; + + partition@320000 { + label = "kernel"; + reg = <0x320000 0x600000>; + }; + + partition@920000 { + label = "ubi"; + reg = <0x920000 0x1400000>; + }; + + partition@1d20000 { + label = "reserved"; + reg = <0x1d20000 0x260000>; + read-only; + }; + + partition@1f80000 { + label = "config"; + reg = <0x1f80000 0x80000>; + read-only; + }; + }; + }; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_appsbl_7ff80 8>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&pcie1 { + status = "okay"; + + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_appsbl_7ff80 16>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + #address-cells = <0x1>; + #size-cells = <0x0>; + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, + <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; +}; + +&gmac0 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <0>; + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + nvmem-cells = <&macaddr_appsbl_7ff80 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + nvmem-cells = <&macaddr_appsbl_7ff80 1>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-g10.dts new file mode 100644 index 00000000000..24273291cb1 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-g10.dts @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include +#include + +/ { + compatible = "asrock,g10", "qcom,ipq8064"; + model = "ASRock G10"; + + aliases { + ethernet0 = &gmac1; + ethernet1 = &gmac0; + + led-boot = &led_status_blue; + led-failsafe = &led_status_amber; + led-running = &led_status_blue; + led-upgrade = &led_status_amber; + }; + + chosen { + bootargs-override = "console=ttyMSM0,115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + /* + * this is a bit misleading. Because there are about seven + * multicolor LEDs connected all wired together in parallel. + */ + + status_yellow { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + led_status_amber: status_amber { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: status_blue { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + /* + * LED is declared in vendors boardfile but it's not + * working and the manual doesn't mention anything + * about the LED being white. + + status_white { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + */ + }; + + i2c-gpio { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */ + <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <5>; + i2c-gpio,scl-output-only; + + mcu@50 { + reg = <0x50>; + compatible = "sonix,sn8f25e21"; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + ir-remote { + label = "ir-remote"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps5g { + label = "wps5g"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps2g { + label = "wps2g"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x1200000>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi5g: wifi@1,0 { + reg = <0x00010000 0 0 0 0>; + compatible = "qcom,ath10k"; + qcom,ath10k-calibration-variant = "ASRock-G10"; + }; + }; +}; + +&pcie1 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi2g: wifi@1,0 { + reg = <0x00010000 0 0 0 0>; + compatible = "qcom,ath10k"; + qcom,ath10k-calibration-variant = "ASRock-G10"; + }; + }; +}; + +&qcom_pinmux { + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio15", "gpio16", "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; +}; + +&rpm { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&tcsr { + qcom,usb-ctrl-select = ; +}; + +/delete-node/ &pcie2_pins; +/delete-node/ &pcie2; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi new file mode 100644 index 00000000000..5b8de27ad69 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2014 The ChromiumOS Authors + */ + +#include "qcom-ipq8064-smb208.dtsi" +#include +#include +#include + +/ { + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac2; + mdio-gpio0 = &mdio; + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + dev { + label = "dev"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + mdio: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, + <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + }; + }; + }; + + soc { + rng@1a500000 { + status = "disabled"; + }; + + sound { + compatible = "google,storm-audio"; + qcom,model = "ipq806x-storm"; + cpu = <&lpass>; + codec = <&max98357a>; + }; + + lpass: lpass@28100000 { + status = "okay"; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&mi2s_default>; + pinctrl-1 = <&mi2s_idle>; + }; + + max98357a: max98357a { + compatible = "maxim,max98357a"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmode_pins>; + sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + rgmii0_pins: rgmii0_pins { + mux { + pins = "gpio2", "gpio66"; + drive-strength = <8>; + bias-disable; + }; + }; + mi2s_pins { + mi2s_default: mi2s_default { + dout { + pins = "gpio32"; + function = "mi2s"; + drive-strength = <16>; + bias-disable; + }; + sync { + pins = "gpio27"; + function = "mi2s"; + drive-strength = <16>; + bias-disable; + }; + clk { + pins = "gpio28"; + function = "mi2s"; + drive-strength = <16>; + bias-disable; + }; + }; + mi2s_idle: mi2s_idle { + dout { + pins = "gpio32"; + function = "mi2s"; + drive-strength = <2>; + bias-pull-down; + }; + sync { + pins = "gpio27"; + function = "mi2s"; + drive-strength = <2>; + bias-pull-down; + }; + clk { + pins = "gpio28"; + function = "mi2s"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + mdio_pins: mdio_pins { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + rst { + pins = "gpio26"; + output-low; + }; + }; + + sdmode_pins: sdmode_pinmux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sdcc1_pins: sdcc1_pinmux { + mux { + pins = "gpio38", "gpio39", "gpio40", + "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", + "gpio47"; + function = "sdc1"; + }; + cmd { + pins = "gpio45"; + drive-strength = <10>; + bias-pull-up; + }; + data { + pins = "gpio38", "gpio39", "gpio40", + "gpio41", "gpio43", "gpio44", + "gpio46", "gpio47"; + drive-strength = <10>; + bias-pull-up; + }; + clk { + pins = "gpio42"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + i2c1_pins: i2c1_pinmux { + pins = "gpio53", "gpio54"; + function = "gsbi1"; + bias-disable; + }; + + rpm_i2c_pinmux: rpm_i2c_pinmux { + mux { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + /delete-property/ bias-none; + /delete-property/ drive-strength; + }; + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + fw_pinmux { + wp { + pins = "gpio17"; + output-low; + }; + }; + + button_pins: button_pins { + recovery { + pins = "gpio16"; + function = "gpio"; + bias-none; + }; + developer { + pins = "gpio15"; + function = "gpio"; + bias-none; + }; + }; + + spi6_pins: spi6_pins { + mux { + pins = "gpio55", "gpio56", "gpio58"; + function = "gsbi6"; + bias-pull-down; + }; + data { + pins = "gpio55", "gpio56"; + drive-strength = <10>; + }; + cs { + pins = "gpio57"; + drive-strength = <10>; + bias-pull-up; + output-high; + }; + clk { + pins = "gpio58"; + drive-strength = <12>; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + pinctrl-0 = <&rgmii0_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi1 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi1_i2c { + status = "okay"; + + clock-frequency = <100000>; + + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +&gsbi4 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi4_serial { + status = "okay"; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 0>; + + flash: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; +}; + +&gsbi6 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi6_spi { + status = "okay"; + spi-max-frequency = <25000000>; + + pinctrl-0 = <&spi6_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; + + dmas = <&adm_dma 8 0xb>, + <&adm_dma 7 0x14>; + dma-names = "rx", "tx"; + + /* + * This "spidev" was included in the manufacturer device tree. I suspect + * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's + * no driver or binding for this at the moment. + */ + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&pcie0 { + status = "okay"; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupt-controller; + + ath10k@0,0 { + reg = <0 0 0 0 0>; + device_type = "pci"; + qcom,ath10k-sa-gpio = <2 3 4 0>; + qcom,ath10k-sa-gpio-func = <5 5 5 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupt-controller; + + ath10k@0,0 { + reg = <0 0 0 0 0>; + device_type = "pci"; + qcom,ath10k-sa-gpio = <2 3 4 0>; + qcom,ath10k-sa-gpio-func = <5 5 5 0>; + }; + }; +}; + +&pcie2 { + status = "okay"; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupt-controller; + + ath10k@0,0 { + reg = <0 0 0 0 0>; + device_type = "pci"; + }; + }; +}; + +&rpm { + pinctrl-0 = <&rpm_i2c_pinmux>; + pinctrl-names = "default"; +}; + +&sdcc1 { + status = "okay"; + pinctrl-0 = <&sdcc1_pins>; + pinctrl-names = "default"; + /delete-property/ mmc-ddr-1_8v; +}; + +&tcsr { + compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon"; + qcom,usb-ctrl-select = ; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500.dts new file mode 100644 index 00000000000..c2703b05d78 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500.dts @@ -0,0 +1,415 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +#include +#include +#include + +/ { + model = "Netgear Nighthawk X4 R7500"; + compatible = "netgear,r7500", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0xe000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + power_amber: power_amber { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power_white: power_white { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + status = "disabled"; + + spi@1a280000 { + status = "disabled"; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; + }; + + kernel@1340000 { + label = "kernel"; + reg = <0x1340000 0x0400000>; + }; + + ubi@1740000 { + label = "ubi"; + reg = <0x1740000 0x1600000>; + }; + + netgear@2d40000 { + label = "netgear"; + reg = <0x2d40000 0x0c00000>; + read-only; + }; + + reserve@3940000 { + label = "reserve"; + reg = <0x3940000 0x46c0000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&tcsr { + qcom,usb-ctrl-select = ; + compatible = "qcom,tcsr"; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500v2.dts new file mode 100644 index 00000000000..469cdaa0a2f --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500v2.dts @@ -0,0 +1,477 @@ +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include + +/ { + model = "Netgear Nighthawk X4 R7500v2"; + compatible = "netgear,r7500v2", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "amber:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb3 { + label = "amber:usb3"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + status { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + internet { + label = "white:internet"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + compatible = "mac-base"; + reg = <0x6 0x6>; + #nvmem-cell-cells = <1>; + }; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + artbak: art@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + kernel@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + + ubi@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + reserve@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-tplink-onhub.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-tplink-onhub.dts new file mode 100644 index 00000000000..9fa0ff18583 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-tplink-onhub.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2014 The ChromiumOS Authors + */ + +#include "qcom-ipq8064-onhub.dtsi" +#include +#include +#include + +/ { + model = "TP-Link OnHub"; + compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064"; +}; + +&qcom_pinmux { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + /* RECOVERY_SW_L is crossystem ABI. */ + "RECOVERY_SW_L", /* 16 */ + /* AP_FLASH_WP_L is crossystem ABI. */ + "AP_FLASH_WP_L" /* 17 */; + + i2c7_pins: i2c7_pinmux { + mux { + pins = "gpio8", "gpio9"; + function = "gsbi7"; + }; + data { + pins = "gpio8"; + bias-disable; + }; + clk { + pins = "gpio9"; + bias-disable; + }; + }; +}; + +&gsbi7 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi7_i2c { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + + led-controller@32 { + compatible = "national,lp5523"; + reg = <0x32>; + clock-mode = /bits/ 8 <1>; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + chan-name = "red:status-0"; + linux,default-trigger = "default-on"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@1 { + reg = <1>; + color = ; + chan-name = "green:status-0"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@2 { + reg = <2>; + color = ; + chan-name = "blue:status-0"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@3 { + reg = <3>; + color = ; + chan-name = "red:status-1"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@4 { + reg = <4>; + color = ; + chan-name = "green:status-1"; + linux,default-trigger = "default-on"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@5 { + reg = <5>; + color = ; + chan-name = "blue:status-1"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@6 { + reg = <6>; + color = ; + chan-name = "red:status-2"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@7 { + reg = <7>; + color = ; + chan-name = "green:status-2"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@8 { + reg = <8>; + color = ; + chan-name = "blue:status-2"; + linux,default-trigger = "default-on"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + }; + + led-controller@33 { + compatible = "national,lp5523"; + reg = <0x33>; + clock-mode = /bits/ 8 <1>; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + chan-name = "red:status-3"; + linux,default-trigger = "default-on"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@1 { + reg = <1>; + color = ; + chan-name = "green:status-3"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@2 { + reg = <2>; + color = ; + chan-name = "blue:status-3"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@3 { + reg = <3>; + color = ; + chan-name = "red:status-4"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@4 { + reg = <4>; + color = ; + chan-name = "green:status-4"; + linux,default-trigger = "default-on"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@5 { + reg = <5>; + color = ; + chan-name = "blue:status-4"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@6 { + reg = <6>; + color = ; + chan-name = "red:status-5"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@7 { + reg = <7>; + color = ; + chan-name = "green:status-5"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + + led@8 { + reg = <8>; + color = ; + chan-name = "blue:status-5"; + linux,default-trigger = "default-on"; + led-cur = /bits/ 8 <0x64>; + max-cur = /bits/ 8 <0x78>; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-unifi-ac-hd.dts new file mode 100644 index 00000000000..c415b5901ad --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-unifi-ac-hd.dts @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include + +/ { + model = "Ubiquiti UniFi AC HD"; + compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064"; + + aliases { + label-mac-device = &gmac2; + led-boot = &led_dome_white; + led-failsafe = &led_dome_white; + led-running = &led_dome_blue; + led-upgrade = &led_dome_blue; + mdio-gpio0 = &mdio0; + ethernet0 = &gmac2; + ethernet1 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_dome_blue: dome_blue { + label = "blue:dome"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + led_dome_white: dome_white { + label = "white:dome"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio9", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; +}; + +&CPU_SPC { + status = "disabled"; +}; + +&gsbi5 { + status = "okay"; + + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + cs-gpios = <&qcom_pinmux 20 0>; + + flash@0 { + compatible = "mx25u25635f", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "SBL2"; + reg = <0x30000 0x20000>; + read-only; + }; + + partition@50000 { + label = "SBL3"; + reg = <0x50000 0x30000>; + read-only; + }; + + partition@80000 { + label = "DDRCONFIG"; + reg = <0x80000 0x10000>; + read-only; + }; + + partition@90000 { + label = "SSD"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "TZ"; + reg = <0xa0000 0x30000>; + read-only; + }; + + partition@d0000 { + label = "RPM"; + reg = <0xd0000 0x20000>; + read-only; + }; + + partition@f0000 { + label = "APPSBL"; + reg = <0xf0000 0xc0000>; + read-only; + }; + + partition@1b0000 { + label = "APPSBLENV"; + reg = <0x1b0000 0x10000>; + read-only; + }; + + eeprom: partition@1c0000 { + label = "EEPROM"; + reg = <0x1c0000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + compatible = "mac-base"; + reg = <0x6 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@1d0000 { + label = "bootselect"; + reg = <0x1d0000 0x10000>; + }; + + partition@1e0000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x1e0000 0xe70000>; + }; + + partition@1050000 { + label = "kernel1"; + reg = <0x1050000 0xe70000>; + read-only; + }; + + partition@1ec0000 { + label = "debug"; + reg = <0x1ec0000 0x100000>; + read-only; + }; + + partition@1fc0000 { + label = "cfg"; + reg = <0x1fc0000 0x40000>; + read-only; + }; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + }; +}; + +&gmac1 { + status = "okay"; + + mdiobus = <&mdio0>; + phy-handle = <&phy5>; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_eeprom_6 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + status = "okay"; + + mdiobus = <&mdio0>; + phy-handle = <&phy4>; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; + +&pcie0 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&macaddr_eeprom_6 1>; + nvmem-cell-names = "mac-address"; + }; +}; + +&pcie1 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&macaddr_eeprom_6 2>; + nvmem-cell-names = "mac-address"; + }; +}; + +&tcsr { + status = "okay"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-vr2600v.dts new file mode 100644 index 00000000000..3df650eba4d --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-vr2600v.dts @@ -0,0 +1,515 @@ +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include + +/ { + model = "TP-Link Archer VR2600v"; + compatible = "tplink,vr2600v", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power; + led-failsafe = &general; + led-running = &power; + led-upgrade = &general; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + dect { + label = "dect"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ledswitch { + label = "ledswitch"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + dsl { + label = "white:dsl"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb { + function = LED_FUNCTION_USB; + color = ; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wlan2g { + label = "white:wlan2g"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan5g { + label = "white:wlan5g"; + gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; + }; + + power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + phone { + label = "white:phone"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + wan { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + general: general { + label = "white:general"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", + "gpio26", "gpio53", "gpio56", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x40000 0x40000>; + read-only; + }; + + partition@80000 { + label = "SBL3"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "DDRCONFIG"; + reg = <0x100000 0x10000>; + read-only; + }; + + partition@110000 { + label = "SSD"; + reg = <0x110000 0x10000>; + read-only; + }; + + partition@120000 { + label = "TZ"; + reg = <0x120000 0x80000>; + read-only; + }; + + partition@1a0000 { + label = "RPM"; + reg = <0x1a0000 0x80000>; + read-only; + }; + + partition@220000 { + label = "APPSBL"; + reg = <0x220000 0x80000>; + read-only; + }; + + partition@2a0000 { + label = "APPSBLENV"; + reg = <0x2a0000 0x40000>; + read-only; + }; + + partition@2e0000 { + label = "OLDART"; + reg = <0x2e0000 0x40000>; + read-only; + }; + + partition@320000 { + label = "firmware"; + reg = <0x320000 0xc60000>; + compatible = "openwrt,uimage"; + openwrt,offset = <512>; /* account for pad-extra 512 */ + }; + + /* hole 0xf80000 - 0xfaf100 */ + + partition@faf100 { + label = "default-mac"; + reg = <0xfaf100 0x00200>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_defaultmac_0: macaddr@0 { + compatible = "mac-base"; + reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@fc0000 { + label = "ART"; + reg = <0xfc0000 0x40000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + }; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_0 (-1)>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_0 0>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_defaultmac_0 1>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_defaultmac_0 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wg2600hp.dts new file mode 100644 index 00000000000..b97b4325f21 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wg2600hp.dts @@ -0,0 +1,552 @@ +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include + +/ { + model = "NEC Aterm WG2600HP"; + compatible = "nec,wg2600hp", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + bridge { + label = "bridge"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + converter { + label = "converter"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + converter_green { + label = "green:converter"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; + }; + + power_red: power_red { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + active_green { + label = "green:active"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + active_red { + label = "red:active"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + power_green: power_green { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; + }; + + converter_red { + label = "red:converter"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_red { + label = "red:wlan2g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_red { + label = "red:wlan5g"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; + }; + + tv_green { + label = "green:tv"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + tv_red { + label = "red:tv"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&CPU_SPC { + status = "disabled"; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + +switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-rxclk-falling-edge; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_PRODUCTDATA_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_PRODUCTDATA_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi5 { + status = "okay"; + + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + MIBIB@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + SBL2@40000 { + label = "SBL2"; + reg = <0x40000 0x40000>; + read-only; + }; + + SBL3@80000 { + label = "SBL3"; + reg = <0x80000 0x80000>; + read-only; + }; + + DDRCONFIG@100000 { + label = "DDRCONFIG"; + reg = <0x100000 0x10000>; + read-only; + }; + + SSD@110000 { + label = "SSD"; + reg = <0x110000 0x10000>; + read-only; + }; + + TZ@120000 { + label = "TZ"; + reg = <0x120000 0x80000>; + read-only; + }; + + RPM@1a0000 { + label = "RPM"; + reg = <0x1a0000 0x80000>; + read-only; + }; + + APPSBL@220000 { + label = "APPSBL"; + reg = <0x220000 0x80000>; + read-only; + }; + + APPSBLENV@2a0000 { + label = "APPSBLENV"; + reg = <0x2a0000 0x10000>; + }; + + PRODUCTDATA: PRODUCTDATA@2b0000 { + label = "PRODUCTDATA"; + reg = <0x2b0000 0x30000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_PRODUCTDATA_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_PRODUCTDATA_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_PRODUCTDATA_c: macaddr@c { + reg = <0xc 0x6>; + }; + + macaddr_PRODUCTDATA_12: macaddr@12 { + reg = <0x12 0x6>; + }; + }; + }; + + ART@2e0000 { + label = "ART"; + reg = <0x2e0000 0x40000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + TP@320000 { + label = "TP"; + reg = <0x320000 0x40000>; + read-only; + }; + + TINY@360000 { + label = "TINY"; + reg = <0x360000 0x500000>; + read-only; + }; + + firmware@860000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x860000 0x17a0000>; + }; + }; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio16", "gpio54", "gpio24", "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", + "gpio15", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb_pwr_en_pins: usb_pwr_en_pins { + mux { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-high; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wpq864.dts new file mode 100644 index 00000000000..0fb7e0531d5 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wpq864.dts @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2017 Christian Mehlis + * Copyright (C) 2018 Mathias Kresin + * All rights reserved. + */ + +#include "qcom-ipq8064-v1.0.dtsi" + +#include +#include +#include + +/ { + compatible = "compex,wpq864", "qcom,ipq8064"; + model = "Compex WPQ864"; + + aliases { + mdio-gpio0 = &mdio0; + ethernet0 = &gmac1; + ethernet1 = &gmac0; + + led-boot = &led_pass; + led-failsafe = &led_fail; + led-running = &led_pass; + led-upgrade = &led_pass; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + rss4 { + label = "green:rss4"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + rss3 { + label = "green:rss3"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rss2 { + label = "orange:rss2"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; + }; + + rss1 { + label = "red:rss1"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + led_pass: pass { + label = "green:pass"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + led_fail: fail { + label = "green:fail"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + usb { + function = LED_FUNCTION_USB; + color = ; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb-pcie { + label = "green:usb-pcie"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + beeper { + compatible = "gpio-beeper"; + + pinctrl-0 = <&beeper_pins>; + pinctrl-names = "default"; + + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; +}; + +&rpm { + pinctrl-0 = <&rpm_pins>; + pinctrl-names = "default"; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + mt29f2g08abbeah4@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "0:MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + partition@180000 { + label = "0:SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + partition@2c0000 { + label = "0:SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + partition@540000 { + label = "0:DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + partition@660000 { + label = "0:SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + partition@780000 { + label = "0:TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + partition@a00000 { + label = "0:RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + partition@c80000 { + label = "0:APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + partition@1180000 { + label = "0:APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + + partition@1200000 { + label = "0:ART"; + reg = <0x1200000 0x0140000>; + }; + + partition@1340000 { + label = "ubi"; + reg = <0x1340000 0x4000000>; + }; + + partition@5340000 { + label = "0:BOOTCONFIG"; + reg = <0x5340000 0x0060000>; + }; + + partition@53a0000 { + label = "0:SBL2_1"; + reg = <0x53a0000 0x0140000>; + read-only; + }; + + partition@54e0000 { + label = "0:SBL3_1"; + reg = <0x54e0000 0x0280000>; + read-only; + }; + + partition@5760000 { + label = "0:DDRCONFIG_1"; + reg = <0x5760000 0x0120000>; + read-only; + }; + + partition@5880000 { + label = "0:SSD_1"; + reg = <0x5880000 0x0120000>; + read-only; + }; + + partition@59a0000 { + label = "0:TZ_1"; + reg = <0x59a0000 0x0280000>; + read-only; + }; + + partition@5c20000 { + label = "0:RPM_1"; + reg = <0x5c20000 0x0280000>; + read-only; + }; + + partition@5ea0000 { + label = "0:BOOTCONFIG1"; + reg = <0x5ea0000 0x0060000>; + }; + + partition@5f00000 { + label = "0:APPSBL_1"; + reg = <0x5f00000 0x0500000>; + read-only; + }; + + partition@6400000 { + label = "ubi_1"; + reg = <0x6400000 0x4000000>; + }; + + partition@a400000 { + label = "unused"; + reg = <0xa400000 0x5c00000>; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&flash { + compatible = "jedec,spi-nor"; +}; + +&sata_phy { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; + + rx_eq = <2>; + tx_deamp_3_5db = <32>; + mpll = <160>; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; + + rx_eq = <2>; + tx_deamp_3_5db = <32>; + mpll = <160>; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; +}; + +&qcom_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinctrl0 { + pcie0_pcie2_perst { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + beeper_pins: beeper_pins { + mux { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rpm_pins: rpm_pins { + mux { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; +}; + +&tcsr { + qcom,usb-ctrl-select = ; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wxr-2533dhp.dts new file mode 100644 index 00000000000..b3561cafe76 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wxr-2533dhp.dts @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include + +/ { + model = "Buffalo WXR-2533DHP"; + compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064"; + + memory@42000000 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &power; + led-failsafe = &diag; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + /* use "ubi_rootfs" volume in "ubi" partition as rootfs */ + bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb { + function = LED_FUNCTION_USB; + color = ; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port0 &hub_port1>; + }; + + guestport { + label = "green:guestport"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + diag: diag { + label = "orange:diag"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + internet_orange { + label = "orange:internet"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + internet_white { + label = "white:internet"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wireless_orange { + label = "orange:wireless"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wireless_white { + label = "white:wireless"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + router_orange { + label = "orange:router"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; + }; + + router_white { + label = "white:router"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + power { + label = "power"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + eject { + label = "eject"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + guest { + label = "guest"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ap { + label = "ap"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + router { + label = "router"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + auto { + label = "auto"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&nand { + status = "okay"; + + cs@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubi@0 { + label = "ubi"; + reg = <0x0000000 0x4000000>; + }; + + rootfs_1@4000000 { + label = "rootfs_1"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_ART_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_ART_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0 0x10000>; + read-only; + }; + + MIBIB@10000 { + label = "MIBIB"; + reg = <0x10000 0x20000>; + read-only; + }; + + SBL2@30000 { + label = "SBL2"; + reg = <0x30000 0x30000>; + read-only; + }; + + SBL3@60000 { + label = "SBL3"; + reg = <0x60000 0x30000>; + read-only; + }; + + DDRCONFIG@90000 { + label = "DDRCONFIG"; + reg = <0x90000 0x10000>; + read-only; + }; + + SSD@a0000 { + label = "SSD"; + reg = <0xa0000 0x10000>; + read-only; + }; + + TZ@b0000 { + label = "TZ"; + reg = <0xb0000 0x30000>; + read-only; + }; + + RPM@e0000 { + label = "RPM"; + reg = <0xe0000 0x20000>; + read-only; + }; + + APPSBL@100000 { + label = "APPSBL"; + reg = <0x100000 0x70000>; + read-only; + }; + + APPSBLENV@170000 { + label = "APPSBLENV"; + reg = <0x170000 0x10000>; + read-only; + }; + + ART@180000 { + label = "ART"; + reg = <0x180000 0x40000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ART_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_ART_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_ART_18: macaddr@18 { + reg = <0x18 0x6>; + }; + + macaddr_ART_1e: macaddr@1e { + reg = <0x1e 0x6>; + }; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + BOOTCONFIG@1c0000 { + label = "BOOTCONFIG"; + reg = <0x1c0000 0x10000>; + read-only; + }; + + APPSBL_1@1d0000 { + label = "APPSBL_1"; + reg = <0x1d0000 0x70000>; + read-only; + }; + }; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&dwc3_0 { + #address-cells = <1>; + #size-cells = <0>; + + hub_port0: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio58", "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs{ + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb_pwr_en_pins: usb_pwr_en_pins { + mux{ + pins = "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-ac400i.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-ac400i.dts new file mode 100644 index 00000000000..7151f8de525 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-ac400i.dts @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8065-smb208.dtsi" +#include + +/ { + model = "Nokia AC400i"; + compatible = "nokia,ac400i", "qcom,ipq8065", "qcom,ipq8064"; + + aliases { + mdio-gpio0 = &mdio0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + + led-boot = &pwr_red; + led-failsafe = &pwr_red; + led-running = &pwr_green; + led-upgrade = &pwr_green; + }; + + chosen { + bootargs-override = " console=ttyMSM0,115200n8 ubi.mtd=ubi root=/dev/ubiblock0_2"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + 5g_red { + label = "red:5g"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; + }; + + 5g_green { + label = "green:5g"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + 2g_red { + label = "red:2g"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + 2g_green { + label = "green:2g"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; + }; + + eth1_red { + label = "red:eth1"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>; + }; + + eth1_green { + label = "green:eth1"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; + }; + + eth2_red { + label = "red:eth2"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_HIGH>; + }; + + eth2_green { + label = "green:eth2"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; + }; + + ctrl_red { + label = "red:ctrl"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; + + ctrl_green { + label = "green:ctrl"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + pwr_red: pwr_red { + label = "red:pwr"; + gpios = <&qcom_pinmux 2 GPIO_ACTIVE_LOW>; + }; + + pwr_green: pwr_green { + label = "green:pwr"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio65", "gpio64", + "gpio53", "gpio54", + "gpio68", "gpio22", + "gpio67", "gpio23", + "gpio55", "gpio56", + "gpio2", "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Nokia-AC400i"; + }; + }; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Nokia-AC400i"; + }; + }; +}; + +&mdio0 { + status = "okay"; + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + +}; + +//POE +&gmac0 { + status = "okay"; + qcom,id = <0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + mdiobus = <&mdio0>; + phy-handle = <&phy0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +//LAN1 +&gmac1 { + status = "okay"; + qcom,id = <1>; + + mdiobus = <&mdio0>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + rootfs@0 { + label = "rootfs"; + reg = <0x0000000 0x4000000>; + }; + + rootfs_1@4000000 { + label = "rootfs_1"; + reg = <0x4000000 0x4000000>; + }; + + cfg@8000000 { + label = "cfg"; + reg = <0x8000000 0x8000000>; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-nbg6817.dts new file mode 100644 index 00000000000..9a9251e9b95 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-nbg6817.dts @@ -0,0 +1,395 @@ +#include "qcom-ipq8065-smb208.dtsi" + +#include +#include + +/ { + model = "Zyxel NBG6817"; + compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + sdcc1 = &sdcc1; + + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1"; + append-rootblock = "root=/dev/mmcblk0p"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + internet { + label = "white:internet"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi2g { + label = "amber:wifi2g"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; + }; + + /* wifi2g amber from the manual is missing */ + + wifi5g { + label = "amber:wifi5g"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + /* wifi5g amber from the manual is missing */ + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio53", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio9", "gpio26", "gpio33", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + mdio0_pins: mdio0-pins { + clk { + pins = "gpio1"; + input-disable; + }; + }; + + rgmii2_pins: rgmii2-pins { + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; + input-disable; + }; + }; + + spi_pins: spi_pins { + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <12>; + }; + + pwr { + pins = "gpio17"; + bias-pull-down; + output-high; + }; + + ovc { + pins = "gpio16"; + bias-pull-up; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <12>; + }; + + pwr { + pins = "gpio14"; + bias-pull-down; + output-high; + }; + + ovc { + pins = "gpio15"; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <51200000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie1 { + status = "okay"; + reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <0>; + qcom,rgmii_delay = <1>; + qcom,phy_mii_type = <0>; + qcom,emulation = <0>; + qcom,irq = <255>; + mdiobus = <&mdio0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,phy_mii_type = <1>; + qcom,emulation = <0>; + qcom,irq = <258>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&sdcc1 { + status = "okay"; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-nighthawk.dtsi new file mode 100644 index 00000000000..a2d916faaf4 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-nighthawk.dtsi @@ -0,0 +1,541 @@ +#include "qcom-ipq8065-smb208.dtsi" + +#include +#include + +/ { + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + + ramoops@42100000 { + compatible = "ramoops"; + reg = <0x42100000 0x40000>; + record-size = <0x4000>; + console-size = <0x4000>; + ftrace-size = <0x4000>; + pmsg-size = <0x4000>; + }; + }; + + aliases { + label-mac-device = &gmac2; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + + mdio-gpio0 = &mdio0; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + power_white: power_white { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + power_amber: power_amber { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", + "gpio22", "gpio23", "gpio24", + "gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + mdio0_pins: mdio0-pins { + clk { + pins = "gpio1"; + input-disable; + }; + }; + + rgmii2_pins: rgmii2-pins { + tx { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + spi6_pins: spi6_pins { + mux { + pins = "gpio55", "gpio56", "gpio58"; + function = "gsbi6"; + bias-pull-down; + }; + + mosi { + pins = "gpio55"; + drive-strength = <12>; + }; + + miso { + pins = "gpio56"; + drive-strength = <14>; + }; + + cs { + pins = "gpio57"; + drive-strength = <12>; + bias-pull-up; + }; + + clk { + pins = "gpio58"; + drive-strength = <12>; + }; + + reset { + pins = "gpio33"; + drive-strength = <10>; + bias-pull-down; + output-high; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x1180000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + partition@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + partition@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: partition@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + compatible = "mac-base"; + reg = <0x6 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + partition@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + partition@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <0>; + qcom,rgmii_delay = <1>; + qcom,phy_mii_type = <0>; + qcom,emulation = <0>; + qcom,irq = <255>; + mdiobus = <&mdio0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,phy_mii_type = <1>; + qcom,emulation = <0>; + qcom,irq = <258>; + mdiobus = <&mdio0>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-r7800.dts new file mode 100644 index 00000000000..3440c52699e --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-r7800.dts @@ -0,0 +1,46 @@ +#include "qcom-ipq8065-nighthawk.dtsi" + +/ { + model = "Netgear Nighthawk X4S R7800"; + compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064"; +}; + +&leds { + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&partitions { + partition@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + partition@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; +}; + +&wifi0 { + nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; + +&wifi1 { + nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts new file mode 100644 index 00000000000..cd63f92db65 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts @@ -0,0 +1,602 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "qcom-ipq8065-smb208.dtsi" +#include +#include + +/ { + model = "Askey RT4230W REV6"; + compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x3e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &ledctrl1; + led-failsafe = &ledctrl1; + led-running = &ledctrl3; + led-upgrade = &ledctrl1; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + ledctrl1: ledctrl1 { + label = "ledctrl1"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + ledctrl2: ledctrl2 { + label = "ledctrl2"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + ledctrl3: ledctrl3 { + label = "ledctrl3"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio54", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio22", "gpio23", "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + rgmii2_pins: rgmii2-pins { + mux { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; + }; + + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; + + spi_pins: spi_pins { + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "everspin,mr25h256"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "0:MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + partition@180000 { + label = "0:SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + partition@2c0000 { + label = "0:SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + partition@540000 { + label = "0:DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + partition@660000 { + label = "0:SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + partition@780000 { + label = "0:TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + partition@a00000 { + label = "0:RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + partition@c80000 { + label = "0:APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + partition@1180000 { + label = "0:APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + + partition@1200000 { + label = "0:ART"; + reg = <0x1200000 0x0140000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ART_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_ART_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + + partition@1340000 { + label = "0:BOOTCONFIG"; + reg = <0x1340000 0x0060000>; + read-only; + }; + + partition@13a0000 { + label = "0:SBL2_1"; + reg = <0x13a0000 0x0140000>; + read-only; + }; + + partition@14e0000 { + label = "0:SBL3_1"; + reg = <0x14e0000 0x0280000>; + read-only; + }; + + partition@1760000 { + label = "0:DDRCONFIG_1"; + reg = <0x1760000 0x0120000>; + read-only; + }; + + partition@1880000 { + label = "0:SSD_1"; + reg = <0x1880000 0x0120000>; + read-only; + }; + + partition@19a0000 { + label = "0:TZ_1"; + reg = <0x19a0000 0x0280000>; + read-only; + }; + + partition@1c20000 { + label = "0:RPM_1"; + reg = <0x1c20000 0x0280000>; + read-only; + }; + + partition@1ea0000 { + label = "0:BOOTCONFIG1"; + reg = <0x1ea0000 0x0060000>; + read-only; + }; + + partition@1f00000 { + label = "0:APPSBL_1"; + reg = <0x1f00000 0x0500000>; + read-only; + }; + + partition@2400000 { + label = "ubi"; + reg = <0x2400000 0x1a000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; + }; + + port@2 { + reg = <2>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@4 { + reg = <4>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + }; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + nvmem-cells = <&macaddr_ART_0>; + nvmem-cell-names = "mac-address"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_ART_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_1000>; + nvmem-cell-names = "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_5000>; + nvmem-cell-names = "pre-calibration"; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-tr4400-v2.dts new file mode 100644 index 00000000000..176ae293376 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-tr4400-v2.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "qcom-ipq8065-smb208.dtsi" +#include +#include + +/ { + model = "Arris TR4400 v2"; + compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &led_status_blue; + led-failsafe = &led_status_red; + led-running = &led_status_blue; + led-upgrade = &led_status_red; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_status_red: status_red { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: status_blue { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + rgmii2_pins: rgmii2-pins { + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; + + spi_pins: spi_pins { + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "everspin,mr25h256"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + partition@40000 { + label = "0:MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + partition@180000 { + label = "0:SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + partition@2c0000 { + label = "0:SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + partition@540000 { + label = "0:DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + partition@660000 { + label = "0:SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + partition@780000 { + label = "0:TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + partition@a00000 { + label = "0:RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + partition@c80000 { + label = "0:APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + partition@1180000 { + label = "0:APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + partition@1200000 { + label = "0:ART"; + reg = <0x1200000 0x0140000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + partition@1340000 { + label = "extra"; + reg = <0x1340000 0x4000000>; + }; + partition@5340000 { + label = "0:BOOTCONFIG"; + reg = <0x5340000 0x0060000>; + read-only; + }; + partition@53a0000 { + label = "0:SBL2_1"; + reg = <0x53a0000 0x0140000>; + read-only; + }; + partition@54e0000 { + label = "0:SBL3_1"; + reg = <0x54e0000 0x0280000>; + read-only; + }; + partition@5760000 { + label = "0:DDRCONFIG_1"; + reg = <0x5760000 0x0120000>; + read-only; + }; + partition@5880000 { + label = "0:SSD_1"; + reg = <0x5880000 0x0120000>; + read-only; + }; + partition@59a0000 { + label = "0:TZ_1"; + reg = <0x59a0000 0x0280000>; + read-only; + }; + partition@5c20000 { + label = "0:RPM_1"; + reg = <0x5c20000 0x0280000>; + read-only; + }; + partition@5ea0000 { + label = "0:BOOTCONFIG1"; + reg = <0x5ea0000 0x0060000>; + read-only; + }; + partition@5f00000 { + label = "0:APPSBL_1"; + reg = <0x5f00000 0x0500000>; + read-only; + }; + partition@6400000 { + label = "fw_env"; + reg = <0x6400000 0x0100000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_fw_env_0: macaddr@0 { + reg = <0x00 0x6>; + }; + macaddr_fw_env_6: macaddr@6 { + reg = <0x06 0x6>; + }; + macaddr_fw_env_c: macaddr@c { + reg = <0x0c 0x6>; + }; + macaddr_fw_env_12: macaddr@12 { + reg = <0x12 0x6>; + }; + macaddr_fw_env_18: macaddr@18 { + reg = <0x18 0x6>; + }; + }; + }; + partition@6500000 { + label = "ubi"; + reg = <0x6500000 0x9b00000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <1000>; + rx-internal-delay-ps = <1000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + }; + }; + + phy7: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + nvmem-cells = <&macaddr_fw_env_18>; + nvmem-cell-names = "mac-address"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_fw_env_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac3 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <3>; + phy-handle = <&phy7>; + + nvmem-cells = <&macaddr_fw_env_6>; + nvmem-cell-names = "mac-address"; +}; + +&adm_dma { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-xr450.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-xr450.dts new file mode 100644 index 00000000000..1d4e9d36fe4 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-xr450.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8065-nighthawk.dtsi" + +/ { + model = "Netgear Nighthawk XR450"; + compatible = "netgear,xr450", "qcom,ipq8065", "qcom,ipq8064"; + +}; + +&leds { + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&partitions { + partition@1880000 { + label = "ubi"; + reg = <0x1880000 0xce00000>; + }; + + partition@e680000 { + label = "reserve"; + reg = <0xe680000 0x0780000>; + read-only; + }; +}; + +&wifi0 { + nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; + +&wifi1 { + nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-xr500.dts new file mode 100644 index 00000000000..9eef59eaf3d --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-xr500.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8065-nighthawk.dtsi" + +/ { + model = "Netgear Nighthawk XR500"; + compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064"; + +}; + +&leds { + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&partitions { + partition@1880000 { + label = "ubi"; + reg = <0x1880000 0xce00000>; + }; + + partition@e680000 { + label = "reserve"; + reg = <0xe680000 0x0780000>; + read-only; + }; +}; + +&wifi0 { + nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; + +&wifi1 { + nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ap3935.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ap3935.dts new file mode 100644 index 00000000000..f26d026be85 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ap3935.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include +#include +#include + +/ { + model = "Extreme Networks AP3935"; + compatible = "extreme,ap3935", "qcom,ipq8064"; + + memory@0 { + reg = <0x41400000 0x3ec00000>; + device_type = "memory"; + }; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi2_serial; + ethernet0 = &gmac0; + ethernet1 = &gmac2; + + led-boot = &led_power_green; + led-failsafe = &led_power_orange; + led-running = &led_power_green; + led-upgrade = &led_power_green; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "ubi.block=0,0 root=/dev/ubiblock0_0"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; + }; + + led_power_orange: power_orange { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; + }; + + led_wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led_wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_lan1_green { + label = "green:lan1"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + led_lan1_orange { + label = "orange:lan1"; + gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>; + }; + + led_lan2_green { + label = "green:lan2"; + gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; + }; + + led_lan2_orange { + label = "orange:lan2"; + gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>; + }; + }; +}; + + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio22", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27", "gpio28", "gpio29"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio56"; + function = "gpio"; + bias-pull-up; + }; + }; + + rgmii0_pins: rgmii0_pins { + mux { + pins = "gpio2", "gpio66"; + drive-strength = <8>; + bias-disable; + }; + + tx { + pins = "gpio53", "gpio64"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; +}; + +&gsbi2 { + qcom,mode = ; + status = "okay"; + + gsbi2_serial: serial@12490000 { + status = "okay"; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "disabled"; + }; +}; + +&gsbi7 { + qcom,mode = ; + status = "okay"; + + gsbi7_serial: serial@16640000 { + status = "okay"; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cfg1@2a0000 { + compatible = "u-boot,env-redundant-bool"; + label = "CFG1"; + reg = <0x2a0000 0x0010000>; + + ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; + }; + + bootpri@2b0000 { + label = "BootPRI"; + reg = <0x2b0000 0x0080000>; + }; + + cfg2@330000 { + label = "CFG2"; + reg = <0x330000 0x0010000>; + }; + + fs@340000 { + label = "FS"; + reg = <0x340000 0x0080000>; + }; + + priimg@3c0000 { + label = "PriImg"; + reg = <0x3c0000 0x0e10000>; + }; + + secimg@11d0000 { + label = "SecImg"; + reg = <0x11d0000 0x0e10000>; + }; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <8>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubi@0 { + label = "ubi"; + reg = <0x0000000 0x20000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; +}; + +&gmac0 { + status = "okay"; + + qcom,id = <0>; + mdiobus = <&mdio0>; + + pinctrl-0 = <&rgmii0_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + + nvmem-cells = <ðaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy2>; + + nvmem-cells = <ðaddr 1>; + nvmem-cell-names = "mac-address"; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi new file mode 100644 index 00000000000..2e715753317 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +/ { + memory { + device_type = "memory"; + linux,usable-memory = <0x41500000 0x1ea00000>; + reg = <0x40000000 0x20000000>; + }; + + cpus { + idle-states { + CPU_SPC: spc { + status = "disabled"; + }; + }; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art"; + }; +}; + +&qcom_pinmux { + mdio0_pins_active: mdio0_pins_active { + mux { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + + clk { + pins = "gpio1"; + input-disable; + }; + }; + + phy_active: phy_active { + phy { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-high; + }; + }; + + uart1_pins: uart1_pins { + mux { + pins = "gpio51", "gpio52"; + function = "gsbi1"; + drive-strength = <4>; + bias-disable; + }; + }; +}; + +&gsbi1 { + status = "okay"; + qcom,mode = ; + + serial@12450000 { + status = "okay"; + + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + }; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&pcie2 { + status = "okay"; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi2: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot-partitions = <0x0 0x2140000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "sbl1"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "mibib"; + reg = <0x40000 0x140000>; + read-only; + }; + + partition@180000 { + label = "sbl2"; + reg = <0x180000 0x140000>; + read-only; + }; + + partition@2c0000 { + label = "sbl3"; + reg = <0x2c0000 0x280000>; + read-only; + }; + + partition@540000 { + label = "ddrconfig"; + reg = <0x540000 0x120000>; + read-only; + }; + + partition@660000 { + label = "ssd"; + reg = <0x660000 0x120000>; + read-only; + }; + + partition@780000 { + label = "tz"; + reg = <0x780000 0x280000>; + read-only; + }; + + partition@a00000 { + label = "rpm"; + reg = <0xa00000 0x280000>; + read-only; + }; + + partition@1fc0000 { + label = "u-boot"; + reg = <0x1fc0000 0x180000>; + read-only; + }; + + partition@21c0000 { + label = "bootkernel1"; + reg = <0x21c0000 0xa80000>; + }; + + partition@2c40000 { + label = "bootkernel2"; + reg = <0x2c40000 0xa80000>; + }; + + partition@36c0000 { + label = "ubi"; + reg = <0x36c0000 0x46c0000>; + }; + + partition@7d80000 { + label = "art"; + reg = <0x7d80000 0x200000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ecw5410.dts new file mode 100644 index 00000000000..9f6c5fb6969 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ecw5410.dts @@ -0,0 +1,332 @@ +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include +#include + +/ { + model = "Edgecore ECW5410"; + compatible = "edgecore,ecw5410", "qcom,ipq8064"; + + reserved-memory { + nss@40000000 { + reg = <0x40000000 0x1000000>; + no-map; + }; + + smem: smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; + + wifi_dump@44000000 { + reg = <0x44000000 0x600000>; + no-map; + }; + }; + + cpus { + idle-states { + CPU_SPC: spc { + status = "disabled"; + }; + }; + }; + + aliases { + serial1 = &gsbi1_serial; + ethernet0 = &gmac2; + ethernet1 = &gmac3; + + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_green; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; + }; + + wlan2g_yellow { + label = "yellow:wlan2g"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + led_power_red: power_red { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; + }; + + wlan5g_yellow { + label = "yellow:wlan5g"; + gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>; + }; + }; +}; + + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio16", "gpio23", "gpio24", "gpio26", + "gpio28", "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart1_pins: uart1_pins { + mux { + pins = "gpio51", "gpio52", "gpio53", "gpio54"; + function = "gsbi1"; + drive-strength = <12>; + bias-none; + }; + }; +}; + +&gsbi1 { + qcom,mode = ; + status = "okay"; + + serial@12450000 { + status = "okay"; + + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; + }; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; + }; + }; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + rootfs1@0 { + label = "rootfs1"; + reg = <0x0000000 0x4000000>; + }; + + rootfs2@4000000 { + label = "rootfs2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy1>; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr42.dts new file mode 100644 index 00000000000..7ec11de56b6 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr42.dts @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8068-cryptid-common.dtsi" + +#include +#include + +/ { + model = "Meraki MR42"; + compatible = "meraki,mr42", "qcom,ipq8064"; + + aliases { + serial1 = &gsbi1_serial; + ethernet0 = &gmac3; + + led-boot = &led_active; + led-failsafe = &led_power; + led-running = &led_active; + led-upgrade = &led_active; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>; + }; + + led_active: active { + label = "white:active"; + gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy2>; + + nvmem-cells = <&mac_address 0>; + nvmem-cell-names = "mac-address"; +}; + +&gsbi2 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi2_i2c { + status = "okay"; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + ina2xx@40 { + compatible = "ina219"; + shunt-resistor = <40000>; + reg = <0x40>; + }; + + eeprom@56 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x56>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + compatible = "mac-base"; + reg = <0x66 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; +}; + +&gsbi6 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi6_i2c { + status = "okay"; + + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + tlc591xx@40 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x40>; + + red@0 { + label = "red:user"; + reg = <0x0>; + }; + + green@1 { + label = "green:user"; + reg = <0x1>; + }; + + blue@2 { + label = "blue:user"; + reg = <0x2>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; + pinctrl-names = "default"; + + phy2: ethernet-phy2 { + reg = <2>; + + reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&qcom_pinmux { + i2c0_pins: i2c0_pins { + mux { + pins = "gpio24", "gpio25"; + function = "gsbi2"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1_pins { + mux { + pins = "gpio29", "gpio30"; + function = "gsbi6"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio31", "gpio32"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-low; + }; + }; +}; + +&wifi0 { + nvmem-cells = <&mac_address 1>; + nvmem-cell-names = "mac-address"; +}; + +&wifi1 { + nvmem-cells = <&mac_address 2>; + nvmem-cell-names = "mac-address"; +}; + +&wifi2 { + nvmem-cells = <&mac_address 3>; + nvmem-cell-names = "mac-address"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts new file mode 100644 index 00000000000..97b280e2015 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8068-cryptid-common.dtsi" + +#include +#include + +/ { + model = "Meraki MR52"; + compatible = "meraki,mr52", "qcom,ipq8064"; + + aliases { + serial1 = &gsbi1_serial; + mdio-gpio0 = &mdio_gpio0; + ethernet0 = &gmac2; + ethernet1 = &gmac3; + + led-boot = &led_active; + led-failsafe = &led_power; + led-running = &led_active; + led-upgrade = &led_active; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>; + }; + + lan1_green { + label = "green:lan1"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + lan2_green { + label = "green:lan2"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + led_active: active { + label = "white:active"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + lan1_orange { + label = "orange:lan1"; + gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>; + }; + + lan2_orange { + label = "orange:lan2"; + gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&mac_address 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio_gpio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy4>; + + nvmem-cells = <&mac_address 1>; + nvmem-cell-names = "mac-address"; +}; + +&gsbi7 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi7_i2c { + status = "okay"; + + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + + ina2xx@45 { + compatible = "ina219"; + shunt-resistor = <80000>; + reg = <0x45>; + }; + + tlc591xx@49 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x49>; + + red@0 { + label = "red:user"; + reg = <0x0>; + }; + + green@1 { + label = "green:user"; + reg = <0x1>; + }; + + blue@2 { + label = "blue:user"; + reg = <0x2>; + }; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + compatible = "mac-base"; + reg = <0x66 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; +}; + +&qcom_pinmux { + i2c_pins: i2c_pins { + mux { + pins = "gpio8", "gpio9"; + function = "gsbi7"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio19", "gpio26"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-low; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; +}; + +&soc { + mdio_gpio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; + pinctrl-names = "default"; + + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH + &qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + + phy0: ethernet-phy0 { + reg = <0>; + reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + }; + + phy4: ethernet-phy4 { + reg = <4>; + reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + }; + }; +}; + +&wifi0 { + nvmem-cells = <&mac_address 4>; + nvmem-cell-names = "mac-address"; +}; + +&wifi1 { + nvmem-cells = <&mac_address 3>; + nvmem-cell-names = "mac-address"; +}; + +&wifi2 { + nvmem-cells = <&mac_address 2>; + nvmem-cell-names = "mac-address"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ss-w2-ac2600.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ss-w2-ac2600.dts new file mode 100644 index 00000000000..5174927a0f5 --- /dev/null +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ss-w2-ac2600.dts @@ -0,0 +1,309 @@ +#include "qcom-ipq8064-v2.0-smb208.dtsi" + +#include +#include +#include + +/ { + model = "IgniteNet SunSpot AC Wave2"; + compatible = "ignitenet,ss-w2-ac2600", "qcom,ipq8068"; + + aliases { + ethernet0 = &gmac2; + ethernet1 = &gmac3; + + led-boot = &led_power_red; + led-failsafe = &led_power_red; + led-running = &led_power_red; + led-upgrade = &led_power_red; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1"; + }; + + reserved-memory { + nss@40000000 { + reg = <0x40000000 0x1000000>; + no-map; + }; + + smem: smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; + + wifi_dump@44000000 { + reg = <0x44000000 0x600000>; + no-map; + }; + }; + + cpus { + idle-states { + CPU_SPC: spc { + status = "disabled"; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; + }; + + wlan2g_yellow { + label = "yellow:wlan2g"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + led_power_red: power_red { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; + }; + + wlan5g_yellow { + label = "yellow:wlan5g"; + gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio16", "gpio23", "gpio24", "gpio26", + "gpio28", "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + w25q128@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + + art: partition-0-art { + label = "0:art"; + }; + }; + }; + }; +}; + +&art { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "IgniteNet-SS-W2-AC2600"; + nvmem-cells = <&precal_art_1000>; + nvmem-cell-names = "pre-calibration"; + }; + }; +}; + +&pcie2 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "IgniteNet-SS-W2-AC2600"; + nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration"; + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + rootfs1@0 { + label = "rootfs1"; + reg = <0x0000000 0x4000000>; + }; + + rootfs2@4000000 { + label = "rootfs2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy1>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/patches-6.6/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-6.6/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch new file mode 100644 index 00000000000..d70be98aca9 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch @@ -0,0 +1,25 @@ +From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 9 Mar 2017 09:31:44 +0100 +Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting + +Signed-off-by: John Crispin +--- + drivers/mtd/mtdpart.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -57,7 +57,11 @@ static struct mtd_info *allocate_partiti + + /* allocate the partition structure */ + child = kzalloc(sizeof(*child), GFP_KERNEL); +- name = kstrdup(part->name, GFP_KERNEL); ++ /* "rootfs" conflicts with OpenWrt auto mounting */ ++ if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs")) ++ name = "ubi"; ++ else ++ name = kstrdup(part->name, GFP_KERNEL); + if (!name || !child) { + printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n", + parent->name); diff --git a/target/linux/ipq806x/patches-6.6/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-6.6/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch new file mode 100644 index 00000000000..83eb6f38cdb --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch @@ -0,0 +1,69 @@ +From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Mon, 17 Jan 2022 23:39:34 +0100 +Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for + ipq8064 + +Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi. +Also declare clock-output-names for acc0 and acc1 and qsb fixed clock +for the secondary mux. + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +--- + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++-- + 1 file changed, 32 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +@@ -302,6 +302,12 @@ + }; + + clocks { ++ qsb: qsb { ++ compatible = "fixed-clock"; ++ clock-frequency = <225000000>; ++ #clock-cells = <0>; ++ }; ++ + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -587,7 +593,7 @@ + }; + + saw0: regulator@2089000 { +- compatible = "qcom,saw2"; ++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; +@@ -602,11 +608,27 @@ + }; + + saw1: regulator@2099000 { +- compatible = "qcom,saw2"; ++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + ++ saw_l2: regulator@02012000 { ++ compatible = "qcom,saw2", "syscon"; ++ reg = <0x02012000 0x1000>; ++ regulator; ++ }; ++ ++ kraitcc: clock-controller { ++ compatible = "qcom,krait-cc-v1"; ++ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, ++ <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>; ++ clock-names = "hfpll0", "hfpll1", "hfpll_l2", ++ "acpu0_aux", "acpu1_aux", "acpu_l2_aux", ++ "qsb", "pxo"; ++ #clock-cells = <1>; ++ }; ++ + nss_common: syscon@3000000 { + compatible = "syscon"; + reg = <0x03000000 0x0000FFFF>; diff --git a/target/linux/ipq806x/patches-6.6/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch b/target/linux/ipq806x/patches-6.6/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch new file mode 100644 index 00000000000..1cf57d018f1 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch @@ -0,0 +1,268 @@ +From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 18 Jan 2022 00:03:47 +0100 +Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for + ipq8064 + +Add opp table for cpu and l2 cache. While the current cpufreq is +the generic one that doesn't scale the L2 cache, we add the l2 +cache opp anyway for the sake of completeness. This will be handy in the +future when a dedicated cpufreq driver is introduced for krait cores +that will correctly scale l2 cache with the core freq. + +Opp-level is set based on the logic of +0: idle level +1: normal level +2: turbo level + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +--- + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++ + 1 file changed, 99 insertions(+) + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +@@ -49,6 +49,105 @@ + }; + }; + ++ opp_table_l2: opp_table_l2 { ++ compatible = "operating-points-v2"; ++ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <100000>; ++ opp-level = <0>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1150000>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ }; ++ ++ opp_table0: opp_table0 { ++ compatible = "operating-points-v2-kryo-cpu"; ++ nvmem-cells = <&speedbin_efuse>; ++ ++ /* ++ * Voltage thresholds are ++ */ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; ++ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <0>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; ++ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; ++ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ ++ opp-1400000000 { ++ opp-hz = /bits/ 64 <1400000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; ++ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; ++ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ }; ++ + thermal-zones { + sensor0-thermal { + polling-delay-passive = <0>; +--- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi +@@ -6,3 +6,92 @@ + model = "Qualcomm Technologies, Inc. IPQ8065"; + compatible = "qcom,ipq8065", "qcom,ipq8064"; + }; ++ ++&opp_table_l2 { ++ /delete-node/opp-1200000000; ++ ++ opp-1400000000 { ++ opp-hz = /bits/ 64 <1400000000>; ++ opp-microvolt = <1150000>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++}; ++ ++&opp_table0 { ++ /* ++ * On ipq8065 1.2 ghz freq is not present ++ * Remove it to make cpufreq work and not ++ * complain for missing definition ++ */ ++ ++ /delete-node/opp-1200000000; ++ ++ /* ++ * Voltage thresholds are ++ */ ++ opp-384000000 { ++ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; ++ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; ++ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; ++ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; ++ }; ++ ++ opp-600000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; ++ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; ++ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; ++ }; ++ ++ opp-800000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; ++ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; ++ }; ++ ++ opp-1000000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; ++ }; ++ ++ opp-1400000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; ++ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; ++ opp-level = <1>; ++ }; ++ ++ opp-1725000000 { ++ opp-hz = /bits/ 64 <1725000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; ++ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; ++ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; ++ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; ++ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++}; +--- a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi +@@ -6,3 +6,39 @@ + model = "Qualcomm Technologies, Inc. IPQ8062"; + compatible = "qcom,ipq8062", "qcom,ipq8064"; + }; ++ ++&opp_table0 { ++ /delete-node/opp-1200000000; ++ /delete-node/opp-1400000000; ++ ++ /* ++ * Voltage thresholds are ++ */ ++ opp-384000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>; ++ opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>; ++ opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>; ++ }; ++ ++ opp-600000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>; ++ opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>; ++ opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>; ++ }; ++ ++ opp-800000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>; ++ opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>; ++ }; ++ ++ opp-1000000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>; ++ }; ++}; diff --git a/target/linux/ipq806x/patches-6.6/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch b/target/linux/ipq806x/patches-6.6/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch new file mode 100644 index 00000000000..e4c9f73c83e --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch @@ -0,0 +1,154 @@ +From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 18 Jan 2022 00:07:57 +0100 +Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu + and l2 for ipq8064 + +Add multiple binding for cpu node, l2 node and add idle-states +definition for ipq8064 dtsi. + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +--- + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +@@ -30,6 +30,15 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; ++ clocks = <&kraitcc 0>, <&kraitcc 4>; ++ clock-names = "cpu", "l2"; ++ clock-latency = <100000>; ++ operating-points-v2 = <&opp_table0>; ++ voltage-tolerance = <5>; ++ cooling-min-state = <0>; ++ cooling-max-state = <10>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SPC>; + }; + + cpu1: cpu@1 { +@@ -40,12 +49,36 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; ++ clocks = <&kraitcc 1>, <&kraitcc 4>; ++ clock-names = "cpu", "l2"; ++ clock-latency = <100000>; ++ operating-points-v2 = <&opp_table0>; ++ voltage-tolerance = <5>; ++ cooling-min-state = <0>; ++ cooling-max-state = <10>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SPC>; ++ }; ++ ++ idle-states { ++ CPU_SPC: spc { ++ compatible = "qcom,idle-state-spc"; ++ status = "disabled"; ++ entry-latency-us = <400>; ++ exit-latency-us = <900>; ++ min-residency-us = <3000>; ++ }; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; ++ qcom,saw = <&saw_l2>; ++ ++ clocks = <&kraitcc 4>; ++ clock-names = "l2"; ++ operating-points-v2 = <&opp_table_l2>; + }; + }; + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8064.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8064-v2.0.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; +--- a/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8062.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; +--- a/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8065.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; diff --git a/target/linux/ipq806x/patches-6.6/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch b/target/linux/ipq806x/patches-6.6/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch new file mode 100644 index 00000000000..a3ac606ae9e --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch @@ -0,0 +1,29 @@ +From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Wed, 15 Jun 2022 16:47:09 +0200 +Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x + +Fix wrong nand_pings definition for bias-disable pins. + +Signed-off-by: Christian 'Ansuel' Marangi +--- + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +@@ -600,12 +600,9 @@ + }; + + nand_pins: nand_pins { +- mux { ++ disable { + pins = "gpio34", "gpio35", "gpio36", +- "gpio37", "gpio38", "gpio39", +- "gpio40", "gpio41", "gpio42", +- "gpio43", "gpio44", "gpio45", +- "gpio46", "gpio47"; ++ "gpio37", "gpio38"; + function = "nand"; + drive-strength = <10>; + bias-disable; diff --git a/target/linux/ipq806x/patches-6.6/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch b/target/linux/ipq806x/patches-6.6/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch new file mode 100644 index 00000000000..b4aa04d7d25 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch @@ -0,0 +1,304 @@ +From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Wed, 15 Jun 2022 16:59:30 +0200 +Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for + ipq806x + +Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to +correctly use the new tag. + +Signed-off-by: Christian 'Ansuel' Marangi +--- + arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts | 134 +++++++++++----------- + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 14 +++ + 2 files changed, 81 insertions(+), 67 deletions(-) + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts +@@ -25,131 +25,6 @@ + device_type = "memory"; + }; + +- mdio0: mdio-0 { +- status = "okay"; +- compatible = "virtual,mdio-gpio"; +- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, +- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pinctrl-0 = <&mdio0_pins>; +- pinctrl-names = "default"; +- +- switch0: switch@10 { +- compatible = "qca,qca8337"; +- +- dsa,member = <0 0>; +- +- pinctrl-0 = <&sw0_reset_pin>; +- pinctrl-names = "default"; +- +- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; +- reg = <0x10>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch0cpu: port@0 { +- reg = <0>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "rgmii-id"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port@1 { +- reg = <1>; +- label = "sw1"; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- color = ; +- function = LED_FUNCTION_LAN; +- default-state = "keep"; +- }; +- }; +- }; +- +- port@2 { +- reg = <2>; +- label = "sw2"; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- color = ; +- function = LED_FUNCTION_LAN; +- default-state = "keep"; +- }; +- }; +- }; +- +- port@3 { +- reg = <3>; +- label = "sw3"; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- color = ; +- function = LED_FUNCTION_LAN; +- default-state = "keep"; +- }; +- }; +- }; +- +- port@4 { +- reg = <4>; +- label = "sw4"; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- color = ; +- function = LED_FUNCTION_LAN; +- default-state = "keep"; +- }; +- }; +- }; +- +- port@5 { +- reg = <5>; +- label = "sw5"; +- +- leds { +- #address-cells = <1>; +- #size-cells = <0>; +- +- led@0 { +- reg = <0>; +- color = ; +- function = LED_FUNCTION_LAN; +- default-state = "keep"; +- }; +- }; +- }; +- }; +- }; +- }; +- + mdio1: mdio-1 { + status = "okay"; + compatible = "virtual,mdio-gpio"; +@@ -337,6 +212,131 @@ + status = "okay"; + }; + ++&mdio0 { ++ status = "okay"; ++ compatible = "virtual,mdio-gpio"; ++ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, ++ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++ ++ switch0: switch@10 { ++ compatible = "qca,qca8337"; ++ ++ dsa,member = <0 0>; ++ ++ pinctrl-0 = <&sw0_reset_pin>; ++ pinctrl-names = "default"; ++ ++ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; ++ reg = <0x10>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ switch0cpu: port@0 { ++ reg = <0>; ++ label = "cpu"; ++ ethernet = <&gmac0>; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "sw1"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ color = ; ++ function = LED_FUNCTION_LAN; ++ default-state = "keep"; ++ }; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "sw2"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ color = ; ++ function = LED_FUNCTION_LAN; ++ default-state = "keep"; ++ }; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "sw3"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ color = ; ++ function = LED_FUNCTION_LAN; ++ default-state = "keep"; ++ }; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ label = "sw4"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ color = ; ++ function = LED_FUNCTION_LAN; ++ default-state = "keep"; ++ }; ++ }; ++ }; ++ ++ port@5 { ++ reg = <5>; ++ label = "sw5"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ color = ; ++ function = LED_FUNCTION_LAN; ++ default-state = "keep"; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ + &gmac0 { + status = "okay"; + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +@@ -1429,6 +1429,20 @@ + status = "disabled"; + }; + ++ mdio0: mdio@37000000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ compatible = "qcom,ipq8064-mdio", "syscon"; ++ reg = <0x37000000 0x200000>; ++ resets = <&gcc GMAC_CORE1_RESET>; ++ reset-names = "stmmaceth"; ++ clocks = <&gcc GMAC_CORE1_CLK>; ++ clock-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ + gmac0: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; diff --git a/target/linux/ipq806x/patches-6.6/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch b/target/linux/ipq806x/patches-6.6/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch new file mode 100644 index 00000000000..9780f6a30b8 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch @@ -0,0 +1,235 @@ +From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 5 Aug 2020 14:19:23 +0200 +Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver + +Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually +scale the Cache frequency when the CPU frequency is changed. This +devfreq driver register with the cpu notifier and scale the Cache +based on the max Freq across all core as the CPU cache is shared across +all of them. If provided this also scale the voltage of the regulator +attached to the CPU cache. The scaling logic is based on the CPU freq +and the 3 scaling interval are set by the device dts. + +Signed-off-by: Christian Marangi +--- + drivers/devfreq/Kconfig | 11 ++ + drivers/devfreq/Makefile | 1 + + drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++ + 3 files changed, 200 insertions(+) + create mode 100644 drivers/devfreq/krait-cache-devfreq.c + +--- a/drivers/devfreq/Kconfig ++++ b/drivers/devfreq/Kconfig +@@ -150,6 +150,17 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ + This adds the DEVFREQ driver for the MBUS controller in some + Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. + ++config ARM_KRAIT_CACHE_DEVFREQ ++ tristate "Scaling support for Krait CPU Cache Devfreq" ++ depends on ARCH_QCOM || COMPILE_TEST ++ select DEVFREQ_GOV_PASSIVE ++ help ++ This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores. ++ ++ The driver register with the cpufreq notifier and find the right frequency ++ based on the max frequency across all core and the range set in the device ++ dts. If provided this scale also the regulator attached to the l2 cache. ++ + source "drivers/devfreq/event/Kconfig" + + endif # PM_DEVFREQ +--- a/drivers/devfreq/Makefile ++++ b/drivers/devfreq/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) + + obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o + obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o + obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o ++obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o + + # DEVFREQ Event Drivers + obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ +--- /dev/null ++++ b/drivers/devfreq/krait-cache-devfreq.c +@@ -0,0 +1,181 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "governor.h" ++ ++struct krait_cache_data { ++ struct clk *clk; ++ unsigned long idle_freq; ++ int token; ++}; ++ ++static int krait_cache_config_clk(struct device *dev, struct opp_table *opp_table, ++ struct dev_pm_opp *old_opp, struct dev_pm_opp *opp, ++ void *data, bool scaling_down) ++{ ++ struct krait_cache_data *kdata; ++ unsigned long old_freq, freq; ++ unsigned long idle_freq; ++ struct clk *clk; ++ int ret; ++ ++ kdata = dev_get_drvdata(dev); ++ idle_freq = kdata->idle_freq; ++ clk = kdata->clk; ++ ++ old_freq = dev_pm_opp_get_freq(old_opp); ++ freq = dev_pm_opp_get_freq(opp); ++ ++ /* ++ * Set to idle bin if switching from normal to high bin ++ * or vice versa. It has been notice that a bug is triggered ++ * in cache scaling when more than one bin is scaled, to fix ++ * this we first need to transition to the base rate and then ++ * to target rate ++ */ ++ if (likely(freq != idle_freq && old_freq != idle_freq)) { ++ ret = clk_set_rate(clk, idle_freq); ++ if (ret) ++ return ret; ++ } ++ ++ return clk_set_rate(clk, freq); ++}; ++ ++static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq) ++{ ++ struct krait_cache_data *data = dev_get_drvdata(dev); ++ ++ *freq = clk_get_rate(data->clk); ++ ++ return 0; ++}; ++ ++static int krait_cache_target(struct device *dev, unsigned long *freq, ++ u32 flags) ++{ ++ struct dev_pm_opp *opp; ++ ++ opp = dev_pm_opp_find_freq_ceil(dev, freq); ++ if (unlikely(IS_ERR(opp))) ++ return PTR_ERR(opp); ++ ++ dev_pm_opp_put(opp); ++ ++ return dev_pm_opp_set_rate(dev, *freq); ++}; ++ ++static int krait_cache_get_dev_status(struct device *dev, ++ struct devfreq_dev_status *stat) ++{ ++ struct krait_cache_data *data = dev_get_drvdata(dev); ++ ++ stat->busy_time = 0; ++ stat->total_time = 0; ++ stat->current_frequency = clk_get_rate(data->clk); ++ ++ return 0; ++}; ++ ++static struct devfreq_dev_profile krait_cache_devfreq_profile = { ++ .target = krait_cache_target, ++ .get_dev_status = krait_cache_get_dev_status, ++ .get_cur_freq = krait_cache_get_cur_freq ++}; ++ ++static struct devfreq_passive_data devfreq_gov_data = { ++ .parent_type = CPUFREQ_PARENT_DEV, ++}; ++ ++static int krait_cache_probe(struct platform_device *pdev) ++{ ++ struct dev_pm_opp_config config = { }; ++ struct device *dev = &pdev->dev; ++ struct krait_cache_data *data; ++ struct devfreq *devfreq; ++ struct dev_pm_opp *opp; ++ struct clk *clk; ++ int ret, token; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ clk = devm_clk_get(dev, "l2"); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ config.regulator_names = (const char *[]){ "l2", NULL }; ++ config.clk_names = (const char *[]){ "l2", NULL }; ++ config.config_clks = krait_cache_config_clk; ++ ++ token = dev_pm_opp_set_config(dev, &config); ++ if (token < 0) ++ return token; ++ ++ ret = devm_pm_opp_of_add_table(dev); ++ if (ret) ++ goto free_opp; ++ ++ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq); ++ if (IS_ERR(opp)) { ++ ret = PTR_ERR(opp); ++ goto free_opp; ++ } ++ dev_pm_opp_put(opp); ++ ++ data->token = token; ++ data->clk = clk; ++ dev_set_drvdata(dev, data); ++ devfreq = devm_devfreq_add_device(dev, &krait_cache_devfreq_profile, ++ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); ++ if (IS_ERR(devfreq)) { ++ ret = PTR_ERR(devfreq); ++ goto free_opp; ++ } ++ ++ return 0; ++ ++free_opp: ++ dev_pm_opp_clear_config(token); ++ return ret; ++}; ++ ++static int krait_cache_remove(struct platform_device *pdev) ++{ ++ struct krait_cache_data *data = dev_get_drvdata(&pdev->dev); ++ ++ dev_pm_opp_clear_config(data->token); ++ ++ return 0; ++}; ++ ++static const struct of_device_id krait_cache_match_table[] = { ++ { .compatible = "qcom,krait-cache" }, ++ {} ++}; ++ ++static struct platform_driver krait_cache_driver = { ++ .probe = krait_cache_probe, ++ .remove = krait_cache_remove, ++ .driver = { ++ .name = "krait-cache-scaling", ++ .of_match_table = krait_cache_match_table, ++ }, ++}; ++module_platform_driver(krait_cache_driver); ++ ++MODULE_DESCRIPTION("Krait CPU Cache Scaling driver"); ++MODULE_AUTHOR("Christian Marangi "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-6.6/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch b/target/linux/ipq806x/patches-6.6/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch new file mode 100644 index 00000000000..92ff75afe6e --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch @@ -0,0 +1,52 @@ +From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 18:39:21 +0200 +Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi + +Add qcom,krait-cache compatible to enable cache devfreq driver for +ipq806x SoC and move the L2 node to the soc node to make the devfreq +driver correctly probe. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +@@ -69,17 +69,6 @@ + min-residency-us = <3000>; + }; + }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- cache-unified; +- qcom,saw = <&saw_l2>; +- +- clocks = <&kraitcc 4>; +- clock-names = "l2"; +- operating-points-v2 = <&opp_table_l2>; +- }; + }; + + opp_table_l2: opp_table_l2 { +@@ -1392,6 +1381,17 @@ + #reset-cells = <1>; + }; + ++ L2: l2-cache { ++ compatible = "cache", "qcom,krait-cache"; ++ cache-level = <2>; ++ cache-unified; ++ qcom,saw = <&saw_l2>; ++ ++ clocks = <&kraitcc 4>; ++ clock-names = "l2"; ++ operating-points-v2 = <&opp_table_l2>; ++ }; ++ + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; diff --git a/target/linux/ipq806x/patches-6.6/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch b/target/linux/ipq806x/patches-6.6/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch new file mode 100644 index 00000000000..c359eda2a51 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch @@ -0,0 +1,203 @@ +From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 19:56:08 +0200 +Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver + +Add ipq806x fabric scaling driver using the devfreq passive governor. + +Signed-off-by: Christian Marangi +--- + drivers/devfreq/Kconfig | 11 ++ + drivers/devfreq/Makefile | 1 + + drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++ + 3 files changed, 167 insertions(+) + create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c + +--- a/drivers/devfreq/Kconfig ++++ b/drivers/devfreq/Kconfig +@@ -161,6 +161,17 @@ config ARM_KRAIT_CACHE_DEVFREQ + based on the max frequency across all core and the range set in the device + dts. If provided this scale also the regulator attached to the l2 cache. + ++config ARM_IPQ806X_FAB_DEVFREQ ++ tristate "Scaling support for ipq806x Soc Fabric" ++ depends on ARCH_QCOM || COMPILE_TEST ++ select DEVFREQ_GOV_PASSIVE ++ help ++ This adds the DEVFREQ driver for the ipq806x Soc Fabric. ++ ++ The driver register with the cpufreq notifier and find the right frequency ++ based on the max frequency across all core and the range set in the device ++ dts. ++ + source "drivers/devfreq/event/Kconfig" + + endif # PM_DEVFREQ +--- a/drivers/devfreq/Makefile ++++ b/drivers/devfreq/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += + obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o + obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o + obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o ++obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o + + # DEVFREQ Event Drivers + obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ +--- /dev/null ++++ b/drivers/devfreq/ipq806x-fab-devfreq.c +@@ -0,0 +1,155 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "governor.h" ++ ++struct ipq806x_fab_data { ++ struct clk *fab_clk; ++ struct clk *ddr_clk; ++}; ++ ++static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(dev); ++ ++ *freq = clk_get_rate(data->fab_clk); ++ ++ return 0; ++}; ++ ++static int ipq806x_fab_target(struct device *dev, unsigned long *freq, ++ u32 flags) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(dev); ++ struct dev_pm_opp *opp; ++ int ret; ++ ++ opp = dev_pm_opp_find_freq_ceil(dev, freq); ++ if (unlikely(IS_ERR(opp))) ++ return PTR_ERR(opp); ++ ++ dev_pm_opp_put(opp); ++ ++ ret = clk_set_rate(data->fab_clk, *freq); ++ if (ret) ++ return ret; ++ ++ return clk_set_rate(data->ddr_clk, *freq); ++}; ++ ++static int ipq806x_fab_get_dev_status(struct device *dev, ++ struct devfreq_dev_status *stat) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(dev); ++ ++ stat->busy_time = 0; ++ stat->total_time = 0; ++ stat->current_frequency = clk_get_rate(data->fab_clk); ++ ++ return 0; ++}; ++ ++static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = { ++ .target = ipq806x_fab_target, ++ .get_dev_status = ipq806x_fab_get_dev_status, ++ .get_cur_freq = ipq806x_fab_get_cur_freq ++}; ++ ++static struct devfreq_passive_data devfreq_gov_data = { ++ .parent_type = CPUFREQ_PARENT_DEV, ++}; ++ ++static int ipq806x_fab_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ipq806x_fab_data *data; ++ struct devfreq *devfreq; ++ struct clk *clk; ++ int ret; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ clk = devm_clk_get(dev, "apps-fab-clk"); ++ if (IS_ERR(clk)) { ++ dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n"); ++ return PTR_ERR(clk); ++ } ++ ++ clk_prepare_enable(clk); ++ data->fab_clk = clk; ++ ++ clk = devm_clk_get(dev, "ddr-fab-clk"); ++ if (IS_ERR(clk)) { ++ dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n"); ++ goto err_ddr; ++ } ++ ++ clk_prepare_enable(clk); ++ data->ddr_clk = clk; ++ ++ ret = dev_pm_opp_of_add_table(dev); ++ if (ret) { ++ dev_err(dev, "failed to parse fab freq thresholds\n"); ++ return ret; ++ } ++ ++ dev_set_drvdata(dev, data); ++ ++ devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile, ++ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); ++ if (IS_ERR(devfreq)) ++ dev_pm_opp_remove_table(dev); ++ ++ return PTR_ERR_OR_ZERO(devfreq); ++ ++err_ddr: ++ clk_unprepare(data->fab_clk); ++ clk_put(data->fab_clk); ++ return PTR_ERR(clk); ++}; ++ ++static int ipq806x_fab_remove(struct platform_device *pdev) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev); ++ ++ clk_unprepare(data->fab_clk); ++ clk_put(data->fab_clk); ++ ++ clk_unprepare(data->ddr_clk); ++ clk_put(data->ddr_clk); ++ ++ dev_pm_opp_remove_table(&pdev->dev); ++ ++ return 0; ++}; ++ ++static const struct of_device_id ipq806x_fab_match_table[] = { ++ { .compatible = "qcom,fab-scaling" }, ++ {} ++}; ++ ++static struct platform_driver ipq806x_fab_driver = { ++ .probe = ipq806x_fab_probe, ++ .remove = ipq806x_fab_remove, ++ .driver = { ++ .name = "ipq806x-fab-scaling", ++ .of_match_table = ipq806x_fab_match_table, ++ }, ++}; ++module_platform_driver(ipq806x_fab_driver); ++ ++MODULE_DESCRIPTION("ipq806x Fab Scaling driver"); ++MODULE_AUTHOR("Christian Marangi "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-6.6/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch b/target/linux/ipq806x/patches-6.6/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch new file mode 100644 index 00000000000..bbdbedd6c23 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch @@ -0,0 +1,48 @@ +From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 20:03:05 +0200 +Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x + +Add fabric scaling node for ipq806x to correctly scale apps and ddr +fabric clk. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +@@ -170,6 +170,18 @@ + }; + }; + ++ opp_table_fab: opp_table_fab { ++ compatible = "operating-points-v2"; ++ ++ opp-533000000 { ++ opp-hz = /bits/ 64 <533000000>; ++ }; ++ ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ }; ++ }; ++ + thermal-zones { + sensor0-thermal { + polling-delay-passive = <0>; +@@ -1392,6 +1404,13 @@ + operating-points-v2 = <&opp_table_l2>; + }; + ++ fab-scaling { ++ compatible = "qcom,fab-scaling"; ++ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; ++ clock-names = "apps-fab-clk", "ddr-fab-clk"; ++ operating-points-v2 = <&opp_table_fab>; ++ }; ++ + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; diff --git a/target/linux/ipq806x/patches-6.6/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-6.6/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch new file mode 100644 index 00000000000..c30c245d0a5 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch @@ -0,0 +1,47 @@ +From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 02:19:28 +0200 +Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS + +qsb fixed clk may be defined in DTS and correctly passed in the clocks +list. Add related code to handle this and modify the logic to +dynamically read qsb clock frequency. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor + { + struct device *dev = &pdev->dev; + const struct of_device_id *id; +- unsigned long cur_rate, aux_rate; ++ unsigned long cur_rate, aux_rate, qsb_rate; + int cpu; + struct clk_hw *mux, *l2_pri_mux; + struct clk *clk, **clks; +@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor + if (!id) + return -ENODEV; + +- /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ +- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); ++ /* ++ * Per Documentation qsb should be provided from DTS. ++ * To address old implementation, register the fixed clock anyway. ++ * Rate is 1 because 0 causes problems for __clk_mux_determine_rate ++ */ ++ clk = clk_get(dev, "qsb"); ++ if (IS_ERR(clk)) ++ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ++ qsb_rate = clk_get_rate(clk); ++ + if (!id->data) { + clk = clk_register_fixed_factor(dev, "acpu_aux", + "gpll0_vote", 0, 1, 2); diff --git a/target/linux/ipq806x/patches-6.6/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-6.6/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch new file mode 100644 index 00000000000..e2f78f79fb1 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch @@ -0,0 +1,36 @@ +From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 02:24:33 +0200 +Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock + +With some tools it was discovered the real frequency of the qsb fixed +clock. While not 100% correct it's still better than using 1 as a dummy +frequency. +Correctly register the qsb fixed clock with the frequency of 225 MHz +instead of 1. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -25,6 +25,8 @@ enum { + clks_max, + }; + ++#define QSB_RATE 2250000000 ++ + static unsigned int sec_mux_map[] = { + 2, + 0, +@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor + */ + clk = clk_get(dev, "qsb"); + if (IS_ERR(clk)) +- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); ++ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE); + if (IS_ERR(clk)) + return PTR_ERR(clk); + diff --git a/target/linux/ipq806x/patches-6.6/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-6.6/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch new file mode 100644 index 00000000000..d95a63fc44f --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch @@ -0,0 +1,44 @@ +From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 18 Mar 2022 16:12:14 +0100 +Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info + +Replace pr_info() with dev_info() to provide better diagnostics. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor + cur_rate = clk_get_rate(clks[l2_mux]); + aux_rate = 384000000; + if (cur_rate < aux_rate) { +- pr_info("L2 @ Undefined rate. Forcing new rate.\n"); ++ dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); + cur_rate = aux_rate; + } + clk_set_rate(clks[l2_mux], aux_rate); + clk_set_rate(clks[l2_mux], 2); + clk_set_rate(clks[l2_mux], cur_rate); +- pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); ++ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); + for_each_possible_cpu(cpu) { + clk = clks[cpu]; + cur_rate = clk_get_rate(clk); + if (cur_rate < aux_rate) { +- pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); ++ dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); + cur_rate = aux_rate; + } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); + clk_set_rate(clk, cur_rate); +- pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); ++ dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); + } + + of_clk_add_provider(dev->of_node, krait_of_get, clks); diff --git a/target/linux/ipq806x/patches-6.6/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-6.6/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch new file mode 100644 index 00000000000..8f88e069912 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch @@ -0,0 +1,88 @@ +From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 03:33:13 +0200 +Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset + hfpll + +Rework and clean mux reset logic. +Compact it to a for loop to handle both CPU and L2 in one place. +Move hardcoded aux_rate to define and add a new hfpll_rate value to +reset hfpll settings. +Change logic to now reset the hfpll to the lowest value of 600 Mhz and +then restoring the previous frequency. This permits to reset the hfpll if +the primary mux was set to source out of the secondary mux. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++-------------------- + 1 file changed, 23 insertions(+), 27 deletions(-) + +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -25,7 +25,9 @@ enum { + clks_max, + }; + +-#define QSB_RATE 2250000000 ++#define QSB_RATE 225000000 ++#define AUX_RATE 384000000 ++#define HFPLL_RATE 600000000 + + static unsigned int sec_mux_map[] = { + 2, +@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor + { + struct device *dev = &pdev->dev; + const struct of_device_id *id; +- unsigned long cur_rate, aux_rate, qsb_rate; ++ unsigned long cur_rate, qsb_rate; + int cpu; + struct clk_hw *mux, *l2_pri_mux; + struct clk *clk, **clks; +@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor + * two different rates to force a HFPLL reinit under all + * circumstances. + */ +- cur_rate = clk_get_rate(clks[l2_mux]); +- aux_rate = 384000000; +- if (cur_rate < aux_rate) { +- dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); +- cur_rate = aux_rate; +- } +- clk_set_rate(clks[l2_mux], aux_rate); +- clk_set_rate(clks[l2_mux], 2); +- clk_set_rate(clks[l2_mux], cur_rate); +- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); +- for_each_possible_cpu(cpu) { ++ for (cpu = 0; cpu < 5; cpu++) { ++ const char *l2_s = "L2"; ++ char cpu_s[5]; ++ + clk = clks[cpu]; ++ if (!clk) ++ continue; ++ ++ if (cpu < 4) ++ snprintf(cpu_s, 5, "CPU%d", cpu); ++ + cur_rate = clk_get_rate(clk); +- if (cur_rate < aux_rate) { +- dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); +- cur_rate = aux_rate; ++ if (cur_rate < AUX_RATE) { ++ dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n", ++ cpu < 4 ? cpu_s : l2_s); ++ cur_rate = AUX_RATE; + } + +- clk_set_rate(clk, aux_rate); +- clk_set_rate(clk, 2); ++ clk_set_rate(clk, AUX_RATE); ++ clk_set_rate(clk, HFPLL_RATE); + clk_set_rate(clk, cur_rate); +- dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); ++ dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s, ++ clk_get_rate(clk) / 1000); + } + + of_clk_add_provider(dev->of_node, krait_of_get, clks); diff --git a/target/linux/ipq806x/patches-6.6/122-05-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-6.6/122-05-clk-qcom-clk-krait-generilize-div-functions.patch new file mode 100644 index 00000000000..45b94ed649d --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/122-05-clk-qcom-clk-krait-generilize-div-functions.patch @@ -0,0 +1,155 @@ +From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 23 Sep 2022 19:05:39 +0200 +Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions + +Generilize div functions and remove hardcode to a divisor of 2. +This is just a cleanup and permit to make it more clear the settings of +the devisor when used by the krait-cc driver. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++---------------- + drivers/clk/qcom/clk-krait.h | 11 ++++--- + drivers/clk/qcom/krait-cc.c | 7 +++-- + 3 files changed, 42 insertions(+), 33 deletions(-) + +--- a/drivers/clk/qcom/clk-krait.c ++++ b/drivers/clk/qcom/clk-krait.c +@@ -97,53 +97,57 @@ const struct clk_ops krait_mux_clk_ops = + EXPORT_SYMBOL_GPL(krait_mux_clk_ops); + + /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ +-static int krait_div2_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) ++static int krait_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) + { +- req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), req->rate * 2); +- req->rate = DIV_ROUND_UP(req->best_parent_rate, 2); ++ struct krait_div_clk *d = to_krait_div_clk(hw); ++ ++ req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), ++ req->rate * d->divisor); ++ req->rate = DIV_ROUND_UP(req->best_parent_rate, d->divisor); + return 0; + } + +-static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, ++static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { +- struct krait_div2_clk *d = to_krait_div2_clk(hw); ++ struct krait_div_clk *d = to_krait_div_clk(hw); ++ u8 div_val = krait_div_to_val(d->divisor); + unsigned long flags; +- u32 val; +- u32 mask = BIT(d->width) - 1; +- +- if (d->lpl) +- mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; +- else +- mask <<= d->shift; ++ u32 regval; + + spin_lock_irqsave(&krait_clock_reg_lock, flags); +- val = krait_get_l2_indirect_reg(d->offset); +- val &= ~mask; +- krait_set_l2_indirect_reg(d->offset, val); ++ regval = krait_get_l2_indirect_reg(d->offset); ++ ++ regval &= ~(d->mask << d->shift); ++ regval |= (div_val & d->mask) << d->shift; ++ ++ if (d->lpl) { ++ regval &= ~(d->mask << (d->shift + LPL_SHIFT)); ++ regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT); ++ } ++ ++ krait_set_l2_indirect_reg(d->offset, regval); + spin_unlock_irqrestore(&krait_clock_reg_lock, flags); + + return 0; + } + + static unsigned long +-krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) + { +- struct krait_div2_clk *d = to_krait_div2_clk(hw); +- u32 mask = BIT(d->width) - 1; ++ struct krait_div_clk *d = to_krait_div_clk(hw); + u32 div; + + div = krait_get_l2_indirect_reg(d->offset); + div >>= d->shift; +- div &= mask; +- div = (div + 1) * 2; ++ div &= d->mask; + +- return DIV_ROUND_UP(parent_rate, div); ++ return DIV_ROUND_UP(parent_rate, krait_val_to_div(div)); + } + +-const struct clk_ops krait_div2_clk_ops = { +- .determine_rate = krait_div2_determine_rate, +- .set_rate = krait_div2_set_rate, +- .recalc_rate = krait_div2_recalc_rate, ++const struct clk_ops krait_div_clk_ops = { ++ .determine_rate = krait_div_determine_rate, ++ .set_rate = krait_div_set_rate, ++ .recalc_rate = krait_div_recalc_rate, + }; +-EXPORT_SYMBOL_GPL(krait_div2_clk_ops); ++EXPORT_SYMBOL_GPL(krait_div_clk_ops); +--- a/drivers/clk/qcom/clk-krait.h ++++ b/drivers/clk/qcom/clk-krait.h +@@ -25,17 +25,20 @@ struct krait_mux_clk { + + extern const struct clk_ops krait_mux_clk_ops; + +-struct krait_div2_clk { ++struct krait_div_clk { + u32 offset; +- u8 width; ++ u32 mask; ++ u8 divisor; + u32 shift; + bool lpl; + + struct clk_hw hw; + }; + +-#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) ++#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw) ++#define krait_div_to_val(_div) ((_div) / 2) - 1 ++#define krait_val_to_div(_val) ((_val) + 1) * 2 + +-extern const struct clk_ops krait_div2_clk_ops; ++extern const struct clk_ops krait_div_clk_ops; + + #endif +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -86,11 +86,11 @@ static int krait_notifier_register(struc + static struct clk_hw * + krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) + { +- struct krait_div2_clk *div; ++ struct krait_div_clk *div; + static struct clk_parent_data p_data[1]; + struct clk_init_data init = { + .num_parents = ARRAY_SIZE(p_data), +- .ops = &krait_div2_clk_ops, ++ .ops = &krait_div_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; + struct clk_hw *clk; +@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id + if (!div) + return ERR_PTR(-ENOMEM); + +- div->width = 2; ++ div->mask = 0x3; ++ div->divisor = 2; + div->shift = 6; + div->lpl = id >= 0; + div->offset = offset; diff --git a/target/linux/ipq806x/patches-6.6/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-6.6/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch new file mode 100644 index 00000000000..0df29a07877 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch @@ -0,0 +1,31 @@ +From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 5 Jul 2022 18:30:18 +0200 +Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for + pxo and cxo + +Now that these clock are defined as fixed clk in dts, we can drop the +register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/gcc-ipq806x.c | 8 -------- + 1 file changed, 8 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -3386,14 +3386,6 @@ static int gcc_ipq806x_probe(struct plat + struct regmap *regmap; + int ret; + +- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); +- if (ret) +- return ret; +- +- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); +- if (ret) +- return ret; +- + if (of_machine_is_compatible("qcom,ipq8065")) { + ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; + ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; diff --git a/target/linux/ipq806x/patches-6.6/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-6.6/850-soc-add-qualcomm-syscon.patch new file mode 100644 index 00000000000..2d639bbfd38 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/850-soc-add-qualcomm-syscon.patch @@ -0,0 +1,118 @@ +From: Christian Lamparter +Subject: SoC: add qualcomm syscon +--- a/drivers/soc/qcom/Makefile ++++ b/drivers/soc/qcom/Makefile +@@ -26,6 +26,7 @@ obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o + obj-$(CONFIG_QCOM_SPM) += spm.o + obj-$(CONFIG_QCOM_STATS) += qcom_stats.o + obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o ++obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o + obj-$(CONFIG_QCOM_APR) += apr.o + obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o + obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o +--- a/drivers/soc/qcom/Kconfig ++++ b/drivers/soc/qcom/Kconfig +@@ -252,6 +252,13 @@ config QCOM_STATS + various SoC level low power modes statistics and export to debugfs + interface. + ++config QCOM_TCSR ++ tristate "QCOM Top Control and Status Registers" ++ depends on ARCH_QCOM ++ help ++ Say y here to enable TCSR support. The TCSR provides control ++ functions for various peripherals. ++ + config QCOM_WCNSS_CTRL + tristate "Qualcomm WCNSS control driver" + depends on ARCH_QCOM || COMPILE_TEST +--- /dev/null ++++ b/drivers/soc/qcom/qcom_tcsr.c +@@ -0,0 +1,61 @@ ++/* ++ * Copyright (c) 2014, The Linux foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License rev 2 and ++ * only rev 2 as published by the free Software foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TCSR_USB_PORT_SEL 0xb0 ++ ++static int tcsr_probe(struct platform_device *pdev) ++{ ++ const struct device_node *node = pdev->dev.of_node; ++ void __iomem *base; ++ u32 val; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { ++ dev_err(&pdev->dev, "setting usb port select = %d\n", val); ++ writel(val, base + TCSR_USB_PORT_SEL); ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id tcsr_dt_match[] = { ++ { .compatible = "qcom,tcsr", }, ++ { }, ++}; ++ ++MODULE_DEVICE_TABLE(of, tcsr_dt_match); ++ ++static struct platform_driver tcsr_driver = { ++ .driver = { ++ .name = "tcsr", ++ .of_match_table = tcsr_dt_match, ++ }, ++ .probe = tcsr_probe, ++}; ++ ++module_platform_driver(tcsr_driver); ++ ++MODULE_AUTHOR("Andy Gross "); ++MODULE_DESCRIPTION("QCOM TCSR driver"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/include/dt-bindings/soc/qcom,tcsr.h +@@ -0,0 +1,23 @@ ++/* Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#ifndef __DT_BINDINGS_QCOM_TCSR_H ++#define __DT_BINDINGS_QCOM_TCSR_H ++ ++#define TCSR_USB_SELECT_USB3_P0 0x1 ++#define TCSR_USB_SELECT_USB3_P1 0x2 ++#define TCSR_USB_SELECT_USB3_DUAL 0x3 ++ ++/* TCSR A/B REG */ ++#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 ++#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 ++ ++#endif diff --git a/target/linux/ipq806x/patches-6.6/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-6.6/900-arm-add-cmdline-override.patch new file mode 100644 index 00000000000..7ea3c82ffd4 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/900-arm-add-cmdline-override.patch @@ -0,0 +1,37 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1568,6 +1568,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN + + endchoice + ++config CMDLINE_OVERRIDE ++ bool "Use alternative cmdline from device tree" ++ help ++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can ++ be used, this is not a good option for kernels that are shared across ++ devices. This setting enables using "chosen/cmdline-override" as the ++ cmdline if it exists in the device tree. ++ + config CMDLINE + string "Default kernel command string" + default "" +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -1190,6 +1190,17 @@ int __init early_init_dt_scan_chosen(cha + if (p != NULL && l > 0) + strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); + ++ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different ++ * device tree option of chosen/bootargs-override. This is ++ * helpful on boards where u-boot sets bootargs, and is unable ++ * to be modified. ++ */ ++#ifdef CONFIG_CMDLINE_OVERRIDE ++ p = of_get_flat_dt_prop(node, "bootargs-override", &l); ++ if (p != NULL && l > 0) ++ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); ++#endif ++ + handle_cmdline: + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else diff --git a/target/linux/ipq806x/patches-6.6/901-01-ARM-decompressor-support-memory-start-validation-.patch b/target/linux/ipq806x/patches-6.6/901-01-ARM-decompressor-support-memory-start-validation-.patch new file mode 100644 index 00000000000..04e2a0c57e6 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/901-01-ARM-decompressor-support-memory-start-validation-.patch @@ -0,0 +1,75 @@ +From 2f86b9b71a11f86e3d850214ab781ebb17d7260e Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 19 Jan 2024 19:48:30 +0100 +Subject: [PATCH v2 1/2] ARM: decompressor: support memory start validation for + appended DTB + +There is currently a problem with a very specific sets of kernel config +and AUTO_ZRELADDR. + +For the most common case AUTO_ZRELADDR check the PC register and +calculate the start of the physical memory. Then fdt_check_mem_start is +called to make sure the detected value makes sense by comparing it with +what is present in DTB in the memory nodes and if additional fixup are +required with the use of linux,usable-memory-range in the chosen node to +hardcode usable memory range in case some reserved space needs to be +addressed. With the help of this function the right address is +calculated and the kernel correctly decompress and loads. + +Things starts to become problematic when in the mix, +CONFIG_ARM_APPENDED_DTB is used. This is a particular kernel config is +used when legacy systems doesn't support passing a DTB directly and a +DTB is appended at the end of the image. + +In such case, fdt_check_mem_start is skipped in AUTO_ZRELADDR iteration +as the appended DTB can be augumented later with ATAGS passed from the +bootloader (if CONFIG_ARM_ATAG_DTB_COMPAT is enabled). + +The main problem and what this patch address is the fact that +fdt_check_mem_start is never called later when the appended DTB is +augumented, hence any fixup and validation is not done making AUTO_ZRELADDR +detection inconsistent and most of the time wrong. + +Add support in head.S for this by checking if AUTO_ZRELADDR is enabled +and calling fdt_check_mem_start with the appended DTB and the augumented +values permitting legacy device to provide info in DTB instead of +disabling AUTO_ZRELADDR and hardcoding the physical address offsets. + +Signed-off-by: Christian Marangi +Reviewed-by: Geert Uytterhoeven +Reviewed-by: Linus Walleij +--- + arch/arm/boot/compressed/head.S | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/arm/boot/compressed/head.S ++++ b/arch/arm/boot/compressed/head.S +@@ -443,6 +443,28 @@ restart: adr r0, LC1 + add r6, r6, r5 + add r10, r10, r5 + add sp, sp, r5 ++ ++#ifdef CONFIG_AUTO_ZRELADDR ++ /* ++ * Validate calculated start of physical memory with appended DTB. ++ * In the first iteration for physical memory start calculation, ++ * we skipped validating it as it could have been augumented by ++ * ATAGS stored at an offset from the same start of physical memory. ++ * ++ * We now have parsed them and augumented the appended DTB if asked ++ * so we can finally validate the start of physical memory. ++ * ++ * This is needed to apply additional fixup with ++ * linux,usable-memory-range or to make sure AUTO_ZRELADDR detected ++ * the correct value. ++ */ ++ sub r0, r4, #TEXT_OFFSET @ revert to base address ++ mov r1, r8 @ use appended DTB ++ bl fdt_check_mem_start ++ ++ /* Determine final kernel image address. */ ++ add r4, r0, #TEXT_OFFSET ++#endif + dtb_check_done: + #endif + diff --git a/target/linux/ipq806x/patches-6.6/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch b/target/linux/ipq806x/patches-6.6/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch new file mode 100644 index 00000000000..ce46f48fa53 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch @@ -0,0 +1,54 @@ +From 781d7cd4c3364e9d38fa12a342c5ad4c7e33a5ba Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 19 Jan 2024 20:33:10 +0100 +Subject: [PATCH v2 2/2] ARM: decompressor: add option to ignore MEM ATAGs + +Some bootloaders can pass broken MEM ATAGs that provide hardcoded +information about mounted RAM size and physical location. +Example booloader provide RAM of size 1.7Gb but actual mounted RAM +size is 512Mb causing kernel panic. + +Add option CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM to ignore these ATAG +and not augument appended DTB memory node. + +Signed-off-by: Christian Marangi +Acked-by: Linus Walleij +--- + arch/arm/Kconfig | 12 ++++++++++++ + arch/arm/boot/compressed/atags_to_fdt.c | 4 ++++ + 2 files changed, 16 insertions(+) + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1549,6 +1549,18 @@ config ARM_ATAG_DTB_COMPAT + bootloaders, this option allows zImage to extract the information + from the ATAG list and store it at run time into the appended DTB. + ++config ARM_ATAG_DTB_COMPAT_IGNORE_MEM ++ bool "Ignore MEM ATAG information from bootloader" ++ depends on ARM_ATAG_DTB_COMPAT ++ help ++ Some bootloaders can pass broken MEM ATAGs that provide hardcoded ++ information about mounted RAM size and physical location. ++ Example booloader provide RAM of size 1.7Gb but actual mounted RAM ++ size is 512Mb causing kernel panic. ++ ++ Enable this option if MEM ATAGs should be ignored and the memory ++ node in the appended DTB should NOT be augumented. ++ + choice + prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT + default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER +--- a/arch/arm/boot/compressed/atags_to_fdt.c ++++ b/arch/arm/boot/compressed/atags_to_fdt.c +@@ -170,6 +170,10 @@ int atags_to_fdt(void *atag_list, void * + setprop_string(fdt, "/chosen", "bootargs", + atag->u.cmdline.cmdline); + } else if (atag->hdr.tag == ATAG_MEM) { ++ /* Bootloader MEM ATAG are broken and should be ignored */ ++ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM)) ++ continue; ++ + if (memcount >= sizeof(mem_reg_property)/4) + continue; + if (!atag->u.mem.size) diff --git a/target/linux/ipq806x/patches-6.6/901-mtd-spi-nor-n25q064a-wp.patch b/target/linux/ipq806x/patches-6.6/901-mtd-spi-nor-n25q064a-wp.patch new file mode 100644 index 00000000000..93e15bec612 --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/901-mtd-spi-nor-n25q064a-wp.patch @@ -0,0 +1,29 @@ +From 1e019e728800d4033b4b3b1b5570f5da5ed309f2 Mon Sep 17 00:00:00 2001 +From: Brian Norris +Date: Thu, 15 Dec 2022 01:49:20 -0800 +Subject: [PATCH] mtd: spi-nor: micron-st: Add n25q064a WP support + +These flash chips are used on Google / TP-Link / ASUS OnHub devices, and +OnHub devices are write-protected by default (same as any other +ChromeOS/Chromebook system). + +Signed-off-by: Brian Norris +--- +Submitted upstream at: + https://lore.kernel.org/linux-mtd/20240726185825.142733-1-computersforpeace@gmail.com/ + https://patchwork.ozlabs.org/project/linux-mtd/patch/20240726185825.142733-1-computersforpeace@gmail.com/ + + drivers/mtd/spi-nor/micron-st.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/mtd/spi-nor/micron-st.c ++++ b/drivers/mtd/spi-nor/micron-st.c +@@ -183,6 +183,8 @@ static const struct flash_info st_nor_pa + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128) ++ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | ++ SPI_NOR_BP3_SR_BIT6) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256) + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | diff --git a/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch b/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch new file mode 100644 index 00000000000..f501514e0bc --- /dev/null +++ b/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch @@ -0,0 +1,197 @@ +From 13bb6d8dd9138927950a520a288401db82871dc9 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Sun, 21 Jan 2024 23:36:57 +0100 +Subject: [PATCH] ARM: decompressor: support for ATAGs rootblock parsing + +The command-line arguments provided by the boot loader will be +appended to a new device tree property: bootloader-args. + +If there is a property "append-rootblock" in DT under /chosen +and a root= option in bootloaders command line it will be parsed +and added to DT bootargs with the form: XX. + +This is usefull in dual boot systems, to get the current root partition +without afecting the rest of the system. + +Signed-off-by: Adrian Panella +[ reworked to a cleaner patch ] +Signed-off-by: Christian Marangi +--- + arch/arm/Kconfig | 10 +++ + arch/arm/boot/compressed/atags_to_fdt.c | 102 ++++++++++++++++++++++-- + init/main.c | 12 +++ + 3 files changed, 117 insertions(+), 7 deletions(-) + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1578,6 +1578,16 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN + The command-line arguments provided by the boot loader will be + appended to the the device tree bootargs property. + ++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE ++ bool "Append rootblock parsing bootloader's kernel arguments" ++ help ++ The command-line arguments provided by the boot loader will be ++ appended to a new device tree property: bootloader-args. ++ ++ If there is a property "append-rootblock" in DT under /chosen ++ and a root= option in bootloaders command line it will be parsed ++ and added to DT bootargs with the form: XX. ++ + endchoice + + config CMDLINE_OVERRIDE +--- a/arch/arm/boot/compressed/atags_to_fdt.c ++++ b/arch/arm/boot/compressed/atags_to_fdt.c +@@ -4,7 +4,8 @@ + #include + #include "misc.h" + +-#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) || \ ++ defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) + #define do_extend_cmdline 1 + #else + #define do_extend_cmdline 0 +@@ -70,6 +71,83 @@ static uint32_t get_cell_size(const void + return cell_size; + } + ++/** ++ * taken from arch/x86/boot/string.c ++ * local_strstr - Find the first substring in a %NUL terminated string ++ * @s1: The string to be searched ++ * @s2: The string to search for ++ */ ++static char *local_strstr(const char *s1, const char *s2) ++{ ++ size_t l1, l2; ++ ++ l2 = strlen(s2); ++ if (!l2) ++ return (char *)s1; ++ l1 = strlen(s1); ++ while (l1 >= l2) { ++ l1--; ++ if (!memcmp(s1, s2, l2)) ++ return (char *)s1; ++ s1++; ++ } ++ return NULL; ++} ++ ++static char *append_rootblock(char *dest, const char *str, int len, void *fdt) ++{ ++ char *ptr, *end, *tmp; ++ const char *root="root="; ++ const char *find_rootblock; ++ int i, l; ++ const char *rootblock; ++ ++ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l); ++ if (!find_rootblock) ++ find_rootblock = root; ++ ++ /* ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 */ ++ ptr = local_strstr(str, find_rootblock); ++ if (!ptr) ++ return dest; ++ ++ end = strchr(ptr, ' '); ++ end = end ? (end - 1) : (strchr(ptr, 0) - 1); ++ ++ /* Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. */ ++ tmp = strchr(ptr, ','); ++ if (tmp) ++ end = end < tmp ? end : tmp - 1; ++ ++ /* ++ * find partition number ++ * (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ ) ++ */ ++ for (i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); ++ ++ ptr = end + 1; ++ ++ /* if append-rootblock property is set use it to append to command line */ ++ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); ++ if (rootblock != NULL) { ++ if (*dest != ' ') { ++ *dest = ' '; ++ dest++; ++ len++; ++ } ++ ++ if (len + l + i <= COMMAND_LINE_SIZE) { ++ memcpy(dest, rootblock, l); ++ dest += l - 1; ++ ++ memcpy(dest, ptr, i); ++ dest += i; ++ } ++ } ++ ++ return dest; ++} ++ + static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) + { + char cmdline[COMMAND_LINE_SIZE]; +@@ -87,13 +165,23 @@ static void merge_fdt_bootargs(void *fdt + ptr += len - 1; + } + +- /* and append the ATAG_CMDLINE */ + if (fdt_cmdline) { +- len = strlen(fdt_cmdline); +- if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { +- *ptr++ = ' '; +- memcpy(ptr, fdt_cmdline, len); +- ptr += len; ++ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)) { ++ /* ++ * save original bootloader args ++ * and append ubi.mtd with root partition number ++ * to current cmdline ++ */ ++ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); ++ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); ++ } else { ++ /* and append the ATAG_CMDLINE */ ++ len = strlen(fdt_cmdline); ++ if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { ++ *ptr++ = ' '; ++ memcpy(ptr, fdt_cmdline, len); ++ ptr += len; ++ } + } + } + *ptr = '\0'; +--- a/init/main.c ++++ b/init/main.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -931,6 +932,17 @@ void start_kernel(void) + pr_notice("Kernel command line: %s\n", saved_command_line); + /* parameters may set static keys */ + jump_label_init(); ++ ++ /* Show bootloader's original command line for reference */ ++ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) && of_chosen) { ++ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); ++ ++ if(prop) ++ pr_notice("Bootloader command line (ignored): %s\n", prop); ++ else ++ pr_notice("Bootloader command line not present\n"); ++ } ++ + parse_early_param(); + after_dashes = parse_args("Booting kernel", + static_command_line, __start___param,