From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Tue, 7 Mar 2023 15:32:01 +0000 (+0530)
Subject: arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent
X-Git-Tag: v6.2.9~226
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a3fdb601969a8c82e40c8a0998987736fff10555;p=thirdparty%2Fkernel%2Fstable.git

arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent

[ Upstream commit 8ba961d4339c5db0e69ff6627606fe1f34c838e5 ]

The UFS controller on SM8450 supports cache coherency, hence add the
"dma-coherent" property to mark it as such.

Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307153201.180626-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 40348bb6ffcdd..16a73288c1b37 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3658,6 +3658,7 @@
 			power-domains = <&gcc UFS_PHY_GDSC>;
 
 			iommus = <&apps_smmu 0xe0 0x0>;
+			dma-coherent;
 
 			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;