From: Ju-Zhe Zhong Date: Tue, 14 Feb 2023 13:44:05 +0000 (+0800) Subject: RISC-V: Add vwmacc vx C api tests X-Git-Tag: basepoints/gcc-14~1175 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a432d0d9e063940db3e1f117af0b1a9fe2748642;p=thirdparty%2Fgcc.git RISC-V: Add vwmacc vx C api tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwmacc_vx-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c: New test. --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-1.c new file mode 100644 index 000000000000..7e7734a826cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-2.c new file mode 100644 index 000000000000..5aa45facaaa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-3.c new file mode 100644 index 000000000000..a32ae88dd6cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c new file mode 100644 index 000000000000..5c04404a9ccd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_m(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_m(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_m(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_m(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_m(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_m(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_m(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_m(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_m(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_m(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_m(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c new file mode 100644 index 000000000000..12e80effea2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_m(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_m(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_m(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_m(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_m(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_m(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_m(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_m(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_m(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_m(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_m(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_m(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_m(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_m(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_m(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c new file mode 100644 index 000000000000..70c0ab0eafc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_m(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_m(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_m(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_m(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_m(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_m(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_m(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_m(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_m(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_m(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_m(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_m(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_m(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_m(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_m(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c new file mode 100644 index 000000000000..b2dbe45f79f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_mu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c new file mode 100644 index 000000000000..c96e333ff613 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_mu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_mu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_mu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_mu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_mu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_mu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_mu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_mu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_mu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_mu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c new file mode 100644 index 000000000000..474f9f8ba549 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_mu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_mu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_mu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_mu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_mu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_mu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_mu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_mu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_mu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_mu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c new file mode 100644 index 000000000000..f76247e0468f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tu(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tu(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tu(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tu(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tu(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tu(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tu(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tu(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tu(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tu(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tu(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tu(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tu(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tu(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tu(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tu(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tu(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tu(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tu(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tu(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tu(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tu(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tu(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tu(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tu(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tu(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tu(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tu(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tu(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tu(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c new file mode 100644 index 000000000000..ab40661ea6e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tu(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tu(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tu(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tu(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tu(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tu(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tu(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tu(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tu(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tu(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tu(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tu(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tu(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tu(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tu(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tu(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tu(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tu(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tu(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tu(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tu(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tu(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tu(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tu(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tu(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tu(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tu(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tu(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tu(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tu(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c new file mode 100644 index 000000000000..cfe077f4413b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tu(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tu(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tu(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tu(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tu(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tu(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tu(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tu(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tu(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tu(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tu(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tu(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tu(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tu(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tu(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tu(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tu(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tu(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tu(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tu(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tu(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tu(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tu(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tu(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tu(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tu(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tu(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tu(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tu(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tu(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c new file mode 100644 index 000000000000..2797ecaab855 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tum(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c new file mode 100644 index 000000000000..3c3c1c4d9a4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tum(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tum(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tum(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tum(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tum(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tum(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tum(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tum(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tum(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tum(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c new file mode 100644 index 000000000000..3234ccdd8096 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tum(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tum(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tum(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tum(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tum(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tum(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tum(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tum(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tum(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tum(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c new file mode 100644 index 000000000000..557a58e0270f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tumu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c new file mode 100644 index 000000000000..881580006a63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tumu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c new file mode 100644 index 000000000000..412d1db02e39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i16m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i32m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vx_i64m8_tumu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c new file mode 100644 index 000000000000..be51a982ee1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c new file mode 100644 index 000000000000..d03532e2a2b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c new file mode 100644 index 000000000000..e453c47ad51f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c new file mode 100644 index 000000000000..9428b2f3768a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_m(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_m(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_m(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_m(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_m(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_m(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_m(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_m(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_m(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_m(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_m(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c new file mode 100644 index 000000000000..47131a7b56f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_m(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_m(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_m(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_m(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_m(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_m(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_m(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_m(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_m(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_m(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_m(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_m(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_m(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_m(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_m(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c new file mode 100644 index 000000000000..29bd5ee5bd55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_m(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_m(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_m(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_m(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_m(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_m(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_m(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_m(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_m(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_m(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_m(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_m(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_m(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_m(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_m(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c new file mode 100644 index 000000000000..81b12b79f0ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_mu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c new file mode 100644 index 000000000000..9566984203a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_mu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_mu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_mu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_mu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_mu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_mu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_mu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_mu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_mu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_mu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c new file mode 100644 index 000000000000..a6a7f03bc702 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_mu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_mu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_mu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_mu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_mu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_mu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_mu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_mu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_mu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_mu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c new file mode 100644 index 000000000000..ed07cf5e0242 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tu(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tu(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tu(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tu(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tu(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tu(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tu(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tu(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tu(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tu(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tu(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tu(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tu(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tu(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tu(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c new file mode 100644 index 000000000000..257e9e2a7d4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tu(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tu(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tu(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tu(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tu(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tu(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tu(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tu(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tu(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tu(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tu(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tu(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tu(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tu(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tu(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c new file mode 100644 index 000000000000..2ea92d8aa4e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tu(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tu(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tu(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tu(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tu(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tu(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tu(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tu(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tu(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tu(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tu(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tu(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tu(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tu(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tu(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c new file mode 100644 index 000000000000..a03d28d688e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tum(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c new file mode 100644 index 000000000000..73c60a09cd58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tum(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tum(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tum(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tum(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tum(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tum(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tum(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tum(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tum(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tum(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c new file mode 100644 index 000000000000..ee110e0b4a90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tum(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tum(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tum(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tum(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tum(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tum(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tum(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tum(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tum(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tum(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c new file mode 100644 index 000000000000..fbff53e5baa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tumu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c new file mode 100644 index 000000000000..fc9aa0f9a737 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tumu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c new file mode 100644 index 000000000000..bb42e332071d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i16m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i32m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vx_i64m8_tumu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-1.c new file mode 100644 index 000000000000..6b34245d2b0b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-2.c new file mode 100644 index 000000000000..1eafc2a8a159 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-3.c new file mode 100644 index 000000000000..533017da8fba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c new file mode 100644 index 000000000000..387017649984 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_m(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_m(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_m(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_m(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_m(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_m(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_m(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_m(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_m(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_m(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_m(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_m(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_m(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_m(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_m(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c new file mode 100644 index 000000000000..b70ec5aaab1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_m(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_m(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_m(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_m(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_m(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_m(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_m(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_m(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_m(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_m(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_m(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_m(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_m(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_m(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_m(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_m(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_m(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_m(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_m(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_m(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_m(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_m(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_m(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_m(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_m(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_m(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_m(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c new file mode 100644 index 000000000000..a644ed9c2037 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_m(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_m(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_m(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_m(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_m(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_m(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_m(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_m(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_m(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_m(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_m(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_m(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_m(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_m(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_m(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_m(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_m(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_m(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_m(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_m(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_m(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_m(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_m(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_m(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_m(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_m(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_m(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c new file mode 100644 index 000000000000..643a9b9f5781 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_mu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c new file mode 100644 index 000000000000..cae30a96ca90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_mu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_mu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_mu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c new file mode 100644 index 000000000000..a7ca61a588e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_mu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_mu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_mu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c new file mode 100644 index 000000000000..fe97851e9264 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tu(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tu(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tu(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tu(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tu(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tu(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tu(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tu(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tu(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tu(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tu(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tu(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tu(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tu(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tu(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c new file mode 100644 index 000000000000..ff3e8f8ccb4b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tu(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tu(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tu(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tu(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tu(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tu(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tu(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tu(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tu(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tu(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tu(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tu(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tu(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tu(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tu(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c new file mode 100644 index 000000000000..3a75eafbd794 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tu(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tu(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tu(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tu(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tu(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tu(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tu(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tu(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tu(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tu(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tu(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tu(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tu(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tu(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tu(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c new file mode 100644 index 000000000000..c1aa0a50892a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tum(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c new file mode 100644 index 000000000000..c76f9c8c3598 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tum(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tum(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tum(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c new file mode 100644 index 000000000000..ebdf9fe7d858 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tum(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tum(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tum(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c new file mode 100644 index 000000000000..877e9cb08dcc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tumu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c new file mode 100644 index 000000000000..a813edc5c5b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tumu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c new file mode 100644 index 000000000000..131d9199781e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m1_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u16m8_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m1_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u32m8_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m1_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vx_u64m8_tumu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-1.c new file mode 100644 index 000000000000..fa3127836448 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-2.c new file mode 100644 index 000000000000..c125ab92b24f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-3.c new file mode 100644 index 000000000000..c4c7ea8af667 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c new file mode 100644 index 000000000000..413de47fb8d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_m(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_m(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_m(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_m(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_m(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_m(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_m(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_m(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_m(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_m(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_m(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c new file mode 100644 index 000000000000..3e4059ecb6db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_m(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_m(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_m(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_m(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_m(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_m(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_m(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_m(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_m(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_m(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_m(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_m(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_m(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_m(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_m(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c new file mode 100644 index 000000000000..b9308aeff496 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_m(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_m(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_m(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_m(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_m(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_m(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_m(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_m(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_m(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_m(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_m(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_m(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_m(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_m(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_m(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c new file mode 100644 index 000000000000..a8ef46258d7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_mu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c new file mode 100644 index 000000000000..82441ce8deb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_mu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_mu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_mu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_mu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_mu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_mu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_mu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_mu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_mu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_mu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c new file mode 100644 index 000000000000..366414558116 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_mu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_mu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_mu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_mu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_mu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_mu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_mu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_mu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_mu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_mu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c new file mode 100644 index 000000000000..1e0a23d4ee76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tu(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tu(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tu(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tu(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tu(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tu(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tu(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tu(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tu(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tu(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tu(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tu(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tu(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tu(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tu(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tu(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tu(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tu(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tu(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tu(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tu(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tu(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tu(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tu(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tu(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tu(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tu(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tu(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tu(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tu(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c new file mode 100644 index 000000000000..05efc805cd64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tu(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tu(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tu(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tu(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tu(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tu(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tu(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tu(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tu(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tu(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tu(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tu(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tu(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tu(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tu(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tu(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tu(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tu(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tu(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tu(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tu(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tu(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tu(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tu(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tu(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tu(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tu(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tu(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tu(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tu(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c new file mode 100644 index 000000000000..a5b823496802 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tu(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tu(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tu(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tu(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tu(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tu(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tu(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tu(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tu(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tu(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tu(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tu(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tu(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tu(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tu(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tu(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tu(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tu(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tu(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tu(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tu(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tu(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tu(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tu(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tu(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tu(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tu(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tu(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tu(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tu(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c new file mode 100644 index 000000000000..fd667a916a5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tum(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c new file mode 100644 index 000000000000..1529a370235c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tum(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tum(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tum(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tum(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tum(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tum(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tum(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tum(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tum(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tum(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c new file mode 100644 index 000000000000..0a98e435c7ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tum(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tum(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tum(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tum(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tum(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tum(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tum(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tum(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tum(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tum(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c new file mode 100644 index 000000000000..7108409b5e39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tumu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c new file mode 100644 index 000000000000..3bdfccd6737f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tumu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c new file mode 100644 index 000000000000..63d67a98e00f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccus_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccus_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccus_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccus_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccus_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccus_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i16m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccus_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccus_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccus_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccus_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccus_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i32m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccus_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccus_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccus_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccus_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccus_vx_i64m8_tumu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */