From: Greg Kroah-Hartman Date: Mon, 9 Aug 2021 11:23:50 +0000 (+0200) Subject: 4.9-stable patches X-Git-Tag: v4.4.280~22 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a681213c36566aad409a75642c63e30a5d1d3cac;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: perf-x86-amd-don-t-touch-the-amd64_eventsel_hostonly-bit-inside-the-guest.patch --- diff --git a/queue-4.9/perf-x86-amd-don-t-touch-the-amd64_eventsel_hostonly-bit-inside-the-guest.patch b/queue-4.9/perf-x86-amd-don-t-touch-the-amd64_eventsel_hostonly-bit-inside-the-guest.patch new file mode 100644 index 00000000000..50600701994 --- /dev/null +++ b/queue-4.9/perf-x86-amd-don-t-touch-the-amd64_eventsel_hostonly-bit-inside-the-guest.patch @@ -0,0 +1,47 @@ +From df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27 Mon Sep 17 00:00:00 2001 +From: Like Xu +Date: Mon, 2 Aug 2021 15:08:50 +0800 +Subject: perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest + +From: Like Xu + +commit df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27 upstream. + +If we use "perf record" in an AMD Milan guest, dmesg reports a #GP +warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx: + + [] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20) + [] Call Trace: + [] amd_pmu_disable_event+0x22/0x90 + [] x86_pmu_stop+0x4c/0xa0 + [] x86_pmu_del+0x3a/0x140 + +The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host, +while the guest perf driver should avoid such use. + +Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled") +Signed-off-by: Like Xu +Signed-off-by: Peter Zijlstra (Intel) +Reviewed-by: Liam Merwick +Tested-by: Kim Phillips +Tested-by: Liam Merwick +Link: https://lkml.kernel.org/r/20210802070850.35295-1-likexu@tencent.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/events/perf_event.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/x86/events/perf_event.h ++++ b/arch/x86/events/perf_event.h +@@ -771,9 +771,10 @@ void x86_pmu_stop(struct perf_event *eve + + static inline void x86_pmu_disable_event(struct perf_event *event) + { ++ u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); + struct hw_perf_event *hwc = &event->hw; + +- wrmsrl(hwc->config_base, hwc->config); ++ wrmsrl(hwc->config_base, hwc->config & ~disable_mask); + } + + void x86_pmu_enable_event(struct perf_event *event); diff --git a/queue-4.9/series b/queue-4.9/series index 209ef9fdfb9..41d9ed8b7e2 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -19,3 +19,4 @@ pipe-increase-minimum-default-pipe-size-to-2-pages.patch serial-8250-mask-out-floating-16-32-bit-bus-bits.patch mips-malta-do-not-byte-swap-accesses-to-the-cbus-uart.patch pcmcia-i82092-fix-a-null-pointer-dereference-bug.patch +perf-x86-amd-don-t-touch-the-amd64_eventsel_hostonly-bit-inside-the-guest.patch